HD74AC164TELL-E [RENESAS]
AC SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO14, TSSOP-14;
| 型号： | HD74AC164TELL-E |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | AC SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO14, TSSOP-14 移位寄存器 |
| 文件： | 总9页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74AC164/HD74ACT164
Serial-In, Parallel-Out Shift Register
REJ03D0253–0200Z
(Previous ADE-205-373 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC164/HD74ACT164 is a high-speed 8-bit serial-in/parallel-out shift register. Serial data is entered through
a 2-input AND gate synchronous with the Low-to-High transition of the clock. The device features an asynchronous
Master Reset which clears the register, setting all outputs Low independent of the clock.
Features
•
•
Outputs Source/Sink 24 mA
HD74ACT164 has TTL-Compatible Inputs
•
Ordering Information
Part Name
HD74AC164P
HD74AC164FPEL SOP-14 pin (JEITA)
Package Type
Package Code Package Abbreviation Taping Abbreviation (Quantity)
DIP-14 pin
DP-14, -14AV
FP-14DAV
P
—
FP
RP
T
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
HD74AC164RPEL SOP-14 pin (JEDEC) FP-14DNV
HD74AC164TELL TSSOP-14 pin TTP-14DV
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
1
2
3
4
5
6
7
14 VCC
A
B
13 Q
7
6
5
4
Q
0
1
2
3
12
11
Q
Q
Q
Q
Q
10 Q
9
8
MR
CP
GND
(Top view)
Rev.2.00, Jul.16.2004, page 1 of 8
HD74AC164/HD74ACT164
Logic Symbol
A
B
CP
MR Q
0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Pin Names
A, B
CP
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active Low)
MR
Q0 to Q7 Outputs
Functional Description
The HD74AC164/HD74ACT164 is an edge-triggered 8-bit shift register with serial data entry and an output from each
of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an
active High Enable for data entry through the other inputs. An unused input must be tied High.
Each Low-to-High transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical
AND of the two data inputs (A•B) that existed before the rising clock edge. A Low level on the Master Reset (MR)
input overrides all other inputs and clears the register asynchronously, forcing all Q outputs Low.
Mode Select Table
Inputs
A
Outputs
Operating Mode
Reset (Clear)
MR
B
Q0
Q1 to Q7
L to L
L
X
L
X
L
L
L
L
L
H
Shift
H
H
H
H
q0 to q6
q0 to q6
q0 to q6
q0 to q6
L
H
L
H
H
H
H : High Voltage Level
L
:
:
:
Low Voltage Level
Immaterial
X
qn
Lower case letters indicate the state of the referenced input or output one setup time prior to the Low-to-High
clock transition.
Logic Diagram
A
B
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
C
D
C
D
C
D
C
D
C
D
C
D
C
D
CD
CP
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Rev.2.00, Jul.16.2004, page 2 of 8
HD74AC164/HD74ACT164
Absolute Maximum Ratings
Item
Supply voltage
Symbol
VCC
Ratings
–0.5 to 7
Unit
Condition
VI = –0.5V
V
DC input diode current
IIK
–20
mA
mA
V
20
VI = Vcc+0.5V
DC input voltage
VI
–0.5 to Vcc+0.5
DC output diode current
IOK
–50
mA
mA
V
VO = –0.5V
50
VO = Vcc+0.5V
DC output voltage
VO
–0.5 to Vcc+0.5
±50
DC output source or sink current
DC VCC or ground current per output pin
Storage temperature
IO
mA
mA
°C
ICC, IGND
Tstg
±50
–65 to +150
Recommended Operating Conditions: HD74AC164
Item
Symbol
VCC
Ratings
Unit
Condition
Supply voltage
2 to 6
V
Input and output voltage
Operating temperature
VI, VO
Ta
0 to VCC
–40 to +85
8
V
°C
ns/V
Input rise and fall time
(except Schmitt inputs)
tr, tf
VCC = 3.0V
VCC = 4.5 V
VCC = 5.5 V
VIN 30% to 70% VCC
DC Characteristics: HD74AC164
Item
Sym-
bol
Vcc
(V)
Ta = 25°C
Ta = –40 to
+85°C
min. max.
Unit
Condition
min.
2.1
3.15
3.85
—
typ.
1.5
max.
—
Input Voltage
VIH
VIL
3.0
2.1
3.15
3.85
—
—
V
VOUT = 0.1 V or VCC –0.1 V
VOUT = 0.1 V or VCC –0.1 V
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
2.25
2.75
1.50
2.25
2.75
2.99
4.49
5.49
—
—
—
—
—
0.9
1.35
1.65
—
0.9
1.35
1.65
—
—
—
—
—
Output voltage
VOH
2.9
4.4
5.4
2.58
3.94
4.94
—
2.9
4.4
5.4
2.48
3.80
4.80
—
V
VIN = VIL or VIH
IOUT = –50 µA
—
—
—
—
—
—
VIN = VIL or VIH
IOH = –12 mA
—
—
—
IOH = –24 mA
IOH = –24 mA
—
—
—
VOL
0.002 0.1
0.001 0.1
0.001 0.1
0.1
0.1
0.1
0.37
0.37
0.37
±1.0
VIN = VIL or VIH
IOUT = 50 µA
—
—
—
—
—
—
—
—
—
0.32
—
VIN = VIL or VIH
IOL = 12 mA
IOL = 24 mA
IOL = 24 mA
—
0.32
0.32
±0.1
—
—
—
Input leakage
current
IIN
—
—
µA
VIN = VCC or GND
Dynamic output
current*
IOLD
IOHD
ICC
5.5
5.5
5.5
—
—
—
—
—
—
—
86
—
—
80
mA
mA
µA
VOLD = 1.1 V
—
–75
—
VOHD = 3.85 V
Quiescent supply
current
8.0
VIN = VCC or ground
*Maximum test duration 2.0 ms, one output loaded at a time.
Rev.2.00, Jul.16.2004, page 3 of 8
HD74AC164/HD74ACT164
Recommended Operating Conditions: HD74ACT164
Item
Symbol
VCC
Ratings
Unit
Condition
Supply voltage
2 to 6
V
Input and output voltage
Operating temperature
VI, VO
Ta
0 to VCC
–40 to +85
8
V
°C
Input rise and fall time
(except Schmitt inputs)
tr, tf
ns/V
V
V
CC = 4.5V
CC = 5.5V
VIN 0.8 to 2.0 V
DC Characteristics: HD74ACT164
Item
Sym-
bol
VCC
(V)
Ta = 25°C
Ta = –40 to
+85°C
min. max.
Unit
Condition
min.
2.0
2.0
—
typ.
1.5
1.5
1.5
1.5
4.49
5.49
—
max.
—
Input voltage
VIH
VIL
4.5
2.0
2.0
—
—
V
V
V
V
V
OUT = 0.1 V or Vcc–0.1 V
OUT = 0.1 V or Vcc–0.1 V
IN = VIL or VIH
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
5.5
5.5
5.5
5.5
—
—
0.8
0.8
—
0.8
0.8
—
—
—
Output voltage
VOH
4.4
5.4
3.94
4.94
—
4.4
5.4
3.80
4.80
—
IOUT = –50 µA
—
—
—
—
VIN = VIL
IOH = –24 mA
IOH = –24 mA
—
—
—
VOL
0.001 0.1
0.001 0.1
0.1
0.1
0.37
0.37
±1.0
1.5
—
V
IN = VIL or VIH
IOUT = 50 µA
—
—
—
—
—
—
0.6
—
—
—
0.32
—
VIN = VIL
IOL = 24 mA
IOL = 24 mA
—
0.32
±0.1
—
—
Input current
IIN
—
—
µA
VIN = VCC or GND
VIN = VCC–2.1 V
VOLD = 1.1 V
ICC/input current
ICCT
IOLD
IOHD
ICC
—
—
mA
mA
mA
µA
Dynamic output
current*
—
—
86
—
—
–75
—
—
VOHD = 3.85 V
Quiescent supply
current
—
8.0
80
VIN = VCC or ground
*Maximum test duration 2.0 ms, one output loaded at a time.
AC Characteristics: HD74AC164
Ta = +25°C
CL = 50 pF
Typ
Ta = –40°C to +85°C
CL = 50 pF
Item
Maximum clock
frequency
Symbol VCC (V)*1
Min
125
Max
Min
Max
Unit
fmax
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
—
—
100
125
1.0
1.0
1.0
1.0
1.0
1.0
—
—
MHz
ns
150
1.0
1.0
1.0
1.0
1.0
1.0
—
—
Propagation delay
CP to Qn
tPLH
tPHL
tPHL
8.5
6.5
8.5
6.5
9.5
7.5
13.0
10.0
13.0
10.0
16.0
11.5
13.5
10.5
14.5
10.5
18.0
13.5
Propagation delay
CP to Qn
Propagation delay
MR to Qn
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 4 of 8
HD74AC164/HD74ACT164
AC Operating Requirements: HD74AC164
Ta = –40°C
to +85°C
CL = 50 pF
Ta = +25°C
CL = 50 pF
Item
Symbol VCC (V)*1
Typ
Guaranteed Minimum
Unit
Setup time A or B to CP
tsu
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.0
2.0
5.5
6.0
4.5
0.0
0.0
7.0
5.0
2.0
2.0
ns
4.0
0.0
0.0
5.5
4.5
2.0
2.0
Hold time CP to A or B
Pulse width CP or MR
Recovery time MR or CP
th
–1.5
–1.5
2.0
tw
2.0
trec
0.0
0.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Characteristics: HD74ACT164
Ta = +25°C
CL = 50 pF
Ta = –40°C to +85°C
CL = 50 pF
Item
Symbol VCC (V)*1
Min
100
Typ
Max
Min
Max
Unit
Maximum clock
frequency
fmax
5.0
5.0
5.0
5.0
—
—
80
—
MHz
ns
Propagation delay
CP to Qn
tPLH
tPHL
tPHL
1.0
1.0
1.0
9.0
9.0
9.5
11.5
1.0
1.0
1.0
12.5
12.5
14.5
Propagation delay
CP to Qn
11.5
13.0
Propagation delay
MR to Qn
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Operating Requirements: HD74AC164
Ta = –40°C
to +85°C
CL = 50 pF
Ta = +25°C
CL = 50 pF
Item
Symbol VCC (V)*1
Typ
Guaranteed Minimum
Unit
Setup time A or B to CP
Hold time CP to A or B
Pulse width CP or MR
Recovery time MR or CP
tsu
5.0
5.0
5.0
5.0
2.5
0.0
4.5
0.0
7.0
8.0
1.5
8.0
2.0
ns
th
1.5
7.0
2.0
tw
trec
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item
Input capacitance
Symbol
Typ
Unit
Condition
CIN
4.5
pF
pF
VCC = 5.5 V
VCC = 5.0 V
Power dissipation capacitance
CPD
20.0
Rev.2.00, Jul.16.2004, page 5 of 8
HD74AC164/HD74ACT164
Package Dimensions
As of January, 2003
Unit: mm
19.20
20.32 Max
14
8
7
1
1.30
2.39 Max
7.62
+ 0.10
– 0.05
0.25
2.54 ± 0.25
0.48 ± 0.10
0˚ – 15˚
Package Code
JEDEC
JEITA
DP-14
Conforms
Conforms
0.97 g
Mass (reference value)
Unit: mm
19.20
20.32 Max
14
1
8
7
1.30
2.39 Max
7.62
*0.25 ± 0.06
2.54 ± 0.25
*0.48 ± 0.08
0˚ – 15˚
Package Code
JEDEC
JEITA
DP-14AV
Conforms
Conforms
0.97 g
*NI/Pd/AU Plating
Mass (reference value)
Rev.2.00, Jul.16.2004, page 6 of 8
HD74AC164/HD74ACT164
As of January, 2003
Unit: mm
10.06
10.5 Max
8
14
1
7
+ 0.20
7.80
– 0.30
1.42 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
Package Code
JEDEC
FP-14DAV
—
JEITA
Mass (reference value)
Conforms
0.23 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
8.65
9.05 Max
8
14
1
7
+ 0.10
6.10
– 0.30
0.635 Max
1.08
0˚ – 8˚
+ 0.67
1.27
*0.40 ± 0.06
0.60
– 0.20
0.15
M
0.25
Package Code
JEDEC
JEITA
FP-14DNV
Conforms
Conforms
0.13 g
*Ni/Pd/Au plating
Mass (reference value)
Rev.2.00, Jul.16.2004, page 7 of 8
HD74AC164/HD74ACT164
As of January, 2003
Unit: mm
5.00
5.30 Max
14
8
1
7
0.65
1.0
*0.20 ± 0.05
0.13 M
6.40 ± 0.20
0.83 Max
0˚ – 8˚
0.50 ± 0.10
0.10
Package Code
JEDEC
TTP-14DV
—
JEITA
—
*Ni/Pd/Au plating
Mass (reference value)
0.05 g
Rev.2.00, Jul.16.2004, page 8 of 8
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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