HD74ACT112RP-EL [RENESAS]
ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16;
| 型号： | HD74ACT112RP-EL |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16 光电二极管 输出元件 |
| 文件： | 总8页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74AC112/HD74ACT112
Dual JK Negative Edge-Triggered Flip-Flop
REJ03D0244–0200Z
(Previous ADE-205-364 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flip-
flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs
may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum
setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse.
Features
•
•
Outputs Source/Sink 24 mA
HD74ACT112 has TTL-Compatible Inputs
•
Ordering Information: Ex. HD74AC112
Part Name
Package Type
Package Code Pabbreviation (Quantity)
HD74AC112FPEL SOP-16 pin (JEITA) FP-16DAV
HD74AC112RPEL SOP-16 pin (JEDEC) FP-16DNV
000 pcs/reel)
(2,500 pcs/reel)
Notes: 1. Please consult the sales office for the abov
2. The packages with lead-free pins are disal products by adding V at the end of
the package code.
Pin Arrangement
4
5
6
7
8
16 VCC
15 CD1
14 CD2
13 CP2
12 K2
Q1
Q1
11 J2
Q2
10 SD2
9 Q2
GND
(Top view)
Rev.2.00, Jul.16.2004, page 1 of 7
HD74AC112/HD74ACT112
Logic Symbol
4
10
SD1
SD2
11
3
1
2
J1
Q1
J2
Q2
5
6
9
7
CP1
CP2
13
12
K1
Q1
K2
Q2
CD1
CD2
15
14
VCC = Pin16
GND = Pin8
Pin Names
J1, J2, K1, K2
CP1, CP2
CD1, CD2
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active Low)
Direct Set Inputs (Active Low)
SD1, SD2
Q1, Q2, Q1, Q 2 Outputs
Asynchronous Inputs:
Low input to SD sets Q to High level
Low input to CD sets Q to Low level
Clear and Set are independent of clock
Simultaneous Low on CD and SD makes both
Truth Table
Inputs
@ tn
Outputs
@ tn + 1
Q
J
L
L
H
Qn
L
H
H
Qn
tn
tn + 1
H
:
:
:
:
Bit time before c
Bit time after clock
High Voltage Level
L
Low Voltage Level
Rev.2.00, Jul.16.2004, page 2 of 7
HD74AC112/HD74ACT112
Logic Diagram
SD
Q
CD
#CP
CP
J
Q
K
CP
#
CP
CP
CP
#
#
CP
CP
CP
CP
#
CP
Absolute Maximum Ratings
Item
Supply voltage
Symbol
Ratings
Condition
VCC
–0.5 to 7
DC input diode current
IIK
–20
= –0.5V
20
VI = Vcc+0.5V
DC input voltage
VI
–0
DC output diode current
IOK
V
VO = –0.5V
VO = Vcc+0.5V
DC output voltage
VO
DC output source or sink current
DC VCC or ground current per output pin
Storage temperature
IO
mA
mA
°C
Recommended OperatinC112
Item
Ratings
Unit
Condition
Supply voltage
2 to 6
V
Input and output voltag
Operating temperatu
0 to VCC
–40 to +85
8
V
°C
ns/V
Input rise and fall time
(except Schmitt inputs)
tf
VCC = 3.0V
VCC = 4.5 V
VCC = 5.5 V
VIN 30% to 70% VCC
Rev.2.00, Jul.16.2004, page 3 of 7
HD74AC112/HD74ACT112
DC Characteristics: HD74AC112
Item
Sym-
bol
Vcc
(V)
Ta = 25°C
Ta = –40 to
Unit
Condition
+85°C
min.
2.1
3.15
3.85
—
typ.
1.5
max.
—
min.
2.1
3.15
3.85
—
max.
—
Input Voltage
VIH
VIL
3.0
V
VOUT = 0.1 V or VCC –0.1 V
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
2.25
2.75
1.50
2.25
2.75
2.99
4.49
5.49
—
—
—
—
—
0.9
1.35
1.65
—
0.9
1.35
1.65
—
VOUT = 0.1 V or VCC –0.1 V
—
—
—
—
Output voltage
VOH
2.9
4.4
5.4
2.58
3.94
4.94
—
2.9
4.4
5.4
2.48
3.80
4.80
—
V
VIN = VIL or VIH
IOUT = –50 µA
—
—
—
—
—
—
VIN = VIL or VIH
IOH = –12 mA
—
—
—
IOH = –24 mA
IOH = –24 mA
—
—
—
VOL
0.002 0.1
0.001 0.1
0.001 0.1
0.1
0.1
0
N = VIL or VIH
= 50 µA
—
—
—
—
—
—
—
—
—
0.32
—
VIH
IOL = 12 mA
IOL = 24 mA
IOL = 24 mA
—
0.32
0.32
±0.1
—
—
Input leakage
current
IIN
—
= VCC or GND
Dynamic output
current*
IOLD
IOHD
ICC
5.5
5.5
5.5
—
—
—
—
—
mA
µA
VOLD = 1.1 V
VOHD = 3.85 V
Quiescent supply
current
VIN = VCC or ground
*Maximum test duration 2.0 ms, one outp
Recommended OperatiACT112
Item
Ratings
Unit
Condition
Supply voltage
2 to 6
V
V
Input and output volta
Operating temperatur
0 to VCC
–40 to +85
8
°C
ns/V
Input rise and fall time
(except Schmitt inputs)
r, tf
V
V
CC = 4.5V
CC = 5.5V
VIN 0.8 to 2.0 V
Rev.2.00, Jul.16.2004, page 4 of 7
HD74AC112/HD74ACT112
DC Characteristics: HD74ACT112
Item
Sym-
bol
VCC
(V)
Ta = 25°C
Ta = –40 to
Unit
Condition
+85°C
min.
2.0
2.0
—
typ.
1.5
1.5
1.5
1.5
4.49
5.49
—
max.
—
min.
2.0
2.0
—
max.
—
Input voltage
VIH
VIL
4.5
V
V
V
V
OUT = 0.1 V or Vcc–0.1 V
OUT = 0.1 V or Vcc–0.1 V
IN = VIL or VIH
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
5.5
5.5
5.5
5.5
—
—
0.8
0.8
—
0.8
0.8
—
—
—
Output voltage
VOH
4.4
5.4
3.94
4.94
—
4.4
5.4
3.80
4.80
—
V
IOUT = –50 µA
—
—
—
—
VIN = VIL
IOH = –24 mA
IOH = –24 mA
—
—
—
VOL
0.001 0.1
0.001 0.1
0.1
0.1
0.37
0.37
±1.0
1.5
VIN = VIL or VIH
IOUT = 50 µA
—
—
—
—
—
—
0.6
—
—
—
0.32
—
VIN = VIL
IOL = 24 mA
IOL = 24 mA
—
0.32
±0.1
—
—
Input current
IIN
—
—
N = VCC or GND
VCC–2.1 V
.1 V
ICC/input current
ICCT
IOLD
IOHD
ICC
—
—
Dynamic output
current*
—
—
86
—
—
–75
—
V
Quiescent supply
current
—
4.0
r ground
*Maximum test duration 2.0 ms, one output loaded at a time.
AC Characteristics: HD74AC112
= –40°C to +85°C
CL = 50 pF
Item
Maximum clock
frequency
Symbol VCC (
Min
Max
Unit
fmax
3.3
100
125
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
—
—
MHz
ns
.0
1.0
1.0
1.0
—
Propagation delay
tPLH
tPHL
11.0
8.5
9.5
7.0
11.5
9.0
14.0
11.0
14.0
11.0
12.5
9.5
15.0
12.0
15.0
12.0
13.5
10.5
15.5
12.5
CP to Q or Q
Propagation delay
CP to Q or Q
Propagation delay
CD, SD to Q or Q
Propagation delay
CD, SD to Q or Q
14.5
11.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 5 of 7
HD74AC112/HD74ACT112
AC Operating Requirements: HD74AC112
Ta = –40°C
to +85°C
CL = 50 pF
Ta = +25°C
CL = 50 pF
Item
Symbol VCC (V)*1
Typ
Guaranteed Minimum
Unit
Setup time
J or K to CP
Hold time
tsu
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.0
2.0
5.5
6.0
4.5
0.0
0.0
7.0
5.0
3.5
3.0
ns
4.5
0.0
0.0
5.5
4.5
3.5
3.0
th
–1.5
–0.5
2.0
CP to J or K
Pulse width
tw
CP or CD or SD
Recovery time
CD or SD to CP
2.0
trec
1.5
1.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Characteristics: HD74ACT112
Ta = +25°C
CL = 50 pF
°C
Item
Symbol VCC (V)*1
Min
100
Typ
M
Unit
Maximum clock
frequency
fmax
5.0
5.0
5.0
5.0
5.0
—
MHz
ns
Propagation delay
CP to Q or Q
Propagation delay
CP to Q or Q
Propagation delay
CD, SD to Q or Q
Propagation delay
tPLH
tPHL
tPLH
tPHL
1.0
1.0
10
1.0
0
14.0
11.0
13.5
CD, SD to Q or Q
Note: 1. Voltage Range 5.0 is 5
AC Operating Req112
Ta = –40°C
to +85°C
CL = 50 pF
Ta = +25°C
CL = 50 pF
Item
VCC (V)*1
Typ
Guaranteed Minimum
Unit
Setup time
J or K to CP
Hold time
CP to J or K
Pulse width
CP or CD or SD
Recovery time
CD , SD to CP
5.0
5.0
5.0
5.0
2.5
0.0
7.0
8.0
1.5
8.0
3.0
ns
th
1.5
7.0
3.0
tw
4.5
trec
–2.5
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item
Input capacitance
Symbol
Typ
Unit
Condition
CIN
4.5
pF
pF
VCC = 5.5 V
VCC = 5.0 V
Power dissipation capacitance
CPD
35.0
Rev.2.00, Jul.16.2004, page 6 of 7
HD74AC112/HD74ACT112
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
9
16
1
8
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
orms
24 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
+ 0.10
6.10
– 0.30
1.08
Max
0˚ – 8˚
+ 0.67
0.60
– 0.20
*0.40 ± 0.06
0.15
0.25
M
Package Code
JEDEC
JEITA
FP-16DNV
Conforms
Conforms
0.15 g
*Ni/Pd/Au plating
Mass (reference value)
Rev.2.00, Jul.16.2004, page 7 of 7
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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