HD74ACT163FPVEL [RENESAS]
ACT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, LEAD FREE, SOP-16;
| 型号： | HD74ACT163FPVEL |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | ACT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, LEAD FREE, SOP-16 光电二极管 |
| 文件： | 总9页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74ACT161/HD74ACT163
Synchronous Presettable Binary Counter
REJ03D0279–0200Z
(Previous ADE-205-402 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74ACT161 and HD74ACT163 are high-speed synchronous modulo-16 binary counters. They are
synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a
Terminal Count output for versatility in forming synchronous multistage counters. The HD74ACT161 have an
asynchronous Master Reset input that overrides all other inputs and forces the outputs Low. The HD74ACT163 has a
Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset
on the rising edge of the clock.
Features
•
•
•
•
•
Synchronous Counting and Loading
High-Speed Synchronous Expansion
Typical Count Rate of 125 MHz
Outputs Source/Sink 24 mA
HD74ACT161 and HD74ACT163 have TTL-Compatible Inputs
•
Ordering Information: Ex. HD74ACT161
Part Name
Package Type
Package Code Package Abbreviation Taping Abbreviation (Quantity)
HD74ACT161FPEL SOP-16 pin (JEITA) FP-16DAV
HD74ACT161RPEL SOP-16 pin (JEDEC) FP-16DNV
FP
RP
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
1
2
3
4
5
6
16 VCC
15 TC
*R
CP
P0
P1
P2
P3
14
13
Q
0
1
2
3
Q
12 Q
11 Q
CEP 7
10 CET
GND
8
9
PE
(Top view)
Rev.2.00, Jul.16.2004, page 1 of 8
HD74ACT161/HD74ACT163
Logic Symbol
PE P
0
P1
P2
P3
CEP
CET
CP
TC
*R Q
0
Q1
Q2
Q3
*
MR for HD74ACT161
SR for HD74ACT163
Pin Names
CEP
CET
CP
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
MR (HD74ACT161)
Asynchronous Master Reset Input
Synchronous Reset Input
Parallel Data Inputs
Parallel Enable Input
Flip-Flop Outputs
SR (HD74ACT163)
P0 to P3
PE
Q0 to Q3
TC
Terminal Count Output
Functional Description
The HD74ACT161 and HD74ACT163 count in modulo-16 binary sequence. From state 15 (HHHH) they increment to
state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the
Q outputs (except due to Master Reset of the HD74ACT161) occur as a reset of, and synchronous with, the Low-to-
High transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence:
asynchronous reset (HD74ACT161),
synchronous reset (HD74ACT163), parallel load, countup and hold. Five control inputs – Master Reste (MR,
HD74ACT161), Synchronous Reset (SR, HD74ACT163), Parallel Enable (PE), Count Enable Parallel (CEP) and
Count Enable Trickle (CET) – determine the mode of operation, as shown in the Mode Select Table. A Low signal on
MR overrides all other inputs and asynchronously forces all outputs Low. A Low signal on SR overrides counting and
parallel loading and allows all outputs to go Low on the next rising edge of CP. A Low signal on PE overrides counting
and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP.
With PE and MR (HD74ACT161) or SR (HD74ACT163) High, CEP and CET permit counting when both are High.
Conversely, a Low signal on either CEP or CET inhibits counting.
The HD74ACT161 and HD74ACT163 use D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET
inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with
respect to the rising edge of CP, are observed. The Terminal Count (TC) output is High when CET is High and counter
is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET
inputs in two different ways. The TC output is subject to decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers.
Logic Equations: Count Enable = CEP•CET•PE
TC = Q0•Q1•Q2•Q3•CET
Rev.2.00, Jul.16.2004, page 2 of 8
HD74ACT161/HD74ACT163
Mode Select Table
SR*1
PE
CET
CEP
Action on the Rising Clock Edge (
Reset (Clear)
)
L
X
L
X
X
H
L
X
X
H
X
L
H
H
H
H
Load (Pn → Qn)
Count (Increment)
No change (Hold)
No change (Hold)
H
H
H
X
Note: 1. For HD74ACT163
H : High Voltage Level
L : Low Voltage Level
X : Immaterial
State Diagram
0
1
2
3
4
5
6
7
8
15
14
13
12
11
10
9
Block Diagram
P0
P1
P2
P3
PE
’161 ’163
CEP
CET
’163
ONRY
TC
CP
’161
ONRY
CP
CP
D CP
Q
D
Q
CD
DETAIL A
DETAIL A
DETAIL A
Q0
Q0
DETAIL A
MR ’161
’163
SR
Q0
Q1
Q2
Q3
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Rev.2.00, Jul.16.2004, page 3 of 8
HD74ACT161/HD74ACT163
Absolute Maximum Ratings
Item
Supply voltage
Symbol
VCC
Ratings
–0.5 to 7
Unit
Condition
VI = –0.5V
V
DC input diode current
IIK
–20
mA
mA
V
20
VI = Vcc+0.5V
DC input voltage
VI
–0.5 to Vcc+0.5
DC output diode current
IOK
–50
mA
mA
V
VO = –0.5V
50
VO = Vcc+0.5V
DC output voltage
VO
–0.5 to Vcc+0.5
±50
DC output source or sink current
DC VCC or ground current per output pin
Storage temperature
IO
mA
mA
°C
ICC, IGND
Tstg
±50
–65 to +150
Recommended Operating Conditions
Item
Symbol
Ratings
2 to 6
Unit
Condition
Supply voltage
VCC
V
Input and output voltage
Operating temperature
VI, VO
Ta
0 to VCC
–40 to +85
8
V
°C
ns/V
Input rise and fall time
(except Schmitt inputs)
tr, tf
V
V
CC = 4.5V
CC = 5.5V
VIN 0.8 to 2.0 V
DC Characteristics
Item
Sym-
bol
VCC
(V)
Ta = 25°C
Ta = –40 to
Unit
Condition
+85°C
min.
2.0
2.0
—
typ.
1.5
1.5
1.5
1.5
4.49
5.49
—
max.
—
min.
2.0
2.0
—
max.
—
Input voltage
VIH
VIL
4.5
V
V
VOUT = 0.1 V or Vcc–0.1 V
VOUT = 0.1 V or Vcc–0.1 V
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
5.5
5.5
5.5
5.5
—
—
0.8
0.8
—
0.8
0.8
—
—
—
Output voltage
VOH
4.4
5.4
3.94
4.94
—
4.4
5.4
3.80
4.80
—
VIN = VIL or VIH
IOUT = –50 µA
—
—
—
—
VIN = VIL
IOH = –24 mA
—
—
—
IOH = –24 mA
VOL
0.001 0.1
0.001 0.1
0.1
0.1
0.37
0.37
±1.0
1.5
—
VIN = VIL or VIH
IOUT = 50 µA
—
—
—
—
—
—
0.6
—
—
—
0.32
—
VIN = VIL
IOL = 24 mA
IOL = 24 mA
—
0.32
±0.1
—
—
Input current
IIN
—
—
µA
VIN = VCC or GND
VIN = VCC–2.1 V
VOLD = 1.1 V
ICC/input current
ICCT
IOLD
IOHD
ICC
—
—
mA
mA
mA
µA
Dynamic output
current*
—
—
86
—
—
–75
—
—
VOHD = 3.85 V
Quiescent supply
current
—
8.0
80
VIN = VCC or ground
*Maximum test duration 2.0 ms, one output loaded at a time.
Rev.2.00, Jul.16.2004, page 4 of 8
HD74ACT161/HD74ACT163
AC Characteristics: HD74ACT161
Ta = +25°C
CL = 50 pF
Ta = –40°C to +85°C
CL = 50 pF
Item
Symbol VCC (V)*1
Min
115
Typ
Max
Min
Max
Unit
Maximum count
frequency
fmax
5.0
125
—
100
1.0
—
MHz
ns
Propagation delay
CP to Qn (PE Input
HIGH or LOW)
tPLH
5.0
1.0
1.0
5.5
9.5
10.5
11.5
Propagation delay
CP to Qn (PE Input
HIGH or LOW)
tPLH
5.0
6.0
10.5
1.0
ns
Propagation delay
CP to TC
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
5.0
5.0
5.0
5.0
5.0
5.0
1.0
1.0
1.0
1.0
1.0
1.0
7.0
8.0
5.5
6.0
6.0
8.0
11.0
12.5
8.5
1.0
1.0
1.0
1.0
1.0
1.0
12.5
13.5
10.0
10.5
11.0
14.5
ns
ns
ns
ns
ns
ns
Propagation delay
CP to TC
Propagation delay
CET to TC
Propagation delay
CET to TC
9.5
Propagation delay
MR to Qn
Propagation delay
10.0
13.5
MR to TC
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Operating Requirements: HD74ACT161
Ta = –40°C
to +85°C
CL = 50 pF
Ta = +25°C
CL = 50 pF
Item
Symbol VCC (V)*1
tsu
Typ
Guaranteed Minimum
Unit
Set-up time, HIGH or LOW
Pn to CP
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
4.0
9.5
11.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hold time, HIGH or LOW
Pn to CP
th
–5.0
4.0
0
0
Setup time, HIGH or LOW
tsu
th
tsu
th
tsu
th
8.5
–0.5
8.5
–0.5
5.5
0
9.5
–0.5
9.5
–0.5
6.5
0
MR to CP
Hold time, HIGH or LOW
–5.5
4.0
MR to CP
Setup time, HIGH or LOW
PE to CP
Hold time, HIGH or LOW
–5.5
2.5
PE to CP
Setup time, HIGH or LOW
CEP or CET to CP
Hold time, HIGH or LOW
CEP or CET to CP
–3.0
2.0
Clock pulse width (Load)
HIGH or LOW
tw
tw
3.0
3.0
3.5
3.5
Clock pulse width (Count)
HIGH or LOW
2.0
MR pulse width, LOW
Recovery time MR to CP
tw
5.0
5.0
3.0
0
3.0
0
7.5
0.5
ns
ns
trec
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 5 of 8
HD74ACT161/HD74ACT163
Capacitance
Item
Input capacitance
Symbol
CIN
CPD
Typ
Unit
Condition
4.5
pF
pF
VCC = 5.5 V
VCC = 5.0 V
Power dissipation capacitance
45.0
AC Characteristics: HD74ACT163
Ta = +25°C
CL = 50 pF
Ta = –40°C to +85°C
CL = 50 pF
Item
Symbol VCC (V)*1
Min
120
Typ
Max
Min
Max
Unit
Maximum count
frequency
fmax
5.0
128
—
105
1.0
—
MHz
ns
Propagation delay
CP to Qn (PE Input
HIGH or LOW)
tPLH
5.0
1.0
1.0
5.5
10.0
11.0
12.0
Propagation delay
CP to Qn (PE Input
HIGH or LOW)
tPHL
5.0
6.0
11.0
1.0
ns
Propagation delay
CP to TC
tPLH
tPHL
tPLH
tPHL
5.0
5.0
5.0
5.0
1.0
1.0
1.0
1.0
7.0
8.0
5.5
6.0
11.5
13.5
9.0
1.0
1.0
1.0
1.0
13.5
15.0
10.5
11.0
ns
ns
ns
ns
Propagation delay
CP to TC
Propagation delay
CET to TC
Propagation delay
CET to TC
10.0
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Operating Requirements: HD74ACT163
Ta = –40°C
to +85°C
CL = 50 pF
Ta = +25°C
CL = 50 pF
Item
Symbol VCC (V)*1
tsu
Typ
Guaranteed Minimum
Unit
Set-up time, HIGH or LOW
Pn to CP
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
4.0
10.0
12.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hold time, HIGH or LOW
Pn to CP
th
–5.0
4.0
0.5
10.0
–0.5
8.5
–0.5
5.5
0
0.5
Setup time, HIGH or LOW
tsu
th
tsu
th
tsu
th
11.5
–0.5
10.5
0
SR to CP
Hold time, HIGH or LOW
–5.5
4.0
SR to CP
Setup time, HIGH or LOW
PE to CP
Hold time, HIGH or LOW
–5.5
2.5
PE to CP
Setup time, HIGH or LOW
CEP or CET to CP
6.5
0.5
3.5
3.5
Hold time, HIGH or LOW
CEP or CET to CP
–3.0
2.0
Clock pulse width (Load)
HIGH or LOW
tw
tw
3.5
3.5
Clock pulse width (Count)
HIGH or LOW
2.0
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 6 of 8
HD74ACT161/HD74ACT163
Capacitance
Item
Input capacitance
Symbol
CIN
CPD
Typ
Unit
Condition
4.5
pF
pF
VCC = 5.5 V
VCC = 5.0 V
Power dissipation capacitance
45.0
Rev.2.00, Jul.16.2004, page 7 of 8
HD74ACT161/HD74ACT163
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
9
16
1
8
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
Package Code
JEDEC
FP-16DAV
—
JEITA
Mass (reference value)
Conforms
0.24 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
9.9
10.3 Max
9
8
16
1
1.27
+ 0.10
6.10
– 0.30
1.08
0.635 Max
0˚ – 8˚
+ 0.67
0.60
– 0.20
*0.40 ± 0.06
0.15
0.25
M
Package Code
JEDEC
JEITA
FP-16DNV
Conforms
Conforms
0.15 g
*Ni/Pd/Au plating
Mass (reference value)
Rev.2.00, Jul.16.2004, page 8 of 8
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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