HD74AVC16835 [RENESAS]
AVC SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56, TTP-56D;
| 型号： | HD74AVC16835 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | AVC SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56, TTP-56D 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总10页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74AVC16835
18-bit Universal Bus Driver with 3-state Outputs
ADE-205-292 (Z)
Preliminary
1st. Edition
May 1999
Description
The HD74AVC16835 is a 18-bit universal bus driver is operational at 1.2 V to 3.6 V VCC, but designed spe-
cifically for 1.65 V to 3.6 V VCC operation.
Data flow from A to Y is controlled by the output enable (OE) input. The device operates in the transparent
mode when the latch enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high
or low logic level. If LE is low, the A data is stored in the latch/flip flop on the low to high transition of CLK.
When OE is high, the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down, OE should be tied to VCC through a
pullup registor; the minimum value of the registor is determined by the current sinking capability of the driv-
er.
Features
•
•
•
Overvoltage tolerant inputs / outputs allow mixed voltage mode data communications
Ioff feature supports partial power down mode operation
High output current ±12 mA (@VCC = 3.0 V)
Function Table
Inputs
OE
H
L
LE
X
H
H
L
CLK
A
X
L
Output Y
X
Z
L
X
L
X
H
L
H
L
L
↑
L
L
↑
H
X
H
*1
L
L
L or H
Y0
H : High level
L :
Low level
X : Immaterial
Z :
High impedance
↑ :
Low to high transition
HD74AVC16835
Note: 1. Output level before the indicated steady-state input conditions were established, provided that
CLK is high before LE goes low.
Pin Arrangement
NC 1
56 GND
55 NC
2
NC
54
53
52
51
50
A1
Y1
GND
Y2
3
4
GND
A2
5
6
Y3
A3
7
VCC
Y4
VCC
8
49 A4
Y5
A5
9
48
47
46
10
Y6
A6
11
12
13
GND
GND
Y7
45 A7
Y8
A8
44
43
42
Y9 14
A9
Y10
15
16
17
A10
41 A11
A12
Y11
Y12
40
39 GND
38
GND 18
Y13
19
A13
37 A14
20
21
22
23
Y14
Y15
VCC
Y16
A15
VCC
A16
A17
GND
A18
CLK
GND
36
35
34
33
32
31
30
29
Y17 24
25
26
27
GND
Y18
OE
LE 28
(Top view)
2
HD74AVC16835
Absolute Maximum Ratings
Item
Symbol
VCC
VI
Ratings
–0.5 to 4.6
–0.5 to 4.6
–0.5 to 4.6
–0.5 to VCC+0.5
–50
Unit
V
Conditions
Supply voltage range
Input voltage range *1
Output voltage range *1, 2
V
VO
V
Output “Z” or VCC : OFF
Output “H” or “L”
VI < 0
Input clamp current
IIK
mA
mA
mA
mA
W
Output clamp current
Continuous output current
VCC, GND current / pin
IOK
–50
VO < 0 or VO > VCC
VO = 0 to VCC
IO
±50
ICC or IGND
PT
±100
Maximum power dissipation
1
TSSOP
at Ta = 55°C (in still air) *3
Storage temperature range
Tstg
–65 to 150
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those indicated under “recommended operating condition” is not implied. Exposure to absolute-maximum-
rated conditions for extended periods may affect device reliability.
Notes: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. The input and output positive-voltage ratings may be exceeded up to 4.6 V if the input and output
clamp-current ratings are observed.
3. The maximum power dissipation is calculated using a junction temperature of 150°C and board
trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol
Min
1.65
0.2
0
Max
3.6
—
Unit
Conditions
Supply voltage
VCC
V
Operating
Data retention only
Input voltage
VI
3.6
VCC
3.6
–4
–8
–12
4
V
V
Output voltage
VO
0
Active state
0
3–state
Static high-level output current *1
Static low-level output current *1
IOHS
—
—
—
—
—
—
—
–40
mA
mA
VCC = 1.65 to 1.95 V
VCC = 2.3 to 2.7 V
VCC = 3 to 3.6 V
VCC = 1.65 to 1.95 V
VCC = 2.3 to 2.7 V
VCC = 3 to 3.6 V
VCC = 1.65 to 3.6 V
IOLS
8
12
5
Input transition rise or fall rate
Operating free-air temperature
∆t/∆v
ns/V
Ta
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
Note: 1. Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5 V
VCC
.
3
HD74AVC16835
Logic Diagram
27
OE
30
CLK
28
LE
54
A1
1D
C1
3
Y1
CLK
To 17 Other Channels
Electrical Characteristics
Ta = –40 to 85°C
Item
Symbol
VCC (V)
Min
Max
—
Unit
Test Conditions
Input voltage
VIH
1.2
VCC
0.65×VC
C
V
1.65 to
1.95
—
2.3 to 2.7 1.7
3.0 to 3.6 2.0
—
—
VIL
1.2
—
—
GND
0.35×VC
V
1.65 to
1.95
C
2.3 to 2.7
3.0 to 3.6
—
—
0.7
0.8
Output voltage
VOH
VOL
IIN
1.65 to 3.6 VCC–0.2 —
V
IOHS = –100 µA
1.65
2.3
1.2
—
IOHS = –4 mA, VIH = 1.07 V
IOHS = –8 mA, VIH = 1.7 V
IOHS = –12 mA, VIH = 2.0 V
IOLS = 100 µA
1.75
2.3
—
3.0
—
1.65 to 3.6 —
0.2
0.45
0.55
0.7
±2.5
V
1.65
2.3
3.0
3.6
—
—
—
—
IOLS = 4 mA, VIL = 0.57 V
IOLS = 8 mA, VIL = 0.7 V
IOLS = 12 mA, VIL = 0.8 V
VIN = VCC or GND
Input current
µA
4
HD74AVC16835
Ta = –40 to 85°C
Item
Symbol
VCC (V)
0
Min
—
Max
±10
±10
40
Unit
µA
Test Conditions
Output leak current
Ioff
VIN = 0 or 3.6 V
Off state output current IOZ
3.6
—
µA
VOUT = VCC or GND
VIN = VCC or GND, IO = 0
Quiescent supply
current
ICC
3.6
—
µA
Switching Characteristics (Ta = –40 to 85°C)
VCC = 1.2 VCC = 1.5 VCC = 1.8 VCC = 2.5 VCC = 3.3
±0.1 V ±0.15 V ±0.2 V ±0.3 V
Min Max Min Max Min Max Min Max Min Max Unit (Input) (Output)
V
Sym-
bol
FROM TO
Item
Maximum fmax
Clock
225
300
300
MHz
frequency
Propagatio tPLH
/
ns
A
Y
n delay
time
tPHL
LE
CLK
Output
enable
time
tZH / tZL
ns OE
Y
Y
Output
disable
time
tHZ / tLZ
ns OE
Switching Characteristics (Ta = –40 to 85°C)
V
V
CC = 1.2 VCC = 1.5 VCC = 1.8 VCC = 2.5 VCC = 3.3
±0.1 V ±0.15 V ±0.2 V ±0.3 V
Sym-
bol
Item
Min Max Min Max Min Max Min Max Min Max Unit Conditions
225 300 300 MHz
Clock
fclock
frequency
Setup time tsu
ns Data before CLK↑
Data
before
LE↓
CLK
“H”
CLK
“L”
Hold time th
ns Data after CLK↑
Data after CLK
LE↓
“H” or
“L”
Pulse
width
tw
ns LE “H”
CLK “H” or “L”
5
HD74AVC16835
Switching Characteristics (Ta = 0 to 85°C, C = 0 pF)
L
FROM
TO
Item
Symbol VCC (V)
Min
Max
Unit (Input)
(Output)
Propagation
tPLH
tPHL
/
3.3±0.15
ns
A
Y
delay time
3.3±0.15
CLK
Operating Characteristics (Ta = 25°C)
V
CC=1.8V VCC=2.5 V VCC=3.3 V
Sym-
bol
Item
Typ
Typ
Typ
Unit Test Conditions
Power dissipation Outputs
enabled
Cpd
pF
CL = 0, f = 10 MHz
capacitance
Outputs
disabled
Test Circuit
2 × VCC
RL
S1
From output
under test
OPEN
GND
*1
CL
RL
Load Circuit for Outputs
Vcc=2.5±0.2 V,
3.3±0.3 V
Vcc=1.2 V
Vcc=1.5±0.1 V Vcc=1.8±0.15 V
Symbol
tPLH/ tPHL
tZH/ tHZ
tZL / tLZ
CL
OPEN
2 × VCC
GND
OPEN
2 × VCC
GND
OPEN
2 × VCC
GND
OPEN
2 × VCC
GND
15 pF
2.5 kΩ
15 pF
2 kΩ
30 pF
1 kΩ
30 pF
500 Ω
RL
Note: 1. CL includes probe and jig capacitance.
6
HD74AVC16835
Waveforms – 1
tr
tf
VCC
0 V
90 %
VCC / 2
90 %
VCC / 2
Input
10 %
10 %
tPHL
tPLH
VOH
Output
VCC / 2
VCC / 2
VOL
Waveforms – 2
tr
VCC
90 %
VCC / 2
Timing Input
Data Input
10 %
tsu
0 V
th
VCC
VCC / 2
VCC / 2
0 V
tw
VCC
0 V
VCC / 2
VCC / 2
Input
7
HD74AVC16835
Waveforms – 3
tf
tr
VCC
90 %
VCC / 2
90 %
VCC / 2
Output
Control
10 %
tZL
10 %
0 V
tLZ
VCC
VCC / 2
tZH
Waveform – A
Waveform – B
Vref1
VOL
VOH
tHZ
Vref2
VCC / 2
0 V
Vcc=1.2 V, Vcc=1.8±0.15 V,
Vcc=3.3±0.3 V
TEST
1.5±0.1 V
2.5±0.2 V
Vref1
Vref2
VOL +0.1 V VOL +0.15 V VOL +0.3 V
VOH–0.1 V VOH–0.15 V VOH–0.3 V
Notes: 1. All input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, Zo = 50 W, tr ≤ 2.0 ns, tf ≤ 2.0 ns.
2. Waveform–A is for an output with internal conditions such that the output is low except when
disabled by the output control.
3. Waveform–B is for an output with internal conditions such that the output is high except when
disabled by the output control.
4. The outputs are measured one at a time with one transition per measurement.
8
HD74AVC16835
Package Dimensions
Unit : mm
+0.3
–0.1
14.00
56
29
28
1
0.50
+0.1
–0.05
M
0.08
0.20
8.10 ± 0.3
0.40 Max
10° Max
0.50 ± 0.1
0.10
Hitachi code
EIAJ code
JEDEC code
TTP-56D
—
—
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copy-
right, trademark, or other intellectual property rights for information contained in this document. Hitachi
bears no responsibility for problems that may arise with third party’s rights, including intellectual property
rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have re-
ceived the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, con-
tact Hitachi’s sales office before using the product in an application that demands especially high quality
and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily
injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety
equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions
and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or fail-
ure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equip-
ment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due
to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
9
HD74AVC16835
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor prod-
ucts.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
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For further information write to:
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Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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