HD74HC76FPEL-E [RENESAS]
IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,SOP,14PIN,PLASTIC;
| 型号： | HD74HC76FPEL-E |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,SOP,14PIN,PLASTIC |
| 文件： | 总7页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74HC76
Dual J-K Flip-Flops (with Preset and Clear)
REJ03D0551-0200
(Previous ADE-205-423)
Rev.2.00
Oct 06, 2005
Description
Each flip-flop has independent J, K, preset, clear, and clock inputs and Q and Q outputs. This device is edge sensitive
to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent
of the clock and accomplished by a low logic level on the corresponding input.
Features
•
•
•
•
•
•
High Speed Operation: tpd (Clock to Q) = 21 ns typ (CL = 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)
Ordering Information
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
Part Name
Package Type
DILP-16 pin
SOP-16 pin (JEITA)
PRDP0016AE-B
(DP-16FV)
HD74HC76P
P
—
PRSP0016DH-B
(FP-16DAV)
HD74HC76FPEL
FP
EL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
Outputs
Preset
Clear
H
Clock
J
X
X
X
L
K
X
X
X
L
Q
Q
L
L
H
L
X
X
X
H
L
L
H*1
H
H*1
L
H
H
H
H
H
H
H
H
No change
L
H
L
H
L
H
L
H
H
H
X
X
X
H
H
H
X
X
X
Toggle
No change
No change
No change
H
L
H
H
H
H :
L :
X :
High level
Low level
Irrelevant
Note: 1. Q and Q will remain High as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset and
Clear go High simultaneously.
Rev.2.00, Oct 06, 2005 page 1 of 6
HD74HC76
Pin Arrangement
1CK
1PR
1CLR
1J
1
2
3
4
5
6
7
8
16 1K
15 1Q
14 1Q
13 GND
12 2K
11 2Q
10 2Q
9 2J
J
K
CK
PR
CLR
Q
Q
VCC
K
J
CK
2CK
2PR
2CLR
CLR
PR
Q
Q
(Top view)
Logic Diagram (1/2)
PR
Q
CLR
J
CK
#
CK
Q
K
CK
#
CK
CK
CK
#
#
CK
CK
CK
CK
#
CK
Absolute Maximum Ratings
Item
Supply voltage range
Input / Output voltage
Input / Output diode current
Output current
Symbol
VCC
Ratings
Unit
V
–0.5 to 7.0
–0.5 to VCC +0.5
±20
Vin, Vout
IIK, IOK
IO
V
mA
mA
mA
mW
°C
±25
VCC, GND current
ICC or IGND
PT
±50
Power dissipation
500
Storage temperature
Tstg
–65 to +150
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Rev.2.00, Oct 06, 2005 page 2 of 6
HD74HC76
Recommended Operating Conditions
Item
Supply voltage
Symbol
VCC
Ratings
2 to 6
Unit
V
Conditions
Input / Output voltage
Operating temperature
VIN, VOUT
Ta
0 to VCC
–40 to 85
0 to 1000
0 to 500
0 to 400
V
°C
VCC = 2.0 V
VCC = 4.5 V
Input rise / fall time*1
tr, tf
ns
VCC = 6.0 V
Note: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Ta = 25°C
Typ Max
Ta = –40 to+85°C
Item
Symbol VCC (V)
VIH
Unit
Test Conditions
Min
1.5
3.15
4.2
—
Min
1.5
3.15
4.2
—
Max
—
Input voltage
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
—
—
—
—
V
V
V
—
—
—
—
VIL
—
0.5
1.35
1.8
—
0.5
1.35
1.8
—
—
—
—
—
—
—
Output voltage
VOH
1.9
4.4
5.9
4.18
5.68
—
2.0
4.5
6.0
—
1.9
4.4
5.9
4.13
5.63
—
Vin = VIH or VIL IOH = –20 µA
—
—
—
—
—
—
IOH = –4 mA
IOH = –5.2 mA
—
—
—
VOL
0.0
0.0
0.0
—
0.1
0.1
0.1
0.26
0.26
±0.1
2.0
0.1
0.1
0.1
0.33
0.33
±1.0
20
V
Vin = VIH or VIL IOL = 20 µA
—
—
—
—
—
—
IOL = 4 mA
—
—
—
IOL = 5.2 mA
Input current
Iin
—
—
—
µA Vin = VCC or GND
Quiescent supply
current
ICC
—
—
—
µA Vin = VCC or GND, Iout = 0 µA
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C
Typ Max
Ta = –40 to +85°C
Item
Symbol VCC (V)
Unit
Test Conditions
Min
—
—
—
—
—
—
—
—
—
—
—
—
Min
—
—
—
—
—
—
—
—
—
—
—
—
Max
5
Maximum clock
frequency
fmax
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
—
—
—
—
21
—
—
17
—
—
19
—
6
MHz
30
24
35
28
Propagation delay tPLHt, tPHL
time
150
30
190
38
ns Clock to Q or Q
ns Clear to Q or Q
ns Preset to Q or Q
26
33
140
28
175
35
24
30
140
28
175
35
24
30
Rev.2.00, Oct 06, 2005 page 3 of 6
HD74HC76
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C
Typ Max
Ta = –40 to +85°C
Item
Symbol VCC (V)
tw
Unit
Test Conditions
Min
80
16
14
100
20
17
0
Min
100
20
17
125
25
21
0
Max
—
—
—
—
—
—
—
—
—
—
—
—
95
19
16
10
Pulse width
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
—
—
6
—
—
—
—
—
—
—
—
—
—
—
—
75
15
13
10
ns Preset, Clear, Clock
ns J or K to Clock
ns Clock to J or K
ns Preset or Clear to Clock
ns
—
—
4
Setup time
Hold time
tsu
—
—
–3
—
—
–2
—
—
5
th
0
0
0
0
Removal time
trem
100
20
17
—
—
—
—
125
25
21
—
Output rise/fall
time
tTLH, tTHL
—
—
5
—
Input capacitance
Cin
—
pF
Test Circuit
VCC
Input
Input
VCC
Output
Preset
Q
Clock
J
Pulse generator
Zout
CL = 50 pF
Ω
= 50
Output
K
Q
Pulse generator
Zout
Clear
Ω
= 50
CL = 50 pF
Note: CL includes the probe and jig capacitance.
Rev.2.00, Oct 06, 2005 page 4 of 6
HD74HC76
Waveforms
• Waveform − 1
tr
tf
tw (L)
VCC
0 V
VOH
VOL
90 %
Clock
50 % 50 %
tw (H)
50 %
50 %
10 %
10 %
tTLH
tTHL
90 %
50 %
90 %
50 %
10 %
Q
10 %
90 %
tPLH
tPHL
tPHL
tPLH
VOH
Q
50 %
10 %
50 %
10 %
VOL
tTLH
tTHL
• Waveform − 2
tf
tr
VCC
90 %
90 %
50 %
10 %
Clear
50 %
10 %
0 V
tw(clear)
tf
tr
VCC
90 %
90 %
Preset
50 %
50 %
10 %
0 V
tw(preset)
tPHL
tPLH
VOH
90 %
50 %
10 %
Q
50 %
VOL
tTHL
tPLH
tPHL
VOH
90 %
50 %
50 %
Q
10 %
VOL
tTLH
Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns
2. The output are measured one at a time with one transition per measurement.
Rev.2.00, Oct 06, 2005 page 5 of 6
HD74HC76
Package Dimensions
JEITA Package Code
P-DIP16-6.3x19.2-2.54
RENESAS Code
Previous Code
DP-16FV
MASS[Typ.]
1.05g
PRDP0016AE-B
D
16
9
1
8
b 3
0.89
Z
Dimension in Millimeters
Reference
Symbol
Min
Nom
7.62
19.2
6.3
Max
e
1
D
20.32
7.4
E
A
5.06
A 1
0.51
0.40
b
0.48
1.30
0.25
0.56
p
bp
e
c
b
3
c
θ
0.19
0.31
e 1
0
°
15°
e
Z
L
2.29
2.54
2.54
2.79
1.12
( Ni/Pd/Au plating )
JEITA Package Code
RENESAS Code
PRSP0016DH-B
Previous Code
FP-16DAV
MASS[Typ.]
0.24g
P-SOP16-5.5x10.06-1.27
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
*1
D
F
16
9
bp
Index mark
Dimension in Millimeters
Reference
Symbol
Min
Nom
10.06
5.50
Max
10.5
Terminal cross section
( Ni/Pd/Au plating )
D
E
1
8
bp
A 2
A 1
A
*3
e
0.00
0.34
0.15
0.10
0.40
0.20
0.20
2.20
0.46
Z
x
M
L1
b p
b 1
c
0.25
c
1
θ
H E
e
0
°
8°
7.50
7.80
1.27
8.00
y
x
0.12
0.15
0.80
0.90
L
y
Z
Detail F
L
0.50
0.70
1.15
L
1
Rev.2.00, Oct 06, 2005 page 6 of 6
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> 2-796-3115, Fax: <82> 2-796-2145
Renesas Technology Malaysia Sdn. Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .3.0
相关型号：
HD74HC76P
J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, DP-16
HITACHI
HD74HC76P-E
HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, 6.30 X 19.20 MM, 2.54 MM PITCH, PLASTIC, DIP-16
RENESAS
HD74HC76RP
J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, FP-16DN
HITACHI
HD74HC76RP-EL
J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, FP-16DN
HITACHI
HD74HC77FP-EL
D Latch, HC/UH Series, 2-Func, High Level Triggered, 2-Bit, True Output, CMOS, PDSO14, FP-14DA
HITACHI
©2020 ICPDF网 联系我们和版权申明