HD74LS163AFPEL [RENESAS]
Synchronous 4-bit Binary Counter (direct clear); 同步4位二进制计数器（直接清除）
| 型号： | HD74LS163AFPEL |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Synchronous 4-bit Binary Counter (direct clear) |
| 文件： | 总12页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74LS163A
Synchronous 4-bit Binary Counter (direct clear)
REJ03D0447–0200
Rev.2.00
Feb.18.2005
This synchronous 4-bit binary counter features an internal carry look-ahead for application in high-speed counting
designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes
coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation
eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This
counter is fully programmable; that is, the output may be preset to either level. As presetting is synchronous, setting up
a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock
pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input would be avoided when the
clock is low if the enable inputs are high at or before the transition. The clear function is asynchronous and a low level
at the clear input sets all four of the flip-flop outputs low after the next clock pulsregardless of the levels of the enable
inputs. This synchronous clear allows the count length to be modified easily ang the maximum count desired
can be accomplished with one external NAND gate. The gate output is conlear input to synchronously
clear the counter to LLLL. Low-to-high transitions at the clear input shon the clock is low if the
enable and load inputs are high at or before the transition. The carry des for cascading
counters for n-bit synchronous applications without additional gettlishing this function are
two count-enable inputs and a ripple carry output. Both count-ebe high to count, and input
T is fed forward to enable the ripple carry output. The ripple ill produce a high-level output
pulse with a duration approximately equal to the high-levThis high-level overflow ripple
carry pulse can be used to enable successive cascaded ansitions at the enable P or T inputs
should occur only when the clock input is high.
Features
•
Ordering Information
e
Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
Part Name
Package T
16AE-B
16FV)
HD74LS163AP
HD74LS163AFPEL
HD74LS163ARPEL
DIL
P
—
RSP0016DH-B
(FP-16DAV)
SO
SOP-16 )
FP
RP
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
PRSP0016DG-A
(FP-16DNV)
Note: Please consult the sales office for the above package availability.
Rev.2.00, Feb.18.2005, page 1 of 11
HD74LS163A
Pin Arrangement
Clear
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
CLR
Ripple
Ripple
Carry Output
CK
Clock
Carry
A
Q
A
B
QA
QB
QC
QD
A
B
B
C
Q
Data
Inputs
Outputs
Q
C
D
C
D
D
P
Q
T
Enable P
GND
Enable T
Load
Load
(Top view)
Block Diagram
Clock
Output
QA
Q
Clear
Load
CK
Q
P
T
A
Enable
Output
D
Q
Q
B
CK
Q
C
D
Output
QC
Data
Inputs
D
Q
CK
Q
Output
QD
D
Q
CK
Q
Ripple
Carry
Output
Rev.2.00, Feb.18.2005, page 2 of 11
HD74LS163A
Absolute Maximum Ratings
Item
Supply voltage
Symbol
VCC
Ratings
Unit
V
7
VIN
Input voltage
7
V
PT
Power dissipation
Storage temperature
400
mW
°C
Tstg
–65 to +150
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Symbol
VCC
Min
4.75
—
Typ
5.00
—
Max
5.25
–400
8
Unit
Supply voltage
Output current
V
µA
mA
°C
MHz
ns
IOH
IOL
—
—
Topr
ƒclock
tw (clock)
tw (clear)
Operating temperature
Clock frequency
–20
0
25
—
75
25
Clock pulse width
Clear pulse width
25
20
20
20
20
20
—
—
—
ns
A, B, C, D
Enable P, T
Load
—
ns
—
ns
Setup time
Hold time
tsu
ns
Clear
—
ns
th
—
ns
Typical Clear, Preset, and Inhibit Seq
Clear
Load
A
B
Data
Inputs
D
Clock
Enable P
Enable T
Q
A
B
Q
Outputs
Q
C
D
Q
Carry
12 13 14 15
Count
0
1
2
Inhibit
Clear Preset
Rev.2.00, Feb.18.2005, page 3 of 11
HD74LS163A
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Symbol
VIH
min.
2.0
—
typ.*
—
max.
—
Unit
V
Condition
Input voltage
VIL
—
0.8
V
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
IOH = –400 µA
VOH
VOL
2.7
—
—
V
V
Output voltage
—
—
—
—
—
—
—
—
—
—
—
–20
—
—
—
—
—
—
—
—
—
—
0.4
0.5
20
IOL = 4 mA
IOL = 8 mA
VCC = 4.75 V, VIH = 2 V,
VIL = 0.8 V
Data, Enable P
Load, Clock, Enable T
Clear
IIH
IIL
II
µA
mA
mA
VCC = 5.25 V, VI = 2.7 V
VCC = 5.25 V, VI = 0.4 V
C = 5.25 V, VI = 7 V
40
40
Data, Enable P
–0.4
–0.8
–0.8
0.1
0.2
Input
Load, Clock, Enable T
current
Clear
Data, Enable P
—
—
—
—
18
19
—
Load, Clock, Enable T
Clear
0.2
–100
31
Short-circuit output current
IOS
ICCH
ICCL
VIK
5 V
Supply current**
Input clamp voltage
5 V, IIN = –18 mA
Notes: * VCC = 5 V, Ta = 25°C
** ICC is measured with the load input high, then , with all other inputs high and all
outputs open. ICC is measured with the clocthe clock input low, with all other
inputs low and all outputs open.
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item
Sym
ts
min.
25
—
typ.
32
20
18
13
18
13
18
9
max.
—
Unit
MHz
ns
Condition
Maximum clock frequency
to QD
35
35
24
27
24
27
14
14
28
Ripple
Carry
—
ns
—
ns
= “H”)
QA to QD
QA to QD
—
ns
CL = 15 pF,
RL = 2 kΩ
Propagation delay time
tP
—
ns
Clock
(Load = “L”)
tPHL
—
ns
tPLH
—
ns
Ripple
Carry
Enable T
Clear
tPHL
—
9
ns
tPHL
QA to QD
—
20
ns
Rev.2.00, Feb.18.2005, page 4 of 11
HD74LS163A
Timing Method
tw (CK)
1.3V
3V
0V
1.3V
th
1.3V
1.3V
Clock
Clear
tsu
3V
1.3V
1.3V
0V
3V
tsu
th
Load
1.3V
1.3V
1.3V
0V
3V
tsu
th
Data
Outputs
A to D
1.3V
0V
th
3V
0V
Enable
P or T
Testing Method
Test Circuit
4.5V
Load circuit 1
RL
Q
A
B
C
L
Input
A
B
C
D
Q
Q
Q
B
C
D
P.G.
Z
Z
out = 50Ω
Q
Same as Load Circuit 1.
Same as Load Circuit 1.
Same as Load Circuit 1.
Q
C
D
P
T
P.G.
out = 50Ω
Q
Ripple
Carry
Ripple
Carry
Same as Load Circuit 1.
CLR
Notes:
1. CL includes probe and jig capacitance.
2. All diodes are 1S2074(H).
Rev.2.00, Feb.18.2005, page 5 of 11
HD74LS163A
Testing Table
Inputs
Clock
From input to
Item
Enable
Data
output
Clear
4.5V
4.5V
Load
4.5V
4.5V
P
T
A
B
C
D
ƒmax
4.5V
4.5V
IN
IN
GND
GND
GND
GND
CK
→
Ripply
Carry
4.5V
4.5V
GND
GND
GND
GND
CK → Q
CK → Q
4.5V
4.5V
4.5V
GND
4.5V
GND
4.5V
GND
IN
IN
GND
IN*
GND
IN*
GND
IN*
GND
IN*
tPLH
tPHL
Enable
T
Ripple
Carry
→
4.5V
IN
GND
GND
4.5V
GND
IN
IN*
IN*
4.5V
4.5V
4.5V
4.5V
4.5V
4.5V
4.5V
4.5V
CLR → Q
GND
Notes: *. For initialized
Outputs
QC
Item
From input to output
QA
QB
QD
OUT
—
Ripple Carry
ƒmax
OUT
—
OUT
—
OUT
—
OUT
OUT
—
CK→Ripple Carry
CK→Q
OUT
OUT
—
OUT
OUT
—
OUT
OUT
tPLH
tPHL
CK→Q
—
Enable T→Ripple Carry
CLR→Q
OUT
—
OUT
OUT
UT
Rev.2.00, Feb.18.2005, page 6 of 11
HD74LS163A
Waveforms 1
ƒmax, tPLH, tPHL, (Clock→Q, Ripple Carry)
tTLH
tTHL
3V
0V
90%
1.3V 1.3V
90%
Clock
1.3V
tPHL
1.3V
10%
tPLH
10%
tw (CK)
(Measure at
(Measure at t
n
n
+ 2)
+ 4)
tn + 1)
VOH
QA
1.3V
1.3V
VOL
VOH
tPHL
tPLH (Measure at t
1.3V
n
n
+ 2)
+ 4)
(Measure at t
QB
1.3V
VOL
VOH
VOL
VOH
VOL
tPHL
t
PLH (Meare at t
(Measure at t
n
+ 8)
QC
1.3V
tPHL
(Measure at
t
n + 1
QD
1.3V
tPLH (Measure at
+ 15)
tPH
t
n
VOH
VOL
Ripple
Carry
1.3V
Note: Clock input pulse; tTLH ≤ 1MHz, duty cycle 50%
and : ƒmax tTLH = tTHL ≤
tn is reference bit timw.
Rev.2.00, Feb.18.2005, page 7 of 11
HD74LS163A
Waveforms 2
tPLH, tPHL, (Clock→Q)
tTLH
tTHL
90%
10%
3V
90%
1.3V
1.3V
Clock
10%
tTLH
0V
3V
tTHL
90%
10%
90%
10%
Data Inputs
A, B, C or D
0V
tPLH
tPHL
VOH
Outputs
QA, QB, QC or QD
1.3V
1.3V
VOL
Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, Clock input: PRR = 1 MHcle 50%,
Data input: PRR = 500 kHz, duty cycle 50%
Waveforms 3
tPLH, tPHL, (Enable T→Ripple Carry)
tTLH
3 V
0 V
90 %
1.3 V
Enable T
10 %
0 %
tPHL
VOH
VOH
Ripple
Carry
V
1.3 V
Note: Input pulse: tTLH PRR = 1 MHz
Rev.2.00, Feb.18.2005, page 8 of 11
HD74LS163A
Waveforms 4
tPHL, (Clear→Q)
tTLH
tTHL
90%
10%
3V
90%
10%
1.3V
Clock
Clear
0V
3V
tTHL
tTLH
tw (CLR)
≥ 20ns
90%
1.3V
90%
1.3V
10%
10%
0V
tPHL
VOH
1.3V
QA to QD
VOL
Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns
Rev.2.00, Feb.18.2005, page 9 of 11
HD74LS163A
Package Dimensions
JEITA Package Code
P-DIP16-6.3x19.2-2.54
RENESAS Code
PRDP0016AE-B
Previous Code
DP-16FV
MASS[Typ.]
1.05g
D
16
9
1
8
b 3
0.89
Z
Dimension in Millimeters
Reference
Symbol
Min
Nom
7.62
19.2
6.3
Max
e
1
D
20.32
7.4
E
A
5.06
A 1
0.51
0.40
b
0.48
1.30
0.25
0.56
0.31
p
bp
e
b
3
c
θ
0.19
0°
15°
e
Z
L
2.29
2.54
2.54
2.79
1.12
u plating )
JEITA Package Code
P-SOP16-5.5x10.06-1.27
RENESAS Code
PRSP0016DH-B
Pre
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
*1
D
F
16
bp
Index mark
Dimension in Millimeters
Reference
Symbol
Min
Nom
10.06
5.50
Max
10.5
Terminal cross section
( Ni/Pd/Au plating )
D
E
1
8
bp
A 2
A 1
A
*3
e
0.00
0.34
0.15
0.10
0.40
0.20
0.20
2.20
0.46
Z
x
M
L1
b p
b 1
c
0.25
c
1
θ
H E
e
0
°
8°
7.50
7.80
1.27
8.00
y
x
0.12
0.15
0.80
0.90
L
y
Z
Detail F
L
0.50
0.70
1.15
L
1
Rev.2.00, Feb.18.2005, page 10 of 11
HD74LS163A
JEITA Package Code
P-SOP16-3.95x9.9-1.27
RENESAS Code
PRSP0016DG-A
Previous Code
FP-16DNV
MASS[Typ.]
0.15g
NOTE)
*1
D
F
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
16
9
b p
Index mark
Dimension in Millimeters
Reference
Symbol
Min
Nom
9.90
3.95
Max
Terminal cross section
( Ni/Pd/Au plating )
D
10.30
E
A 2
A 1
A
1
8
0.10
0.34
0.15
0.14
0.40
0.20
0.25
1.75
0.46
*3
e
Z
bp
x
M
L1
b p
b 1
c
0.25
c
1
θ
H E
e
0
°
8°
5.80
6.10
1.27
6.20
x
0.25
0.15
y
y
Z
0.635
1.27
L
0.40
0.60
1.08
L
1
Rev.2.00, Feb.18.2005, page 11 of 11
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Colophon .2.0
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