HD74LV123ARP [RENESAS]
暂无描述;
| 型号： | HD74LV123ARP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 暂无描述 触发器 |
| 文件： | 总16页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74LV123A
Dual Retriggerable Monostable Multivibrators
REJ03D0314–0600Z
(Previous ADE-205-258D (Z))
Rev.6.00
Jun. 02, 2004
Description
The HD74LV123A features output pulse-duration control by three methods. In the first method, the A input is low and
the B input goes high. In the second method, the B input is high and the A input goes low. In the third method, the A
input is low, the B input is high, and the clear (CLR) input goes high.
The basic pulse duration is programmed by selecting external resistance and capacitance values.
The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor
connected between Rext/Cext and Vcc
To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and Vcc.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or high-level-
active (B) input. Pulse duration can be reduced by taking CLR low.
Features
•
•
•
•
•
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LV123AFPEL
HD74LV123ARPEL
HD74LV123ATELL
SOP–16 pin(JEITA)
SOP–16 pin(JEDEC)
TSSOP–16 pin
FP–16DAV
FP–16DNV
TTP–16DAV
FP
RP
T
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Rev.6.00 Jun. 02, 2004 page 1 of 15
HD74LV123A
Function Table
Inputs
Outputs
CLR
L
A
X
H
X
L
B
X
X
L
Q
L
Q
H
H
H
H
L
H
L
H
↑
H
↓
H
H
↑
L
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
: High level pulse
: Low level pulse
Pin Arrangement
16
1
2
3
4
5
6
7
8
VCC
1A
1B
15
14
13
12
11
1Rext / Cext
1CLR
1Q
1Cext
1Q
2Q
2Q
2CLR
2B
2Cext
2Rext / Cext
GND
10
9
2A
(Top view)
Rev.6.00 Jun. 02, 2004 page 2 of 15
HD74LV123A
Absolute Maximum Ratings
Item
Symbol
Ratings
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
Unit
V
Conditions
Supply voltage range
Input voltage range*1
Output voltage range*1, 2
VCC
VI
V
VO
V
Output: H or L
VCC: OFF
Input clamp current
IIK
mA
mA
mA
mA
VI < 0
Output clamp current
IOK
±50
VO < 0 or VO > VCC
VO = 0 to VCC
Continuous output current
Continuous current through
IO
±25
ICC or IGND
±50
VCC or GND
Maximum power dissipation at PT
Ta = 25°C (in still air)*3
785
mW
SOP
500
TSSOP
Storage temperature
Tstg
–65 to 150
°C
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Symbol Min
Typ
—
Max
5.5
5.5
VCC
–50
–2
Unit Conditions
Supply voltage range
Input voltage range
Output voltage range
Output current
VCC
VI
2.0
0
V
V
V
—
VO
IOH
0
—
—
—
—
—
—
—
—
—
0
—
µA
VCC = 2.0 V
—
mA
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.0 V
—
–6
—
–12
50
IOL
—
µA
—
2
mA
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
—
6
—
12
Input transition rise or fall rate
External timing resistance
∆t /∆v
—
200
100
20
ns/V VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
0
—
0
—
V
CC = 4.5 to 5.5 V
VCC = 2.0 V
CC ≥ 2.3 V
Rext
5
—
—
kΩ
1
—
—
V
External timing capacitance
Power-up ramp rate
Cext
—
1
Unlimited
—
—
F
∆t /∆VCC
—
ms/
V
Operating free-air temperature
Ta
–40
—
85
°C
Note: Unused or floating inputs must be held high or low.
Rev.6.00 Jun. 02, 2004 page 3 of 15
HD74LV123A
Logic Diagram
Rext/
Cext
Cext
A
Q
Q
B
Q
Q
CLR
CLR
Rev.6.00 Jun. 02, 2004 page 4 of 15
HD74LV123A
DC Electrical Characteristics
Ta = –40 to 85°C
Unit Test Conditions
V
Item
Symbol
V
CC (V)*
Min
Typ Max
Input voltage
VIH
2.0
1.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.5
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
2.0
V
V
V
CC × 0.7
CC × 0.7
CC × 0.7
VIL
—
—
—
—
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
V
V
V
CC × 0.3
CC × 0.3
CC × 0.3
Output voltage
VOH
Min to Max VCC – 0.1
—
V
IOH = –50 µA
IOH = –2 mA
IOH = –6 mA
IOH = –12 mA
IOL = 50 µA
2.3
2.0
2.48
3.8
—
—
3.0
—
4.5
—
VOL
Min to Max
2.3
0.1
0.4
0.44
0.55
±1
—
IOL = 2 mA
3.0
—
IOL = 6 mA
4.5
—
IOL = 12 mA
Input current
IIN
IIN
0 to 5.5
5.5
—
µA
µA
VIN = 5.5 V or GND
VIN = VCC or GND
Input current
Rext / Cext
—
±2.5
Quiescent supply
current
ICC
5.5
—
—
20
µA
µA
VIN = VCC or GND, IO = 0
Active state supply
current
(per circuit)
∆ICC
2.3
3.0
4.5
5.5
0
—
—
—
—
—
—
—
—
—
—
220
280
650
975
5
VIN = VCC or GND
Rext/Cext = 0.5 VCC
Output leakage
current
IOFF
CIN
µA
VI or VO = 0 V to 5.5 V
VI = VCC or GND
Input capacitance
3.3
—
4.0
—
pF
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Rev.6.00 Jun. 02, 2004 page 5 of 15
HD74LV123A
Switching Characteristics
VCC = 2.5 ± 0.2 V
TO
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
(Input)
Item
Symbol
Unit Conditions
(Output)
Min Typ Max Min
Max
37.0
42.0
29.5
34.5
39.0
44.0
320
Propagation
delay time
tPLH
tPHL
—
—
—
—
—
—
—
90
13.5 31.4 1.0
16.0 36.0 1.0
11.0 25.0 1.0
13.0 32.8 1.0
14.0 33.4 1.0
16.0 38.0 1.0
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
A or B
Q or Q
Q or Q
Q or Q
CLR
CLR
(Trigger)
Output pulse
width
twQ
170 260
—
ns
CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ
100 110 90
110
µs
CL = 50 pF,
Cext = 0.01 µF, Rext = 10 kΩ
0.9
1.0
1.1
0.9
1.1
ms
CL = 50 pF,
Cext = 0.1 µF, Rext = 10 kΩ
∆twQ
tw
—
±1
—
40
—
—
—
—
—
—
—
%
CL = 50 pF
Pulse width
6.0
—
6.5
—
ns
ns
A, B or CLR
Retrigger time
trr
A, or B
(Rext = 1 kΩ, Cext = 100 pF)
—
1.5
—
—
—
µs
A, or B
(Rext = 1 kΩ, Cext = 0.01 µF)
VCC = 3.3 ± 0.3 V
Ta = 25°C
Ta = –40 to 85°C
Test
Unit Conditions
FROM
(Input)
TO
Item
Symbol
(Output)
Min Typ Max Min
Max
24.0
27.5
18.5
22.0
26.0
29.5
300
Propagation
delay time
tPLH
tPHL
—
—
—
—
—
—
—
90
9.7
20.6 1.0
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
A or B
Q or Q
Q or Q
Q or Q
11.5 24.1 1.0
8.0
9.5
9.9
15.8 1.0
19.3 1.0
22.4 1.0
CLR
CLR
(Trigger)
11.5 25.9 1.0
150 240
100 110 90
Output pulse
width
twQ
—
ns
CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ
110
µs
CL = 50 pF,
Cext = 0.01 µF, Rext = 10 kΩ
0.9
1.0
1.1
0.9
1.1
ms
CL = 50 pF,
Cext = 0.1 µF, Rext = 10 kΩ
∆twQ
tw
—
±1
—
30
—
—
—
—
—
—
—
%
CL = 50 pF
Pulse width
5.0
—
5.0
—
ns
ns
A, B or CLR
Retrigger time
trr
A, or B
(Rext = 1 kΩ, Cext = 100 pF)
—
1.2
—
—
—
µs
A, or B
(Rext = 1 kΩ, Cext = 0.01 µF)
Rev.6.00 Jun. 02, 2004 page 6 of 15
HD74LV123A
Switching Characteristics (cont)
VCC = 5.0 ± 0.5 V
TO
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
(Input)
Item
Symbol
Unit Conditions
(Output)
Min Typ Max Min
Max
14.0
16.0
11.0
13.0
15.0
17.0
240
Propagation
delay time
tPLH
tPHL
—
—
—
—
—
—
—
90
7.3
8.5
5.9
7.5
7.3
8.7
12.0 1.0
14.0 1.0
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
A or B
Q or Q
Q or Q
Q or Q
9.4
1.0
CLR
11.4 1.0
12.9 1.0
14.9 1.0
CLR
(Trigger)
Output pulse
width
twQ
140 200
—
ns
CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ
100 110 90
110
µs
CL = 50 pF,
Cext = 0.01 µF, Rext = 10 kΩ
0.9
1.0
1.1
0.9
1.1
ms
CL = 50 pF,
Cext = 0.1 µF, Rext = 10 kΩ
∆twQ
tw
—
±1
—
20
—
—
—
—
—
—
—
%
CL = 50 pF
Pulse width
5.0
—
5.0
—
ns
ns
A, B or CLR
Retrigger time
trr
A, or B
(Rext = 1 kΩ, Cext = 100 pF)
—
0.95
—
—
—
µs
A, or B
(Rext = 1 kΩ, Cext = 0.01 µF)
Operating Characteristics
CL = 50 pF
Ta = 25°C
Item
Symbol
VCC (V)
Unit
Test Conditions
f = 10 MHz
Min
—
Typ
74.0
86.0
Max
—
Power dissipation capacitance CPD
3.3
5.0
pF
—
—
Test Circuit
VCC
Cext
Rext
Cext = 28 pF or 100 pF or 0.01 µF or 0.1 µF
Rext = 1 kΩ or 2 kΩ or 10 kΩ
−
+
VCC
VCC
Q
Cext Rext/
Cext
Output
A
Refer
to
CL = 15 pF or 50 pF
Func-
tion
Input
B
Table
Q
Output
CLR
CL = 15 pF or 50 pF
GND
Note : CL includes the probe and jig capacitance.
Rev.6.00 Jun. 02, 2004 page 7 of 15
HD74LV123A
Timing diagram
trr
A
B
CLR
Rext/
Cext
Q
tw
tw
tw +trr
Caution in use
In order to prevent any malfunctions due to noise, connect a high frequency
performance capacitor between Vcc and GND, and keep the wiring between the
External components and Cext, Rext/Cext pins as short as possible.
Large values of Cext may cause problems when powering down the HD74LV123A
because of the amount of energy stored in the capacitor. When a system containing
this device is powered down, the capacitor may discharge from Vcc through the protection
diodes at pin 7 or pin 15.
Current through the input protection diodes must be limited to 20 mA; therefore, the turn-off
time of the Vcc power supply must not be faster than t = Vcc • Cext/(20 mA). For example,
if Vcc = 5 V and Cext = 22 µF, the Vcc supply must turn off no faster than t = (5 V) • (22 µF)/
20 mA = 5.5 ms. This is usually not a problem because power supplies are heavily filtered
and cannot discharge at this rate.
When a more rapid decrease of Vcc to zero volts occurs, the HD74LV123A may sustain damage.
To avoid this possibility, use an external calmping diode.
The input pins for unused circuit should be used under conditions to fix the outputs to avoid
malfunction cased by noises. Also, it's recommended that Rext / Cext terminals are open and
external parts are not connected to.
Rev.6.00 Jun. 02, 2004 page 8 of 15
HD74LV123A
• Waveform − 1
tf
VCC
90%
50%
Input A
10%
tr
GND
VCC
90%
Input B
50%
10%
10%
GND
tf
tr
tr
VCC
90%
50%
90%
50%
10%
90%
50%
10%
Input CLR
GND
tw (L)
tPLH(trigger)
tPHL
VOH
Output Q
50% VCC
50% VCC
VOL
tPHL(trigger)
tPLH
VOH
50% VCC
50% VCC
Output Q
VOL
Rev.6.00 Jun. 02, 2004 page 9 of 15
HD74LV123A
• Waveform − 2
tf
tr
tr
VCC
90%
50%
90%
50%
90%
50%
10%
Input A
10%
90%
10%
GND
tw (H)
tw (L)
tf
tr
tf
VCC
90%
50%
90%
50%
50%
Input B
10%
10%
10%
GND
tw (L)
tw (H)
VOH
VOL
VOH
Output Q
Output Q
50% VCC
50% VCC
tw (out)
50% VCC
50% VCC
VOL
• Waveform − 3
Input A
tf
tr
tf
VCC
90%
50%
90%
90%
50%
10%
10%
90%
10%
tr
GND
trr
tf
tr
VCC
90%
50%
90%
50%
Input B
10%
10%
10%
GND
VOH
Output Q
50% VCC
50% VCC
VOL
tw (out) + trr
VOH
50% VCC
50% VCC
Output Q
VOL
Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns
2. The output are measured one at a time with one transition per measurement.
Rev.6.00 Jun. 02, 2004 page 10 of 15
HD74LV123A
Application Data
Vcc = 2.5 V
10000.0
1000.0
100.0
10.0
Rext
1 kΩ
1.0
0.1
10 kΩ
100 kΩ
1 MΩ
102
103
104
105
106
107
Timing capacitance Cext (pF)
Vcc = 3.3 V
10000.0
1000.0
100.0
10.0
Rext
1 kΩ
1.0
0.1
10 kΩ
100 kΩ
1 MΩ
102
103
104
105
106
107
Timing capacitance Cext (pF)
Rev.6.00 Jun. 02, 2004 page 11 of 15
HD74LV123A
Vcc = 5.0 V
10000.0
1000.0
100.0
10.0
Rext
1 kΩ
1.0
0.1
10 kΩ
100 kΩ
1 MΩ
102
103
104
105
106
107
Timing capacitance Cext (pF)
Rext = 2 kΩ
1.4
1.3
1.2
1.1
1.0
0.9
0.8
Cext
1000 pF
10000 pF
100000 pF
1000000 pF
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Supply voltage VCC (V)
Rev.6.00 Jun. 02, 2004 page 12 of 15
HD74LV123A
Rext = 10 kΩ
1.4
1.3
1.2
1.1
1.0
0.9
0.8
Cext
1000 pF
10000 pF
100000 pF
1000000 pF
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Supply voltage VCC (V)
Rev.6.00 Jun. 02, 2004 page 13 of 15
HD74LV123A
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
9
16
1
8
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
Package Code
JEDEC
FP-16DAV
—
JEITA
Mass (reference value)
Conforms
0.24 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
9.9
10.3 Max
9
8
16
1
1.27
+ 0.10
6.10
– 0.30
1.08
0.635 Max
0˚ – 8˚
+ 0.67
0.60
– 0.20
*0.40 ± 0.06
0.15
0.25
M
Package Code
JEDEC
JEITA
FP-16DNV
Conforms
Conforms
0.15 g
*Ni/Pd/Au plating
Mass (reference value)
Rev.6.00 Jun. 02, 2004 page 14 of 15
HD74LV123A
As of January, 2003
Unit: mm
5.00
5.30 Max
16
9
1
8
0.65
0.13 M
0.65 Max
1.0
*0.20 ± 0.05
6.40 ± 0.20
0˚ – 8˚
0.50 ± 0.10
0.10
Package Code
JEDEC
TTP-16DAV
—
JEITA
—
*Ni/Pd/Au plating
Mass (reference value)
0.05 g
Rev.6.00 Jun. 02, 2004 page 15 of 15
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Renesas Technology Hong Kong Ltd.
7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2375-6836
Renesas Technology Taiwan Co., Ltd.
FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
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