HD74LV161AT-ELL [RENESAS]
LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, TSSOP-16;
| 型号： | HD74LV161AT-ELL |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, TSSOP-16 计数器 |
| 文件： | 总16页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74LV161A
Synchronous 4-bit Binary Counter (Direct Clear)
REJ03D0319–0400Z
(Previous ADE-205-264B (Z))
Rev.4.00
Jun. 04, 2004
Description
The HD74LV161A is 4-bit binary counters. All flip flops are clocked simultaneously on the low to high to transition
(positive edge) of the clock input waveform. These counters may be preset using the load input. Presetting of all four
flip flops is synchronous to the rising edge of clock. When load is held low counting is disabled and the data on the A,
B, C and D inputs is loaded into the counter on the rising edge clock. If the load input is taken high before the positive
edge of clock, the count operation will be unaffected.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the
low-power consumption extends the battery life.
Features
•
•
•
•
•
•
•
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LV161AFPEL
HD74LV161ARPEL
HD74LV161ATELL
SOP–16 pin(JEITA)
SOP–16 pin(JEDEC)
TSSOP–16 pin
FP–16DAV
FP–16DNV
TTP–16DAV
FP
RP
T
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Rev.4.00 Jun. 04, 2004 page 1 of 15
HD74LV161A
Function Table
Inputs
Outputs
QA
CLR
L
LOAD
X
ENP
X
ENT
X
CLK
QB
L
QC
L
QD
L
X
↑
↑
↑
↑
↓
L
H
L
X
X
A
B
C
D
H
H
H
H
X
X
L
No change
No change
Count up
No change
H
L
X
H
H
H
H
X
X
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
A, B, C, D: Data input
Carry = ENT • QA • QB • QC • QD
Pin Arrangement
1
2
3
4
5
6
7
8
16 VCC
CLR
CK
A
CARRY
15
14
13
12
11
10
9
OUTPUT
QA
QB
B
QC
C
QD
D
ENP
GND
ENT
LOAD
(Top view)
Rev.4.00 Jun. 04, 2004 page 2 of 15
HD74LV161A
Absolute Maximum Ratings
Item
Symbol
Ratings
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
Unit
V
Conditions
Supply voltage range
Input voltage range*1
Output voltage range*1, 2
VCC
VI
V
H or L
VO
V
Output: H or L
VCC: OFF
Input clamp current
IIK
mA
mA
mA
mA
VI < 0
Output clamp current
IOK
±50
VO < 0 or VO > VCC
VO = 0 to VCC
Continuous output current
Continuous current through
IO
±25
ICC or IGND
±50
VCC or GND
Maximum power dissipation at PT
Ta = 25°C (in still air)*3
785
mW
SOP
500
TSSOP
Storage temperature
Tstg
–65 to 150
°C
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Symbol
VCC
VI
Min
2.0
0
Max
5.5
5.5
VCC
–50
–2
Unit
V
Conditions
Supply voltage range
Input voltage range
Output voltage range
Output current
V
VO
0
V
IOH
—
—
—
—
—
—
—
—
0
µA
mA
VCC = 2.0 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.0 V
–6
–12
50
IOL
µA
2
mA
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
6
12
Input transition rise or fall rate
Operating free-air temperature
∆t /∆v
200
100
20
ns/V
°C
0
0
VCC = 4.5 to 5.5 V
Ta
–40
85
Note: Unused or floating inputs must be held high or low.
Rev.4.00 Jun. 04, 2004 page 3 of 15
HD74LV161A
Logic Diagram
CLK
Output
CLR
D
Q
Q
A
CK
Q
CLR
LOAD
P
Enable
T
A
Output
D
Q
Q
B
CK
Q
CLR
B
C
D
Output
D
Q
Q
C
CK
Data
Inputs
Q
CLR
Output
D
Q
Q
D
CK
Q
CLR
Carry
Output
Rev.4.00 Jun. 04, 2004 page 4 of 15
HD74LV161A
Timing Diagram
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
QA
QB
QC
QD
Out
puts
Carry
12
13
14
15
0
1
2
Count
Inhibit
Clear
Preset
(Load)
Rev.4.00 Jun. 04, 2004 page 5 of 15
HD74LV161A
DC Electrical Characteristics
Ta = –40 to 85°C
Unit Test Conditions
V
Item
Symbol
V
CC (V)*
Min
Typ Max
Input voltage
VIH
2.0
1.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.5
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
2.0
V
V
V
CC × 0.7
CC × 0.7
CC × 0.7
VIL
—
—
—
—
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
V
V
V
CC × 0.3
CC × 0.3
CC × 0.3
Output voltage
VOH
Min to Max VCC – 0.1
—
V
IOL = –50 µA
IOL = –2 mA
2.3
2.0
2.48
3.8
—
—
3.0
—
IOL = –6 mA
4.5
—
IOL = –12 mA
IOL = 50 µA
VOL
Min to Max
2.3
0.1
0.4
0.44
0.55
±1
—
IOL = 2 mA
3.0
—
IOL = 6 mA
4.5
—
IOL = 12 mA
Input current
IIN
0 to 5.5
5.5
—
µA
µA
VIN = 5.5 V or GND
VIN = VCC or GND, IO = 0
Quiescent supply
current
ICC
—
20
Output leakage
current
IOFF
0
—
—
5
µA
VI or VO = 0 V to 5.5 V
Input capacitance
CIN
3.3
—
1.7
—
pF
VI = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Rev.4.00 Jun. 04, 2004 page 6 of 15
HD74LV161A
Switching Characteristics
VCC = 2.5 ± 0.2 V
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
TO
Item
Symbol
Unit Conditions (Input)
(Output)
Min
50
30
—
Typ
Max Min
Max
—
Maximum clock
frequency
fmax
90
60
—
—
40
25
MHz CL = 15 pF
CL = 50 pF
—
Propagation
delay time
tPLH/tPHL
11.1 16.2 1.0
14.3 19.2 1.0
11.5 17.0 1.0
14.7 20.0 1.0
13.8 20.6 1.0
17.0 23.6 1.0
10.3 15.7 1.0
14.0 18.7 1.0
11.7 17.0 1.0
14.7 20.0 1.0
11.2 16.6 1.0
14.4 19.6 1.0
19.5
22.5
20.5
23.5
24.5
27.5
19.0
22.0
20.5
23.5
20.0
23.0
—
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CLK
CLK
CLK
ENT
CLR
CLR
Q
—
tPLH/tPHL
—
Carry
Carry
Carry
Q
Count mode
tPLH/tPHL
—
—
Load mode
tPLH/tPHL
—
—
—
tPHL
tPHL
tsu
—
—
—
Carry
—
Setup time
7.5
10.0
9.5
—
—
—
—
—
—
8.5
ns
Data before CLK ↑
LOAD before CLK ↑
11.5
11.0
—
—
ENT, ENP before
CLK ↑
4.5
—
—
4.5
—
CLR inactive before
CLK ↑
Hold time
th
1.5
7.0
7.0
—
—
—
—
—
—
1.5
7.0
7.0
—
—
—
ns
ns
Pulse width
tw
CLK H or L
CLR L
Rev.4.00 Jun. 04, 2004 page 7 of 15
HD74LV161A
Switching Characteristics (cont)
VCC = 3.3 ± 0.3 V
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
TO
Item
Symbol
Unit Conditions (Input)
(Output)
Min
80
55
—
Typ
Max Min
Max
—
Maximum clock
frequency
fmax
130
85
—
—
70
50
MHz CL = 15 pF
CL = 50 pF
—
Propagation
delay time
tPLH/tPHL
8.3
12.8 1.0
15.0
18.5
16.0
19.5
20.0
23.5
14.5
18.0
16.0
19.5
15.5
19.0
—
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CLK
CLK
CLK
ENT
CLR
CLR
Q
—
10.8 16.3 1.0
8.7 13.6 1.0
tPLH/tPHL
—
Carry
Carry
Carry
Q
Count mode
tPLH/tPHL
—
11.2 17.1 1.0
11.0 17.2 1.0
13.5 20.7 1.0
—
Load mode
tPLH/tPHL
—
—
7.5
10.5 15.8 1.0
8.9 13.6 1.0
11.2 17.1 1.0
8.4 13.2 1.0
10.9 16.7 1.0
12.3 1.0
—
tPHL
tPHL
tsu
—
—
—
Carry
—
Setup time
5.5
8.0
7.5
—
—
—
—
—
—
6.5
9.5
9.0
ns
Data before CLK ↑
LOAD before CLK ↑
—
—
ENT, ENP before
CLK ↑
2.5
—
—
2.5
—
CLR inactive before
CLK ↑
Hold time
th
1.0
5.0
5.0
—
—
—
—
—
—
1.0
5.0
5.0
—
—
—
ns
ns
Pulse width
tw
CLK H or L
CLR L
Rev.4.00 Jun. 04, 2004 page 8 of 15
HD74LV161A
Switching Characteristics (cont)
VCC = 5.0 ± 0.5 V
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
TO
Item
Symbol
Unit Conditions (Input)
(Output)
Min
135
95
—
Typ
Max Min
Max
—
Maximum clock
frequency
fmax
185
125
4.9
8.7
4.9
6.4
6.2
7.7
4.9
6.4
5.5
7.0
5.0
6.5
—
—
115
85
MHz CL = 15 pF
CL = 50 pF
—
—
Propagation
delay time
tPLH/tPHL
8.1
1.0
9.5
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CLK
CLK
CLK
ENT
CLR
CLR
Q
—
10.1 1.0
8.1 1.0
11.5
9.5
tPLH/tPHL
—
Carry
Carry
Carry
Q
Count mode
tPLH/tPHL
—
10.1 1.0
10.3 1.0
12.3 1.0
11.5
12.0
14.0
9.5
—
Load mode
tPLH/tPHL
—
—
8.1
10.1 1.0
9.0 1.0
11.0 1.0
8.6 1.0
10.6 1.0
1.0
—
11.5
10.5
12.5
10.0
12.0
—
tPHL
tPHL
tsu
—
—
—
Carry
—
Setup time
4.5
5.0
5.0
—
—
—
4.5
6.0
6.0
ns
Data before CLK ↑
LOAD before CLK ↑
—
—
—
—
ENT, ENP before
CLK ↑
1.5
—
—
1.5
—
CLR inactive before
CLK ↑
Hold time
th
1.0
5.0
5.0
—
—
—
—
—
—
1.0
5.0
5.0
—
—
—
ns
ns
Pulse width
tw
CLK H or L
CLR L
Operating Characteristics
CL = 50 pF
Ta = 25°C
Item
Symbol
VCC (V) Min
Typ
Max
Unit
Test Conditions
Power dissipation capacitance CPD
3.3
5.0
—
—
17.0
20.4
—
—
pF
f = 10 MHz
Rev.4.00 Jun. 04, 2004 page 9 of 15
HD74LV161A
Noise Characteristics
CL = 50 pF
Test Conditions
Ta = 25°C
Min
Item
Symbol
VCC (V)
Unit
Typ
Max
Quiet output, maximum
dynamic VOL
VOL (P)
3.3
—
0.3
0.8
V
Quiet output, minimum
dynamic VOL
VOL (V)
VOH (V)
VIH (D)
VIL (D)
3.3
3.3
3.3
3.3
—
–0.3
3.0
—
–0.8
—
V
V
V
V
Quiet output, minimum
dynamic VOH
—
High-level dynamic input
voltage
2.31
—
—
Low-level dynamic input
voltage
—
0.99
Test Circuit
Measurement point
*
C L
Note: 1. CL includes the probe and jig capacitance.
Rev.4.00 Jun. 04, 2004 page 10 of 15
HD74LV161A
Waveforms
Waveform
− 1
Count mode
t
t
wL
wH
V
CC
CLK
50%V
50%V
CC
CC
GND
V
V
OH
OL
Q,
CARRY
50%V
50%V
CC
CC
t
t
pHL
pLH
Waveform
− 2
Preset mode
V
CC
LOAD
50%V
50%V
su
CC
CC
GND
t
t
t
t
h
su
h
A~D
CLK
50%V
CC
t
t
su
h
V
CC
50%V
CC
50%V
CC
GND
t
t
pLH,pHL
V
V
OH
OL
Q,
CARRY
50%V
CC
Rev.4.00 Jun. 04, 2004 page 11 of 15
HD74LV161A
Waveform
− 3
Count enable mode
V
CC
ENP
50%V
CC
50%V
CC
ENT
CK
GND
t
t
t
t
h
su
h
su
V
CC
50%V
50%V
CC
CC
GND
V
V
OH
OL
Q
Waveform
− 4
Clear mode
V
CC
CLR
50%V
CC
GND
t
wL
V
CC
CLK
50%V
CC
GND
t
su
V
OH
OL
Q,
CARRY
50%V
CC
V
t
pHL
Rev.4.00 Jun. 04, 2004 page 12 of 15
HD74LV161A
Waveform
− 5
Cascade mode
(Set to maximum count number)
VCC
ENT
50%VCC
50%VCC
GND
VOH
CARRY
50%VCC
50%VCC
VOL
tpLH
tpHL
Note:
1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t r≤ 3 ns, t f ≤ 3 ns
Application
Cascade circuitry
H: COUNT
L: DISABLE
INPUTS
INPUTS
INPUTS
LD
A
B
C
D
LD
A
B
C
D
LD
A
B
C
D
ENP
ENT
CK
ENP
ENT
CK
ENP
ENT
CK
H: COUNT
L: DISABLE
CARRY
CARRY
CARRY
to next stages
CLR QA QB QC QD
CLR QA QB QC QD
CLR QA QB QC QD
OUTPUT
OUTPUT
OUTPUT
CLR
CLK
Rev.4.00 Jun. 04, 2004 page 13 of 15
HD74LV161A
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
9
16
1
8
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
Package Code
JEDEC
FP-16DAV
—
JEITA
Mass (reference value)
Conforms
0.24 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
9.9
10.3 Max
9
8
16
1
1.27
+ 0.10
6.10
– 0.30
1.08
0.635 Max
0˚ – 8˚
+ 0.67
0.60
– 0.20
*0.40 ± 0.06
0.15
0.25
M
Package Code
JEDEC
JEITA
FP-16DNV
Conforms
Conforms
0.15 g
*Ni/Pd/Au plating
Mass (reference value)
Rev.4.00 Jun. 04, 2004 page 14 of 15
HD74LV161A
As of January, 2003
Unit: mm
5.00
5.30 Max
16
9
1
8
0.65
0.13 M
0.65 Max
1.0
*0.20 ± 0.05
6.40 ± 0.20
0˚ – 8˚
0.50 ± 0.10
0.10
Package Code
JEDEC
TTP-16DAV
—
JEITA
—
*Ni/Pd/Au plating
Mass (reference value)
0.05 g
Rev.4.00 Jun. 04, 2004 page 15 of 15
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Renesas Technology Taiwan Co., Ltd.
FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
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