HD74LV4040ARPEL [RENESAS]
12-stage Binary Counter; 12级二进制计数器
| 型号： | HD74LV4040ARPEL |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 12-stage Binary Counter |
| 文件： | 总11页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74LV4040A
12-stage Binary Counter
REJ03D0337–0200Z
(Previous ADE-205-282 (Z))
Rev.2.00
Jul. 20, 2004
Description
The HD74LV4040A is a 12 stage counter. This device is incremented on the falling edge (negative transition) of the
input clock, and all its output is reset to a low level by applying a logical high on its reset input. Low-voltage and high-
speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power
consumption extends the battery life.
Features
•
•
•
•
•
•
•
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LV4040AFPEL
HD74LV4040ARPEL
HD74LV4040ATELL
SOP–16 pin (JEITA)
SOP–16 pin (JEDEC)
TSSOP–16 pin
FP–16DAV
FP–16DNV
TTP–16DAV
FP
RP
T
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
Output
Qn
CLK
↑
CLR
L
L
Remains unchanged
Changed
All outputs low
↓
X
H
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
Rev.2.00 Jul. 20, 2004 page 1 of 10
HD74LV4040A
Pin Arrangement
1
2
3
4
5
6
7
8
16 VCC
Q12
Q6
15
14
13
12
11
10
9
Q11
Q10
Q8
Q5
Q7
Q9
Q4
CLR
Q3
Q2
Q1
GND
(Top view)
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Conditions
Supply voltage range
Input voltage range*1
Output voltage range*1, 2
VCC
VI
VO
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
±50
±25
±50
V
V
V
Output: H or L
VCC: OFF
VI < 0
VO < 0 or VO > VCC
VO = 0 to VCC
Input clamp current
Output clamp current
Continuous output current
Continuous current through
VCC or GND
IIK
IOK
IO
mA
mA
mA
mA
ICC or IGND
Maximum power dissipation at PT
Ta = 25°C (in still air)*3
785
500
mW
SOP
TSSOP
Storage temperature
Tstg
–65 to 150
°C
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.2.00 Jul. 20, 2004 page 2 of 10
HD74LV4040A
Recommended Operating Conditions
Item
Symbol
VCC
VI
VO
IOH
Min
2.0
0
Max
5.5
5.5
VCC
–50
–2
–6
–12
50
2
6
12
200
100
20
Unit
V
V
V
µA
mA
Conditions
Supply voltage range
Input voltage range
Output voltage range
Output current
0
H or L
VCC = 2.0 V
—
—
—
—
—
—
—
—
0
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.0 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
IOL
µA
mA
Input transition rise or fall rate
Operating free-air temperature
∆t /∆v
ns/V
°C
0
0
–40
Ta
85
Note: Unused or floating inputs must be held high or low.
Rev.2.00 Jul. 20, 2004 page 3 of 10
HD74LV4040A
Logic Diagram
CLR (11)
(10)
R
R
(9)
(7)
(6)
(5)
(3)
(2)
(4)
(13)
(12)
(14)
(15)
(1)
Q 1
Q 2
Q 3
Q 4
Q 5
Q 6
Q 7
T
T
R
R
Q 8
T
T
R
R
Q 9
T
T
R
R
Q 10
Q 11
Q 12
T
T
R
R
T
T
R
R
T
T
Rev.2.00 Jul. 20, 2004 page 4 of 10
HD74LV4040A
Timing Diagram
1
2
3
4
8
16
32
64
128
256
512
1024
2048
4096
CLR
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
COUNT
CLEAR
CLEAR
DC Electrical Characteristics
Ta = –40 to 85°C
Item
Symbol VCC (V)*
VIH 2.0
Min
1.5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
Unit Test Conditions
Input voltage
V
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
2.0
V
V
V
CC×0.7
CC×0.7
CC×0.7
VIL
—
—
—
—
0.5
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
VCC×0.3
VCC×0.3
VCC×0.3
Output voltage
VOH
Min to Max VCC–0.1
—
—
—
—
0.1
0.4
0.44
0.55
±1
V
IOH = –50 µA
IOH = –2 mA
2.3
3.0
4.5
2.0
2.48
3.8
—
—
—
—
—
—
IOH = –6 mA
IOH = –12 mA
IOL = 50 µA
IOL = 2 mA
IOL = 6 mA
VOL
Min to Max
2.3
3.0
4.5
IOL = 12 mA
Input current
Quiescent supply
current
IIN
ICC
0 to 5.5
5.5
µA
µA
VIN = 5.5 V or GND
VIN = VCC or GND, IO = 0
20
Output leakage current IOFF
Input capacitance CIN
0
3.3
—
—
—
3.7
5
—
µA
pF
VI or VO = 0 to 5.5 V
VI = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Rev.2.00 Jul. 20, 2004 page 5 of 10
HD74LV4040A
Switching Characteristics
VCC = 2.5 ± 0.2 V
TO
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
(Input)
Item
Symbol
Unit Conditions
(Output)
Min Typ Max Min
Max
—
—
Maximum
fmax
50
30
—
—
—
—
—
90
60
—
—
40
25
MHz CL = 15 pF
CL = 50 pF
clock frequency
Propagation
delay time
tPLH/tPHL
tPHL
10.0 16.0 1.0
12.7 19.6 1.0
9.9
18.3
22.2
17.5
20.4
6.3
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
CLK
CLR
Qn
Q1
15.4 1.0
11.8 18.0 1.0
Propagation
∆tpd
tSU
tw
3.0
—
5.5
—
—
ns
ns
ns
Qn+1
delay time skew
Setup time
Pulse width
7.0
7.0
—
CLR inactive before
CLK ↓
7.0
7.0
—
—
—
—
7.0
7.0
—
—
CLK high or low
CLR high
VCC = 3.3 ± 0.3 V
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
(Input)
TO
Item
Symbol
Unit Conditions
(Output)
Min Typ Max Min
Max
—
—
Maximum
fmax
75
55
—
—
—
—
—
140
80
7.5
—
—
70
50
MHz CL = 15 pF
CL = 50 pF
clock frequency
Propagation
delay time
tPLH/tPHL
tPHL
11.9 1.0
14.0
17.5
15.0
18.5
5.0
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
CLK
CLR
Qn
Q1
10.0 15.4 1.0
8.3 12.8 1.0
10.8 16.3 1.0
Propagation
∆tpd
tSU
tw
2.4
4.4
—
ns
ns
ns
Qn+1
delay time skew
Setup time
Pulse width
5.0
—
—
5.0
—
CLR inactive before
CLK ↓
CLK high or low
CLR high
5.0
5.0
—
—
—
—
5.0
5.0
—
—
Rev.2.00 Jul. 20, 2004 page 6 of 10
HD74LV4040A
Switching Characteristics (Cont.)
VCC = 5.0 ± 0.5 V
TO
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
(Input)
Item
Symbol
Unit Conditions
(Output)
Min Typ Max Min
Max
—
—
Maximum
fmax
150 210
—
—
7.3
9.3
8.6
125
80
MHz CL = 15 pF
CL = 50 pF
clock frequency
Propagation
delay time
95
—
—
—
—
—
125
4.8
6.3
5.6
7.1
1.6
tPLH/tPHL
tPHL
1.0
1.0
1.0
8.5
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
CLK
CLR
Qn
Q1
10.5
10.0
12.0
3.5
10.6 1.0
Propagation
∆tpd
tSU
tw
3.1
—
ns
ns
ns
Qn + 1
delay time skew
Setup time
Pulse width
5.0
—
—
5.0
—
CLR inactive before
CLK ↓
5.0
5.0
—
—
—
—
5.0
5.0
—
—
CLK high or low
CLR high
Operating Characteristics
CL = 50 pF
Ta = 25°C
Item
Symbol VCC = (V)
Unit
Test Conditions
Min
—
—
Typ
17.3
19.0
Max
—
—
Power dissipation capacitance CPD
3.3
5.0
pF
f = 10 MHz
Noise Characteristics
CL = 50 pF
Test Conditions
Ta = 25°C
Min
Item
Symbol VCC = (V)
Unit
Typ
Max
Quiet output, maximum
dynamic VOL
Quiet output, minimum
dynamic VOL
Quiet output, minimum
dynamic VOH
High-level dynamic input
voltage
VOL (P)
VOL (V)
VOH (V)
VIH (D)
VIL (D)
3.3
3.3
3.3
3.3
3.3
—
0.4
0.8
V
—
–0.5
3.0
—
–0.8
—
V
V
V
V
—
2.31
—
—
Low-level dynamic input
voltage
—
0.99
Rev.2.00 Jul. 20, 2004 page 7 of 10
HD74LV4040A
Test Circuit
Measurement point
*
CL
Note: CL includes the probe and jig capacitance.
Waveform
− 1
tf
tr
VCC
90%
50% VCC
10%
GND
tW
tW
1/fmax
tPLH
tPHL
50% VCC
Q1
Waveform
− 2
VCC
50% VCC
GND
tsu
tW
VCC
50% VCC
CLR
GND
tPHL
Any Q
50% VCC
Rev.2.00 Jul. 20, 2004 page 8 of 10
HD74LV4040A
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
9
16
1
8
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
Package Code
JEDEC
FP-16DAV
—
JEITA
Mass (reference value)
Conforms
0.24 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
9.9
10.3 Max
9
8
16
1
1.27
+ 0.10
6.10
– 0.30
1.08
0.635 Max
0˚ – 8˚
+ 0.67
0.60
– 0.20
*0.40 ± 0.06
0.15
0.25
M
Package Code
JEDEC
JEITA
FP-16DNV
Conforms
Conforms
0.15 g
*Ni/Pd/Au plating
Mass (reference value)
Rev.2.00 Jul. 20, 2004 page 9 of 10
HD74LV4040A
As of January, 2003
Unit: mm
5.00
5.30 Max
16
9
1
8
0.65
0.13 M
0.65 Max
1.0
*0.20 ± 0.05
6.40 ± 0.20
0˚ – 8˚
0.50 ± 0.10
0.10
Package Code
JEDEC
TTP-16DAV
—
JEITA
—
*Ni/Pd/Au plating
Mass (reference value)
0.05 g
Rev.2.00 Jul. 20, 2004 page 10 of 10
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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