HD74LV540ATELL [RENESAS]
Octal Inverted Buffers / Drivers with 3-state Outputs; 八路反向缓冲器/驱动器与3态输出
| 型号： | HD74LV540ATELL |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Octal Inverted Buffers / Drivers with 3-state Outputs |
| 文件： | 总10页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74LV540A
Octal Inverted Buffers / Drivers with 3-state Outputs
REJ03D0334–0200Z
(Previous ADE-205-277 (Z))
Rev.2.00
Jun. 28, 2004
Description
The HD74LV540A has eight inverter drivers with three state outputs in a 20 pin package. When OE1 and OE2 is low
level, this drivers set up output is enable. Low-voltage operation is suitable for battery-powered products (e.g.,
notebook computers), and the low-power consumption extends the battery life.
Features
•
•
•
•
•
•
•
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V)
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LV540AFPEL
HD74LV540ARPEL
HD74LV540ATELL
SOP–20 pin (JEITA)
SOP–20 pin (JEDEC)
TSSOP–20 pin
FP–20DAV
FP–20DBV
TTP–20DAV
FP
RP
T
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
Output Y
H
OE1
L
OE2
L
A
L
L
L
H
X
X
L
H
X
Z
Z
X
H
Note: H: High level
L: Low level
X: Immaterial
Z: High impedance
Rev.2.00 Jun. 28.2004 page 1 of 9
HD74LV540A
Pin Arrangement
1
2
3
4
5
6
7
8
9
20 VCC
OE1
A1
A2
A3
A4
A5
A6
A7
A8
19
18
17
16
15
14
13
12
11
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
GND 10
(Top view)
Absolute Maximum Ratings
Item
Symbol
VCC
Ratings
Unit
Conditions
Supply voltage range
Input voltage range*1
Output voltage range*1, 2
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
V
V
V
VI
VO
Output: H or L
VCC: OFF or Output: Z
VI < 0
Input clamp current
IIK
IOK
IO
mA
mA
mA
mA
Output clamp current
Continuous output current
±50
VO < 0 or VO > VCC
VO = 0 to VCC
±35
Continuous current through
VCC or GND
ICC or IGND ±70
Maximum power dissipation at PT
Ta = 25°C (in still air)*3
835
mW
SOP
757
TSSOP
Storage temperature
Tstg
–65 to 150
°C
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.2.00 Jun. 28, 2004 page 2 of 9
HD74LV540A
Recommended Operating Conditions
Item
Symbol
VCC
Min
2.0
0
Max
5.5
5.5
VCC
5.5
–50
–2
Unit
V
Conditions
Supply voltage range
Input voltage range
Output voltage range
VI
V
VO
0
V
H or L
0
High impedance state
VCC = 2.0 V
Output current
IOH
—
—
—
—
—
—
—
—
0
µA
mA
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.0 V
–8
–16
50
IOL
µA
2
mA
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
8
16
Input transition rise or fall rate
Operating free-air temperature
∆t/∆v
200
100
20
ns/V
°C
0
0
VCC = 4.5 to 5.5 V
Ta
–40
85
Note: Unused or floating inputs must be held high or low.
Logic Diagram
1
OE1
19
OE2
2
18
A1
Y1
To Seven Other Channels
Rev.2.00 Jun. 28, 2004 page 3 of 9
HD74LV540A
DC Electrical Characteristics
Ta = –40 to 85°C
Unit Test Conditions
V
Item
Symbol
V
CC (V)*
Min
Typ Max
Input voltage
VIH
2.0
1.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.5
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
2.0
V
V
V
CC × 0.7
CC × 0.7
CC × 0.7
VIL
—
—
—
—
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
V
V
V
CC × 0.3
CC × 0.3
CC × 0.3
Output voltage
VOH
Min to Max VCC – 0.1
—
V
IOH = –50 µA
IOH = –2 mA
IOH = –8 mA
IOH = –16 mA
IOL = 50 µA
2.3
2.0
2.48
3.8
—
—
3.0
—
4.5
—
VOL
Min to Max
2.3
0.1
0.4
0.44
0.55
±1
—
IOL = 2 mA
3.0
—
IOL = 8 mA
4.5
—
IOL = 16 mA
Input current
IIN
0 to 5.5
5.5
—
µA
µA
VIN = 5.5 V or GND
VO = VCC or GND
Off-state output
current
IOZ
—
±5
Quiescent supply
current
ICC
5.5
0
—
—
—
—
—
3
20
5
µA
µA
pF
VIN = VCC or GND, IO = 0
VI or VO = 0 V to 5.5 V
VI = VCC or GND
Output leakage
current
IOFF
Input capacitance
CIN
3.3
—
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Rev.2.00 Jun. 28, 2004 page 4 of 9
HD74LV540A
Switching Characteristics
VCC = 2.5 ± 0.2 V
TO
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
(Input)
Item
Symbol
Unit
Conditions
(Output)
Min Typ Max Min
Max
14.5
18.5
21.0
25.5
19.0
25.5
Propagation
delay time
tPLH
tPHL
tZH
tZL
—
—
—
—
—
—
7.4
9.3
8.2
9.6
7.5
12.0 1.0
16.8 1.0
17.4 1.0
22.2 1.0
16.0 1.0
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
A
Y
Y
Y
Enable time
ns
ns
OE
OE
Disable time
tHZ
tLZ
10.5 22.3 1.0
VCC = 3.3 ± 0.3 V
TO
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
(Input)
Item
Symbol
Unit
Conditions
(Output)
Min Typ Max Min
Max
8.5
Propagation
delay time
tPLH
tPHL
tZH
tZL
—
—
—
—
—
—
5.3
6.8
6.2
7.6
5.3
7.0
7.0
1.0
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
A
Y
Y
Y
10.5 1.0
10.5 1.0
14.0 1.0
10.5 1.0
15.4 1.0
12.0
12.5
16.0
12.5
17.5
Enable time
ns
ns
OE
OE
Disable time
tHZ
tLZ
VCC = 5.0 ± 0.5 V
TO
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
(Input)
Item
Symbol
Unit
Conditions
(Output)
Min Typ Max Min
Max
6.0
Propagation
delay time
tPLH
tPHL
tZH
tZL
—
—
—
—
—
—
3.8
5.0
4.6
5.8
3.6
5.3
5.0
7.0
7.2
9.2
6.8
8.8
1.0
1.0
1.0
1.0
1.0
1.0
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
A
Y
Y
Y
8.0
Enable time
8.5
ns
ns
OE
OE
10.5
8.0
Disable time
tHZ
tLZ
10.0
Output-skew Characteristics
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol
VCC = (V)
Unit
Min
—
Max
2.0
1.5
1.0
Min
—
Max
Output skew
tsk (O)
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
2.0
1.5
1.0
ns
—
—
—
—
Note: Skew between any outputs of the same package switching in the same direction. This parameter is warranted
but not production tested.
Rev.2.00 Jun. 28, 2004 page 5 of 9
HD74LV540A
Operating Characteristics
CL = 50 pF
Ta = 25°C
Item
Symbol VCC = (V)
Unit
Test Conditions
f = 10 MHz
Min
—
Typ
23.0
27.5
Max
—
Power dissipation capacitance CPD
3.3
5.0
pF
—
—
Noise Characteristics
CL = 50 pF
Test Conditions
Ta = 25°C
Min
Item
Symbol VCC = (V)
Unit
Typ
Max
Quiet output, maximum
dynamic VOL
VOL (P)
VOL (V)
VOH (V)
VIH (D)
VIL (D)
3.3
3.3
3.3
3.3
3.3
—
0.4
0.8
V
Quiet output, minimum
dynamic VOL
—
–0.3
2.9
—
–0.8
—
V
V
V
V
Quiet output, minimum
dynamic VOH
—
High-level dynamic input
voltage
2.31
—
—
Low-level dynamic input
voltage
—
0.99
Test Circuit
Output
1 kΩ
OPEN
GND
VCC
S2
CL
TEST
tPLH/tPHL
tZH/tHZ
tZL /tLZ
S2
OPEN
GND
VCC
Note: CL includes the probe and jig capacitance.
Rev.2.00 Jun. 28, 2004 page 6 of 9
HD74LV540A
• Waveform
tr
tf
VCC
90%
90%
50%VCC
50%VCC
Input A
10%
tPLH
10%
GND
tPHL
VOH
50%VCC
50%VCC
Output Y
VOL
tf
tr
VCC
90%
90%
Input OE
50%VCC
50%VCC
10%
10%
GND
VCC
tZL
tLZ
Waveform
Waveform
−
−
A
B
50%VCC
tZH
V
OL + 0.3 V
VOL
VOH
tHZ
VOH− 0.3 V
50%VCC
GND
Notes:
1. tr ≤ 3 ns, tf ≤ 3 ns
2. Input waveform: PRR ≤ 1 MHZ, duty cycle 50%
3. Waveform-A is for an output with internal conditions such that the output is low except
when disabled by the output control.
4. Waveform-B is for an output with internal conditions such that the output is high except
when disabled by the output control.
Rev.2.00 Jun. 28, 2004 page 7 of 9
HD74LV540A
Package Dimensions
As of January, 2002
Unit: mm
12.6
13 Max
11
10
20
1
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
0.12 M
Package Code
JEDEC
FP–20DAV
—
JEITA
Mass (reference value)
Conforms
0.31 g
*Pd plating
As of January, 2003
Unit: mm
12.8
13.2 Max
11
10
20
1
+ 0.25
– 0.40
10.40
0.935 Max
1.45
0˚ – 8˚
+ 0.57
– 0.30
1.27
0.70
*0.40 ± 0.06
0.15
M
0.12
Package Code
JEDEC
JEITA
FP-20DBV
Conforms
—
*Ni/Pd/Au plating
Mass (reference value)
0.52 g
Rev.2.00 Jun. 28, 2004 page 8 of 9
HD74LV540A
As of January, 2002
Unit: mm
6.50
6.80 Max
20
11
1
10
0.65
1.0
*0.20 ± 0.05
0.13
M
6.40 ± 0.20
0.65 Max
0˚ – 8˚
0.50 ± 0.10
0.10
Package Code
JEDEC
TTP–20DAV
—
JEITA
—
*Pd plating
Mass (reference value)
0.07 g
Rev.2.00 Jun. 28, 2004 page 9 of 9
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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