HD74LVU04A [RENESAS]

Hex Inverters; 六路反向器
HD74LVU04A
型号: HD74LVU04A
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

Hex Inverters
六路反向器

文件: 总8页 (文件大小:65K)
中文:  中文翻译
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HD74LVU04A  
Hex Inverters  
REJ03D0228–0200Z  
(Previous ADE-205-248 (Z))  
Rev.2.00  
May 21, 2004  
Description  
The HD74LVU04A has six inverters with unbuffered outputs in a 14-pin package.  
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the  
low-power consumption extends the battery life.  
Features  
VCC = 2.0 V to 5.5 V operation  
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)  
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)  
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)  
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)  
Output current  
±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)  
Ordering Information  
Part Name  
Package Type  
Package Code  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
HD74LVU04AFPEL  
HD74LVU04ARPEL  
HD74LVU04ATELL  
SOP–14 pin(JEITA)  
SOP–14 pin(JEDEC)  
TSSOP–14 pin  
FP–14DAV  
FP–14DNV  
TTP–14DV  
FP  
RP  
T
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
ELL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Function Table  
Input A  
Output Y  
H
L
L
H
Note: H: High level  
L: Low level  
Rev.2.00, May 21.2004, page 1 of 7  
HD74LVU04A  
Pin Arrangement  
VCC  
6A  
6Y  
5A  
5Y  
4A  
4Y  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1A  
1Y  
2A  
2Y  
3A  
3Y  
GND  
8
(Top view)  
Absolute Maximum Ratings  
Item  
Symbol  
VCC  
VI  
Ratings  
Unit  
Conditions  
Supply voltage range  
Input voltage range*1  
Output voltage range*1, 2  
Input clamp current  
Output clamp current  
Continuous output current  
–0.5 to 7.0  
–0.5 to 7.0  
V
V
V
VO  
–0.5 to VCC + 0.5  
Output: H or L  
VI < 0  
IIK  
–20  
±50  
±25  
mA  
mA  
mA  
mA  
IOK  
VO < 0 or VO > VCC  
VO = 0 to VCC  
IO  
Continuous current through  
VCC or GND  
ICC or IGND ±50  
Maximum power dissipation at PT  
Ta = 25°C (in still air)*3  
785  
mW  
SOP  
500  
TSSOP  
Storage temperature  
Tstg  
–65 to 150  
°C  
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of  
which may be realized at the same time.  
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are  
observed.  
2. This value is limited to 5.5 V maximum.  
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.  
Rev.2.00, May 21, 2004, page 2 of 7  
HD74LVU04A  
Recommended Operating Conditions  
Item  
Symbol  
VCC  
VI  
Min  
2.0  
0
Max  
5.5  
5.5  
VCC  
–50  
–2  
Unit  
V
Conditions  
Supply voltage range  
Input voltage range  
Output voltage range  
Output current  
V
VO  
0
V
IOH  
–40  
µA  
mA  
VCC = 2.0 V  
VCC = 2.3 to 2.7 V  
VCC = 3.0 to 3.6 V  
VCC = 4.5 to 5.5 V  
VCC = 2.0 V  
–6  
–12  
50  
IOL  
µA  
2
mA  
VCC = 2.3 to 2.7 V  
VCC = 3.0 to 3.6 V  
VCC = 4.5 to 5.5 V  
6
12  
Operating free-air temperature  
Ta  
85  
°C  
Note: Unused or floating inputs must be held high or low.  
Logic Diagram  
A
Y
Rev.2.00, May 21, 2004, page 3 of 7  
HD74LVU04A  
DC Electrical Characteristics  
Ta = –40 to 85°C  
Unit Test Conditions  
Item  
Symbol  
VCC (V)*  
Min  
Typ Max  
Input voltage  
VIH  
2.0  
1.7  
0.3  
V
2.3 to 2.7  
3.0 to 3.6  
4.5 to 5.5  
2.0  
V
V
V
CC × 0.8  
CC × 0.8  
CC × 0.8  
VIL  
2.3 to 2.7  
3.0 to 3.6  
4.5 to 5.5  
V
V
V
CC × 0.2  
CC × 0.2  
CC × 0.2  
Output voltage  
VOH  
Min to Max VCC – 0.1  
V
V
IOL = –50 µA  
IOL = –2 mA  
2.3  
2.0  
2.48  
3.8  
3.0  
IOL = –6 mA  
4.5  
IOL = –12 mA  
IOL = 50 µA  
VOL  
Min to Max  
2.3  
0.1  
0.4  
0.44  
0.55  
±1  
IOL = 2 mA  
3.0  
IOL = 6 mA  
4.5  
IOL = 12 mA  
Input current  
IIN  
0 to 5.5  
5.5  
µA  
µA  
VIN = 5.5 V or GND  
VIN = VCC or GND, IO = 0  
Quiescent supply  
current  
ICC  
20  
Input capacitance  
CIN  
3.3  
4.0  
pF  
VI = VCC or GND  
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.  
Switching Characteristics  
VCC = 2.5 ± 0.2 V  
TO  
Ta = 25°C  
Ta = –40 to 85°C  
Test  
Conditions  
FROM  
(Input)  
(Output)  
Item  
Symbol  
Unit  
Min Typ Max Min  
Max  
14.0  
16.0  
Propagation  
delay time  
tPLH  
tPHL  
3.2  
6.6  
10.9 1.0  
13.4 1.0  
ns  
CL = 15 pF  
CL = 50 pF  
A
Y
VCC = 3.3 ± 0.3 V  
Ta = 25°C  
Ta = –40 to 85°C  
Test  
Conditions  
FROM  
(Input)  
TO  
(Output)  
Item  
Symbol  
Unit  
Min Typ Max Min  
Max  
10.5  
13.0  
Propagation  
delay time  
tPLH  
tPHL  
2.5  
4.7  
8.9  
1.0  
ns  
CL = 15 pF  
CL = 50 pF  
A
Y
11.4 1.0  
VCC = 5.0 ± 0.5 V  
TO  
Ta = 25°C  
Ta = –40 to 85°C  
Test  
FROM  
(Input)  
Item  
Symbol  
Unit Conditions  
(Output)  
Min Typ Max Min  
Max  
6.5  
Propagation  
delay time  
tPLH  
tPHL  
2.2  
3.9  
5.5  
7.0  
1.0  
1.0  
ns  
CL = 15 pF  
CL = 50 pF  
A
Y
8.0  
Rev.2.00, May 21, 2004, page 4 of 7  
HD74LVU04A  
Operating Characteristics  
CL = 50 pF  
Ta = 25°C  
Item  
Symbol  
VCC (V)  
Unit  
Test Conditions  
f = 10 MHz  
Min  
Typ  
5.6  
6.7  
Max  
Power dissipation capacitance CPD  
3.3  
5.0  
pF  
Noise Characteristics  
CL = 50 pF  
Test Conditions  
Ta = 25°C  
Min  
Item  
Symbol  
VCC (V)  
Unit  
Typ  
Max  
Quiet output, maximum  
dynamic VOL  
VOL (P)  
VOL (V)  
VOH (V)  
VIH (D)  
3.3  
0.5  
0.8  
V
Quiet output, minimum  
dynamic VOL  
3.3  
3.3  
3.3  
3.3  
–0.1  
3.0  
–0.8  
V
V
V
V
Quiet output, minimum  
dynamic VOH  
High-level dynamic put  
voltage  
2.31  
Low-level dynamic put voltage VIL (D)  
0.99  
Test Circuit  
Measurement point  
*
C L  
Note: CL includes the probe and jig capacitance.  
Rev.2.00, May 21, 2004, page 5 of 7  
HD74LVU04A  
Waveform 1  
tr  
tf  
VCC  
0 V  
90%  
50% VCC  
90%  
50% VCC  
Input  
10%  
10%  
tPHL  
tPLH  
VOH  
In phase output  
50% VCC  
50% VCC  
50% VCC  
tPLH  
VOL  
tPHL  
VOH  
50% VCC  
Out of phase output  
VOL  
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , t r3 ns, t f 3 ns  
2. The output are measured one at a time with one transition per measurement.  
Package Dimensions  
As of January, 2003  
Unit: mm  
10.06  
10.5 Max  
8
14  
1
7
+ 0.20  
7.80  
– 0.30  
1.42 Max  
1.15  
0˚ – 8˚  
1.27  
0.70 ± 0.20  
*0.40 ± 0.06  
0.15  
M
0.12  
Package Code  
JEDEC  
FP-14DAV  
JEITA  
Mass (reference value)  
Conforms  
0.23 g  
*Ni/Pd/Au plating  
Rev.2.00, May 21, 2004, page 6 of 7  
HD74LVU04A  
As of January, 2003  
Unit: mm  
8.65  
9.05 Max  
8
14  
1
7
+ 0.10  
6.10  
– 0.30  
0.635 Max  
1.08  
0˚ – 8˚  
+ 0.67  
1.27  
0.60  
– 0.20  
*0.40 ± 0.06  
0.15  
M
0.25  
Package Code  
JEDEC  
JEITA  
FP-14DNV  
Conforms  
Conforms  
0.13 g  
*Ni/Pd/Au plating  
Mass (reference value)  
As of January, 2003  
Unit: mm  
5.00  
5.30 Max  
14  
8
1
7
0.65  
1.0  
*0.20 ± 0.05  
0.13 M  
6.40 ± 0.20  
0.83 Max  
0˚ – 8˚  
0.50 ± 0.10  
0.10  
Package Code  
JEDEC  
TTP-14DV  
JEITA  
*Ni/Pd/Au plating  
Mass (reference value)  
0.05 g  
Rev.2.00, May 21, 2004, page 7 of 7  
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan  
Keep safety first in your circuit designs!  
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble  
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.  
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary  
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.  
Notes regarding these materials  
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's  
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.  
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,  
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.  
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of  
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is  
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product  
information before purchasing a product listed herein.  
The information described here may contain technical inaccuracies or typographical errors.  
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.  
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor  
home page (http://www.renesas.com).  
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to  
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes  
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8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.  
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http://www.renesas.com  
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© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.  
Colophon .1.0  

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