HI5813JIJ [RENESAS]
1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24, CERDIP-24;
| 型号： | HI5813JIJ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24, CERDIP-24 CD 转换器 |
| 文件： | 总11页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI5813
CMOS 3.3V, 25 Microsecond, 12-Bit, Sampling
A/D Converter with Internal Track and Hold
August 1997
[ /Title
(HI581
3)
/Sub-
ject
(CMO
S
3.3V,
25
Micro-
sec-
ond,
12-
Bit,
Sam-
pling
A/D
Con-
verter
with
Inter-
nal
Track
and
Features
Description
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 25µs The HI5813 is a 3.3V, very low power, 12-bit, successive
approximation analog-to-digital converter. It can operate
from a single 3V to 6V supply and typically draws a maxi-
mum of 1.0mA (at 25 C) when operating at 3.3V. The
HI5813 features a built-in track and hold. The conversion
time is as low as 25µs with a 3.3V supply.
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .40 KSPS
o
• Built-In Track and Hold
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . +3.3V
o
• Maximum Power Consumption at 25 C. . . . . . . . 3.3mW
The twelve data outputs feature full high speed CMOS three-
state bus driver capability, and are latched and held through
a full conversion cycle. The output is user selectable: (i.e.)
12-bit , 8-bit (MSBs), and/or 4-bit (LSBs). A data ready flag
and conversion start input complete the digital interface.
Applications
• Remote Low Power Data Acquisition Systems
• Battery Operated Systems
Ordering Information
• Pen Based PC Handheld Scanners
• DSP Modems
INL (LSB)
TEMP.
PART
(MAX OVER RANGE
PKG.
NO.
o
• General Purpose DSP Front End
• µP Controlled Measurement Systems
• PCMCIA Type II Compliant
NUMBER
TEMP.)
±4.0
±2.5
±4.0
±2.5
±4.0
±2.5
( C)
PACKAGE
HI5813JIP
HI5813KIP
HI5813JIB
HI5813KIB
HI5813JIJ
HI5813KIJ
-40 to 85 24 Ld PDIP
-40 to 85 24 Ld PDIP
-40 to 85 24 Ld SOIC
-40 to 85 24 Ld SOIC
E24.3
E24.3
M24.3
M24.3
• PC Based Industrial Controls/DAQ Systems
-40 to 85 24 Ld CERDIP F24.3
-40 to 85 24 Ld CERDIP F24.3
Hold)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
Semi-
con-
ductor,
A/D,
ADC,
flash,
Pinout
HI5813 (PDIP, CERDIP, SOIC)
TOP VIEW
DRDY
(LSB) D0
D1
1
2
3
4
5
6
7
8
9
24
V
DD
23 OEL
22 CLK
21 STRT
D2
D3
20 V
19 V
-
REF
REF
D4
+
D5
18
V
IN
D6
17 V
+
AA
D7
16
V
-
AA
D8 10
D9 11
15 OEM
14 D11 (MSB)
13 D10
V
12
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number 3634.1
6-1802
HI5813
Functional Block Diagram
STRT
V
DD
TO INTERNAL LOGIC
V
SS
V
IN
CLK
CLOCK
CONTROL
AND
TIMING
DRDY
32C
OEM
V
+
REF
16C
8C
D11 (MSB)
50Ω
SUBSTRATE
D10
D9
D8
D7
D6
4C
2C
V
+
AA
C
V
-
32C
AA
64C
63
16C
12-BIT
12-BIT EDGE
TRIGGERED
“D” LATCHED
SUCCESSIVE
APPROXIMATION
REGISTER
8C
4C
2C
D5
D4
D3
C
C
P1
D2
D1
V
-
REF
D0 (LSB)
OEL
6-1803
HI5813
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage
Thermal Resistance (Typical, Note 1)
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . .
CERDIP Package . . . . . . . . . . . . . . . .
Maximum Junction Temperature
θ
( C/W)
θ
( C/W)
JA
JC
V
to V
. . . . . . . . . . . . . . . . . . . .(V -0.5V) < V < +6.5V
SS DD
80
75
60
N/A
N/A
12
DD
SS
V
+ to V -. . . . . . . . . . . . . . . . . . . . (V -0.5V) to (V +6.5V)
AA AA SS SS
V
+ to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
DD
AA
Analog and Reference Inputs
, V +, V - . . . . . . . . . (V -0.3V) < V
o
V
< (V
+0.3V)
+0.3V)
PDIP and SOIC Packages. . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300 C
IN REF REF SS INA
DD
DD
o
Digital I/O Pins . . . . . . . . . . . . . . (V -0.3V) < VI/O < (V
SS
ο
o
o
Operating Conditions
(SOIC - Lead Tips Only)
Temperature Range
PDIP, SOIC, and CERDIP Packages . . . . . . . . . . . -40 C to 85 C
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
V
= V + = V
AA
+ = 3.3V, V = V - = V
REF SS AA
- = GND, CLK = 600kHz (J suffix),
REF
DD
CLK = 500kHz (K suffix), Unless Otherwise Specified
o
o
o
25 C
-40 C TO 85 C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
ACCURACY
Resolution
12
-
-
-
-
-
-
-
-
-
-
-
12
-
-
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Integral Linearity Error, INL
(End Point)
J
±4.0
±2.5
±4.0
±2.0
±2.0
±2.0
±3.0
±2.5
±4.0
±2.5
±4.0
±2.0
±2.0
±2.0
±3.0
±2.5
K
J
-
-
Differential Linearity Error, DNL
-
-
K
J
-
-
Gain Error, FSE
(Adjustable to Zero)
-
-
K
J
-
-
Offset Error, V
OS
(Adjustable to Zero)
-
-
K
-
-
DYNAMIC CHARACTERISTICS
Signal to Noise Ratio, SINAD
RMS Signal
J
f
f
= 600kHz, f = 1kHz
IN
-
-
61.5
63.9
-
-
-
-
-
-
dB
dB
S
K
= 500kHz, f = 1kHz
IN
S
RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
J
f
f
= 600kHz, f = 1kHz
IN
-
-
63.2
65.1
-
-
-
-
-
-
dB
dB
S
K
= 500kHz, f = 1kHz
IN
S
RMS Noise
Total Harmonic Distortion, THD
J
f
f
f
f
= 750kHz, f = 1kHz
IN
-
-
-
-
-68.4
-70.8
69.0
71.8
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dB
S
S
S
S
K
J
= 750kHz, f = 1kHz
IN
Spurious Free Dynamic Range,
SFDR
= 600kHz, f = 1kHz
IN
K
= 500kHz, f = 1kHz
IN
dB
ANALOG INPUT
Input Current, Dynamic
Input Current, Static
At V = V
IN
+, 0V
-
-
±50
±100
±10
-
-
±100
±10
µA
µA
REF
Conversion Stopped
±0.4
6-1804
HI5813
Electrical Specifications
V
= V + = V
AA
+ = 3.3V, V = V - = V
- = GND, CLK = 600kHz (J suffix),
REF
DD
REF
SS
AA
CLK = 500kHz (K suffix), Unless Otherwise Specified (Continued)
o
o
o
25 C
-40 C TO 85 C
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX
MIN
MAX
UNITS
MHz
µA
Input Bandwidth -3dB
-
-
-
-
-
-
-
-
-
Reference Input Current
160
420
-
-
Input Series Resistance, R
In Series with Input
Ω
S
C
SAMPLE
Input Capacitance, C
Input Capacitance, C
During Sample State
During Hold State
-
-
380
20
-
-
-
-
-
-
pF
pF
SAMPLE
HOLD
DIGITAL INPUTS OEL, OEM, STRT
High-Level Input Voltage, V
IH
2.4
-
-
-
2.4
-
0.8
±10
-
V
V
Low-Level Input Voltage, V
-
-
-
0.8
±10
-
-
-
IL
Input Leakage Current, I
IL
Except CLK, V = 0V, 5V
IN
-
µA
pF
Input Capacitance, C
10
IN
DIGITAL OUTPUTS
High-Level Output Voltage, V
I
I
= -400µA
2.6
-
-
-
-
2.6
-
V
V
OH
SOURCE
Low-Level Output Voltage, V
= 1.6mA
-
-
0.4
±10
-
-
0.4
±10
OL
SINK
Three-State Leakage, I
Except DRDY, V
3.3V
= 0V,
OUT
µA
OZ
Output Capacitance, C
Except DRDY
-
20
-
-
-
pF
OUT
TIMING
Conversion Time (t
(Includes Acquisition Time)
+ t
)
J
25
-
-
-
-
25
-
-
µs
µs
MHz
ns
CONV
ACQ
K
30
30
Clock Frequency
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
0.05
-
0.75
-
0.05
0.75
-
Clock Pulse Width, t
, t
LOW HIGH
100
-
100
Aperture Delay, t APR
-
-
35
180
180
30
60
15
110
65
95
50
210
220
-
-
-
70
240
250
-
ns
D
Clock to Data Ready Delay, t DRDY
D1
ns
Clock to Data Ready Delay, t DRDY
D2
-
-
ns
Start Removal Time, t STRT
75
85
-
75
30
-
ns
R
Start Setup Time, t STRT
SU
-
-
ns
Start Pulse Width, t STRT
25
130
75
110
25
160
80
130
ns
W
Start to Data Ready Delay, t DRDY
D3
-
-
ns
Output Enable Delay, t
-
-
ns
EN
Output Disabled Delay, t
-
-
ns
DIS
POWER SUPPLY CHARACTERISTICS
Supply Current, I
NOTE:
+ I
AA
-
0.5
1
-
2.5
mA
DD
2. Parameter guaranteed by design or characterization, not production tested.
6-1805
HI5813
Timing Diagrams
5 - 14
4
15
1
3
1
2
2
3
CLK
t
LOW
t
DRDY
D1
t
HIGH
STRT
DRDY
t
DRDY
D2
DATA N - 1
D0 - D11
DATA N
HOLD N
V
IN
TRACK N
TRACK N + 1
OEL = OEM = V
SS
FIGURE 1. CONTINUOUS CONVERSION MODE
2
2
3
15
2
4
1
5
CLK
t
STRT
t STRT
SU
R
t
STRT
W
STRT
t
DRDY
D3
DRDY
HOLD
HOLD
TRACK
V
IN
FIGURE 2. SINGLE SHOT MODE
6-1806
HI5813
Timing Diagrams (Continued)
OEL OR OEM
t
t
DIS
EN
1.6mA
90%
50%
D0 - D3 OR D4 - D11
HIGH IMPEDANCE
TO HIGH
+2.1V
TO
OUTPUT
PIN
50pF
HIGH
IMPEDANCE
50%
TO LOW
10%
-1.6mA
FIGURE 3A.
FIGURE 3. OUTPUT ENABLE/DISABLE TIMING DIAGRAM
FIGURE 3B.
INPUT FREQUENCY = 1kHz
SAMPLING RATE = 33kHz
SNR = 65.55dB
1.6mA
SINAD = 64.18dB
EFFECTIVE BITS = 10.37
THD = -70.02dBc
PEAK NOISE = -70.9dB
SFDR = 71.1dB
+2.1V
50pF
-400µA
FREQUENCY
FIGURE 4. GENERAL TIMING LOAD CIRCUIT
FIGURE 5. FFT SPECTRUM
Typical Performance Curves
4.00
4.00
3.60
3.20
2.80
V
= V + = V + = 3.3V
AA REF
V
= V + = V
AA
+ = 3.3V
REF
3.60
3.20
2.80
DD
DD
CLK = 600kHz
CLK = 500kHz
CLK = 600kHz
CLK = 500kHz
2.40
2.00
1.60
1.20
0.80
0.40
0.00
2.40
2.00
1.60
1.20
0.80
0.40
0.0
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
o
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 7. DNL vs TEMPERATURE
FIGURE 6. INL vs TEMPERATURE
6-1807
HI5813
Typical Performance Curves
1.20
0.00
-0.10
-0.20
-0.30
V
= V + = V
AA
+ = 3.3V
REF
V
= V + = V
AA
+ = 3.3V
REF
DD
DD
1.10
CLK = 500kHz
CLK = 600kHz
1.00
0.90
0.80
-0.40
-0.50
-0.60
-0.70
CLK = 600kHz
CLK = 500kHz
0.70
0.60
0.50
-0.80
-0.90
-1.00
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
o
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 9. FULL SCALE ERROR vs TEMPERATURE
FIGURE 8. OFFSET ERROR vs TEMPERATURE
3.0
2.5
2.0
1.5
1.0
0.5
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
V
= V + = V +
AA REF
V
= V + = V
AA
+ = 3.3V
REF
DD
DD
CLK = 600kHz
CLK = 500kHz
CLK = 500kHz
3.0
3.1
3.2
3.3
3.4
3.5
3.6
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
o
SUPPLY VOLTAGE (V)
TEMPERATURE ( C)
FIGURE 10. SUPPLY CURRENT vs TEMPERATURE
FIGURE 11. DNL vs SUPPLY VOLTAGE
Pin Descriptions
PIN # NAME
DESCRIPTION
PIN # NAME
DESCRIPTION
1
DRDY Output flag signifying new data is available. Goes
high at end of clock period 15. Goes low when new
conversion is started.
14
15
16
17
18
19
D11
Bit 11 (Most significant bit, MSB)
OEM Three-State enable for D4-D11. Active Low Input.
V
-
Analog Ground, (0V).
AA
2
3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Bit 0 (Least Significant Bit, LSB).
V
+
Analog Positive Supply. (+3.3V) (See text.)
Analog Input.
AA
Bit 1.
V
IN
4
Bit 2.
V
+
Reference Voltage Positive Input, sets 4095
code end of input range.
REF
5
Bit 3.
6
Bit 4.
20
21
22
V
-
Reference Voltage Negative Input, sets 0 code
end of input range.
REF
7
Bit 5.
8
Bit 6.
STRT Start Conversion Input active low, recognized af-
ter end of clock period 15.
9
Bit 7.
CLK
CLK Input. Conversion functions are synchronized
to positive going edge. (See text)
10
11
12
13
Bit 8.
Bit 9.
23
24
OEL
Three-State Enable for D0 - D3. Active low input.
Digital Positive Supply (+3.3V).
V
Digital Ground, (0V).
Bit 10.
SS
V
DD
D10
6-1808
HI5813
constants or 1.4µs. The maximum source impedance
(R Max) for a 6µs acquisition time settling to within
0.5 LSB is 1.3kΩ.
Theory of Operation
SOURCE
HI5813 is a CMOS 12-Bit, Analog-to-Digital Converter that
uses capacitor charge balancing to successively
approximate the analog input. A binary weighted capacitor
network forms the A/D heart of the device. See the block
diagram for the HI5813.
If the clock frequency was slower, or the converter was not
restarted immediately (causing a longer sample time), a
higher source impedance could be tolerated.
V
IN
R
SW ≈ 420Ω
The capacitor network has a common node which is
connected to a comparator. The second terminal of each
C
SAMPLE ≈ 380pF
capacitor is individually switchable to the input, V
+ or
REF
R
SOURCE
V
-.
REF
-t
ACQ
- R
SW
R
=
C
During the first three clock periods of a conversion cycle, the
switchable end of every capacitor is connected to the input
and the comparator is being auto balanced at the capacitor
common node.
SOURCE (MAX)
-(N + 1)
ln [2
]
SAMPLE
FIGURE 12. ANALOG INPUT MODEL IN TRACK MODE
Reference Input
During the fourth period, all capacitors are disconnected
from the input; the one representing the MSB (D11) is
The reference input V
REF
impedance source and be well decoupled.
+ should be driven from a low
connected to the V
+ terminal; and the remaining
REF
-. The capacitor common node, after the
capacitors to V
REF
charges balance out, will indicate whether the input was
Current spikes are generated on the reference pin during
each bit test of the successive approximation part of the con-
version cycle as the charge balancing capacitors are
1
above
period, the comparator output is stored and the MSB
capacitor is either left connected to V + (if the comparator
/
of (V
+ - V
-). At the end of the fourth
2
REF
REF
switched between V
- and V + (clock periods 5 - 14).
REF
-. This allows the next
REF
REF
was high) or returned to V
These current spikes must settle completely during each bit
test of the conversion to not degrade the accuracy of the
REF
3
1
comparison to be at either / or / of (V
+ - V
-).
4
4
REF
REF
converter. Therefore V
bypassed. Reference input V
+ and V
- should be well
REF
REF
- is normally connected
directly to the analog ground plane. If V - is biased for
At the end of periods 5 through 14, capacitors representing
D10 through D1 are tested, the result stored, and each
REF
REF
capacitor either left at V
+ or at V
-.
REF
REF
nulling the converters offset it must be stable during the
At the end of the 15th period, when the LSB (D0) capacitor is
tested, (D0) and all the previous results are shifted to the
output registers and drivers. The capacitors are reconnected
to the input, the comparator returns to the balance state, and
the data ready output goes active. The conversion cycle is
now complete.
conversion cycle.
Full Scale and Offset Adjustment
In many applications the accuracy of the HI5813 would be
sufficient without any adjustments. In applications where
accuracy is of utmost importance full scale and offset errors
may be adjusted to zero.
Analog Input
The V
REF
+ and V - pins reference the two ends of the
REF
The analog input pin is a predominately capacitive load that
changes between the track and hold periods of the
conversion cycle. During hold, clock period 4 through 15, the
input loading is leakage and stray capacitance, typically less
than 5µA and 20pF.
analog input range and may be used for offset and full scale
adjustments. In a typical system the V - might be
REF
returned to a clean ground, and the offset adjustment done
on an input amplifier. V + would then be adjusted to null
REF
out the full scale error. When this is not possible, the V
input can be adjusted to null the offset error, however, V
must be well decoupled.
-
-
REF
REF
At the start of input tracking, clock period 1, some charge is
dumped back to the input pin. The input source must have
low enough impedance to dissipate the current spike by the
end of the tracking period. The amount of charge is depen-
dent on supply and input voltages. The average current is
also proportional to clock frequency.
Full scale and offset error can also be adjusted to zero in the
signal conditioning amplifier driving the analog input (V ).
IN
Control Signal
As long as these current spikes settle completely by end of
the signal acquisition period, converter accuracy will be
preserved. The analog input is tracked for 3 clock cycles.
With a clock of 500kHz the track period is 6µs.
The HI5813 may be synchronized from an external source
by using the STRT (Start Conversion) input to initiate conver-
sion, or if STRT is tied low, may be allowed to free run. Each
conversion cycle takes 15 clock periods.
A simplified analog input model is presented in Figure 12.
The input is tracked from clock period 1 through period 3,
then disconnected as the successive approximation takes
During tracking, the A/D input (V ) typically appears as a
IN
380pF capacitor being charged through a 420Ω internal
switch resistance. The time constant is 160ns. To charge
this capacitor from an external “zero Ω” source to 0.5 LSB
(1/8192), the charging time must be at least 9 time
place. After the start of the next period 1 (specified by t
data), the output is updated.
D
6-1809
HI5813
The DRDY (Data Ready) status output goes high (specified noise. A 10µF capacitor from V + to ground would
AA
by t DRDY) after the start of clock period 1, and returns attenuate 30kHz noise by approximately 40dB. Note that
D1
low (specified by t DRDY) after the start of clock period 2.
D2
back to back diodes should be placed from V
DD
to V + to
AA
handle supply to capacitor turn-on or turn-off current spikes.
The 12 data bits are available in parallel on three-state bus
driver outputs. When low, the OEM input enables the most Dynamic Performance
significant byte (D4 through D11) while the OEL input
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the A/D. A low distor-
tion sine wave is applied to the input of the A/D converter.
enables the four least significant bits (D0 - D3). t
specify the output enable and disable times.
and t
EN
DIS
If the output data is to be latched externally, either the trailing The input is sampled by the A/D and its output stored in
edge of data ready or the next falling edge of the clock after RAM. The data is than transformed into the frequency
data ready goes high can be used.
domain with a 4096 point FFT and analyzed to evaluate the
converters dynamic performance such as SNR and THD.
See typical performance characteristics.
Figure 2 shows operation of the HI5813 when the STRT pin
is used to initate a conversion. If STRT is taken high at least
t STRT before clock period 1 and is not reapplied during Signal-To-Noise Ratio
R
that period, the converter will stay in the track mode and the
The signal to noise ratio (SNR) is the measured RMS signal
DRDY output will remain high. A low signal applied to STRT
will bring the DRDY flag low and the conversion will continue
with clock period 3 on the first positive going clock edge that
to RMS sum of noise at a specified input and sampling
frequency. The noise is the RMS sum of all except the
fundamental and the first five harmonic signals. The SNR is
dependent on the number of quantization levels used in the
converter. The theoretical SNR for an N-bit converter with
no differential or integral linearity error is: SNR = (6.02N +
1.76)dB. For an ideal 12-bit converter the SNR is 74dB. Dif-
ferential and integral linearity errors will degrade SNR:
meets the t STRT setup time.
SU
Clock
The clock used to drive the HI5813 can range in frequency
from 50kHz up to 750kHz. All converter functions are syn-
chronized with the rising edge of the clock signal. The clock
can be shut off only during the sample (track) portion of the
conversion cycle. At other times it must be above the mini-
mum frequency shown in the specifications. In the above two
cases, a further restriction applies in that the clock should
not be shut off during the third sample period for more than
1ms. This might cause an internal charge pump voltage to
decay.
Sinewave Signal Power
SNR = 10 Log
Total Noise Power
Signal-To-Noise + Distortion Ratio
SINAD is the measured RMS signal to RMS sum of noise
plus harmonic power and is expressed by the following:
Sinewave Signal Power
SINAD = 10 Log
If the clock is shut off during the conversion time (clock
cycles 4 through 15) of the A/D, the output might be invalid
due to balancing capacitor droop.
Noise + Harmonic Power (2nd - 6th)
Effective Number of Bits
The clock must also meet the minimum t
and t
HIGH
LOW
The effective number of bits (ENOB) is derived from the
SINAD data:
times shown in the specifications. A violation may cause an
internal miscount and invalidate the results.
Power Supplies and Grounding
SINAD - 1.76
ENOB =
6.02
V
and V are the digital supply pins: they power all
SS
DD
internal logic and the output drivers. Because the output
drivers can cause fast current spikes in the V and V
Total Harmonic Distortion
DD
SS
lines, V
ground and V
should have a low impedance path to digital
The total harmonic distortion (THD) is the ratio of the RMS
sum of the second through sixth harmonic components to
the fundamental RMS signal for a specified input and
sampling frequency.
SS
should be well bypassed.
DD
Except for V +, which is a substrate connection to V , all
pins have protection diodes connected to V
AA
DD
and V
.
DD
SS
Input transients above V
the digital supplies.
or below V will get steered to
DD
SS
Total Harmonic Power (2nd - 6th Harmonic)
THD = 10 Log
Sinewave Signal Power
The V + and V - terminals supply the charge balancing
AA AA
comparator only. Because the comparator is autobalanced
between conversions, it has good low frequency supply
rejection. It does not reject well at high frequencies however;
Spurious-Free Dynamic Range
The spurious-free dynamic range (SFDR) is the ratio of the
fundamental RMS amplitude to the rms amplitude of the next
largest spur or spectral component. If the harmonics are
buried in the noise floor it is the largest peak.
V
- should be returned to a clean analog ground and V +
AA AA
should be RC decoupled from the digital supply as shown in
Figure 13.
Sinewave Signal Power
SFDR = 10 Log
There is approximately 50Ω of substrate impedance
between V
and V +. This can be used, for example, as
Highest Spurious Signal Power
DD
AA
part of a low pass RC filter to attenuate switching supply
6-1810
HI5813
TABLE 2. CODE TABLE
INPUT
BINARY OUTPUT CODE
VOLTAGE†
V
+ = 3.3V
- = 0.0V
(V)
MSB
LSB
D0
1
REF
CODE
DESCRIPTION
V
DECIMAL
COUNT
REF
D11
1
D10
1
D9
1
D8
1
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
Full Scale (FS)
3.2992
4095
4094
3072
2048
1024
1
FS - 1 LSB
3
3.2984
2.4750
1.6500
0.8250
1
1
1
1
1
1
1
1
1
1
1
0
/
/
/
FS
FS
FS
1
1
0
0
0
0
0
0
0
0
0
0
4
2
4
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1 LSB
Zero
0.00080566
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
†The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage.
+3.3V
0.1µF
4.7µF
10µF
0.1µF
0.01µF
V
+
V
DD
AA
D11
OUTPUT
DATA
.
.
.
D0
V
+
REF
DRDY
OEM
OEL
ANALOG
INPUT
V
V
IN
STRT
CLK
500kHz CLOCK
-
V
-
V
SS
REF
AA
FIGURE 13. GROUND AND SUPPLY DECOUPLING
6-1811
HI5813
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3200µm x 3940µm
Type: PSG
Thickness: 13kÅ ±2.5kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
Type: AlSi
Thickness: 11kÅ ±1kÅ
5
2
1.84 x 10 A/cm
Metallization Mask Layout
HI5813
D0
(LSB)
D1
DRDY
V
OEL
DD
CLK
D2
D3
STRT
V
-
REF
D4
D5
D6
V
+
REF
D7
D8
V
IN
V
+
-
AA
V
AA
D9
V
D10
D11
OEM
SS
(MSB)
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
6-1812
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