HIP4086AABZ-T13 [RENESAS]
HALF BRDG BASED MOSFET DRIVER;
| 型号： | HIP4086AABZ-T13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | HALF BRDG BASED MOSFET DRIVER 驱动 |
| 文件： | 总16页 (文件大小：470K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
80V, 500mA, 3-Phase MOSFET Driver
HIP4086, HIP4086A
Features
The HIP4086 and HIP4086A (referred to as the HIP4086/A) are
three phase N-Channel MOSFET drivers. Both parts are
specifically targeted for PWM motor control. These drivers have
flexible input protocol for driving every possible switch
combination. The user can even override the shoot-through
protection for switched reluctance applications.
• Independently drives 6 N-Channel MOSFETs in three phase
bridge configuration
• Bootstrap supply max voltage up to 95VDC with bias supply
from 7V to 15V
• 1.25A peak turn-off current
• User programmable dead time (0.5µs to 4.5µs)
The HIP4086/A have a wide range of programmable dead times
(0.5µs to 4.5µs) which makes them very suitable for the low
frequencies (up to 100kHz) typically used for motor drives.
• Bootstrap and optional charge pump maintain the high-side
driver bias voltage.
• Programmable bootstrap refresh time
The only difference between the HIP4086 and the HIP4086A is
that the HIP4086A has the built-in charge pumps disabled. This
is useful in applications that require very quiet EMI performance
(the charge pumps operate at 10MHz). The advantage of the
HIP4086 is that the built-in charge pumps allow indefinitely long
on times for the high-side drivers.
• Drives 1000pF load with typical rise time of 20ns and Fall
Time of 10ns
• Programmable undervoltage set point
Applications
• Brushless Motors (BLDC)
• 3-phase AC motors
To insure that the high-side driver boot capacitors are fully
charged prior to turning on, a programmable bootstrap refresh
pulse is activated when VDD is first applied. When active, the
refresh pulse turns on all three of the low-side bridge FETs while
holding off the three high-side bridge FETs to charge the
high-side boot capacitors. After the refresh pulse clears, normal
operation begins.
• Switched reluctance motor drives
• Battery powered vehicles
• Battery powered tools
Another useful feature of the HIP4086/A is the programmable
undervoltage set point. The set point range varies from 6.6V to
8.5V.
Related Literature
• AN9642 “HIP4086 3-Phase Bridge Driver Configurations and
Applications”
200
VDD
V
- V
= 10V
xHS
xHB
VDD
CHB
BHB
AHB
RDEL
150
100
50
AHO
BHO
CHO
CHS
BHS
AHS
Battery
24V...48V
Speed
Brake
AHI
ALI
BHI
BLI
CHI
CLI
Controller
VSS
ALO
BLO
CLO
0
-60 -40 -20
0
20 40 60 80 100 120 140 160
JUNCTION TEMPERATURE (°C)
FIGURE 2. CHARGE PUMP OUTPUT CURRENT
FIGURE 1. TYPICAL APPLICATION
February 1, 2013
FN4220.9
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2011, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
HIP4086, HIP4086A
Block Diagram (for clarity, only one phase is shown)
Charge
Pump*
If undervoltage is active or if
DIS is asserted, the high and
low-side drivers are turned off.
Drive Enable
Common with
all phases
VDD
16 xHB
EN
Adjustable
Turn-on
Delay
xHI 5
Level
Shifter
17 xHO
18 xHS
DIS 10
10ns
delay
*The charge pump is
permanently disabled
in the HIP4086A.
VDD 20
Undervoltage
Detector
UVLO 8
Delay Disable
Common with
all phases
VDD
Refresh
Pulse
RFSH 9
Common with
all phases
Adjustable
Turn-on
Delay
21 xLO
6 VSS
xLI 4
Common with
all phases
RDEL 7
2µs Delay
If the voltage on RDEL is less than 100mV, the
turn-on delay timers are disabled and the high and
low-side drivers can be turned on simultaneously.
100mV
Truth Table
INPUT
OUTPUT
ALI, BLI, CLI
AHI, BHI, CHI
UV
X
DIS
1
RDEL
ALO, BLO, CLO
AHO, BHO, CHO
X
X
1
0
0
1
X
X
X
0
1
0
X
0
0
1
0
0
1
0
0
0
1
0
1
1
X
X
0
0
>100mV
0
0
X
X
0
0
0
0
<100mV
NOTE: X signifies that input can be either a “1” or “0”.
FN4220.9
February 1, 2013
2
HIP4086, HIP4086A
Pin Configuration
HIP4086, HIP4086A
(PDIP, SOIC)
TOP VIEW
1
2
24
23
22
21
20
19
18
17
16
15
14
13
BHB
BHI
BHO
BHS
BLO
ALO
VDD
CLO
AHS
AHC
AHB
CHS
CHO
CHB
3
BLI
4
ALI
5
AHI
6
VSS
RDEL
UVLO
RFSH
DIS
7
8
9
10
11
12
CLI
CHI
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
16
1
13
AHB
BHB
CHB
(xHB)
High-Side Bias Connections. One external bootstrap diode and one capacitor are required for
each. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to each xHB
pin.
15
23
15
AHS
BHS
CHS
High-Side Source Connections. Connect the sources of the High-Side power MOSFETs to these
pins. The negative side of the bootstrap capacitors are also connected to these pins.
(xHS)
5
2
12
AHI
BHI
CHI
High-Side Logic Level Inputs. Logic at these three pins controls the three high side output
drivers, AHO (Pin 17), BHO (Pin 24) and CHO (Pin 14). When xHI is low, xHO is high. When xHI
is high, xHO is low. Unless the dead time is disabled by connecting RDEL (Pin 7) to ground, the
low side input of each phase will override the corresponding high side input on that phase -
see “Truth Table” on page 2. If RDEL is tied to ground, dead time is disabled and the outputs
follow the inputs with no shoot-thru protection. DIS (Pin 10) also overrides the high side inputs.
(xHI)
xHI can be driven by signal levels of 0V to 15V (no greater than V ).
DD
4
3
11
ALI
BLI
CLI
Low-Side Logic Level Inputs. Logic at these three pins controls the three low-side output
drivers ALO (Pin 21), BLO (Pin 22) and CLO (Pin 19). If the upper inputs are grounded then the
lower inputs control both xLO and xHO drivers, with the dead time set by the resistor at RDEL
(Pin 7). DIS (Pin 10) high level input overrides xLI, forcing all outputs low. xLI can be driven by
(xLI)
signal levels of 0V to 15V (no greater than V ).
DD
6
7
V
Ground. Connect the sources of the Low-Side power MOSFETs to this pin.
SS
RDEL
Delay Time Set point. Connect a resistor from this pin to V to set timing current that defines
DD
the dead time between drivers - see Figure 17. All drivers turn-off with minimal delay, RDEL
resistor prevents shoot-through by delaying the turn-on of all drivers. When RDEL is tied to V
,
SS
both upper and lowers can be commanded on simultaneously. While not necessary in most
applications, a decoupling capacitor of 0.1µF or smaller may be connected between RDEL and
V
.
SS
8
9
UVLO
RFSH
DIS
Undervoltage Set point. A resistor can be connected between this pin and V to program the
SS
undervoltage set point - see Figure 18. With this pin not connected, the under voltage disable
is typically 6.6V. When this pin is tied to V , the under voltage disable is typically 6.2V.
DD
Refresh Pulse Setting. An external capacitor can be connected from this pin to V to increase
SS
the length of the start up refresh pulse - see Figure 16. If this pin is not connected, the refresh
pulse is typically 1.5µs.
10
Disable Input. Logic level input that when taken high sets all six outputs low. DIS high
overrides all other inputs. With DIS low, the outputs are controlled by the other inputs. DIS can
be driven by signal levels of 0V to 15V (no greater than V ).
DD
FN4220.9
February 1, 2013
3
HIP4086, HIP4086A
Pin Descriptions(Continued)
PIN NUMBER
SYMBOL
DESCRIPTION
High-Side Outputs. Connect to the gates of the High-Side power MOSFETs in each phase.
17
24
14
AHO
BHO
CHO
(xHO)
20
V
Positive Supply. Decouple this pin to V (Pin 6).
SS
DD
21
22
19
ALO
BLO
CLO
Low-Side Outputs. Connect the gates of the Low-Side power MOSFETs to these pins.
(xLO)
NOTE: x = A, B or C.
Ordering Information
PART NUMBER
PART
TEMP RANGE
(°C)
CHARGE
PUMP
PKG.
DWG. #
(Notes 1, 3)
MARKING
PACKAGE
HIP4086AB
HIP4086AB
-40 to +125
-40 to +125
-40 to +125
-40 to +125
Yes
Yes
Yes
No
24 Ld SOIC
M24.3
HIP4086ABZ (Note 2)
HIP4086APZ (Note 2)
HIP4086AABZ (Note 2)
NOTES:
HIP4086ABZ
HIP4086APZ
HIP4086AABZ
24 Ld SOIC (Pb-free)
24 Ld PDIP (Pb-free)
24 Ld SOIC (Pb-free)
M24.3
E24.3
M24.3
1. Add “-T*”, suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for HIP4086, HIP4086A. For more information on MSL, please see Technical
Brief TB363.
FN4220.9
February 1, 2013
4
HIP4086, HIP4086A
Absolute Maximum Ratings (Note 7)
Thermal Information
Supply Voltage, V Relative to GND. . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Logic Inputs (xLI, xHI) . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3v to V + 0.3V
DD
Voltage on xHS . . . . . . . . . . . . . . -6V (Transient) to 85V (-40°C to +150°C)
Voltage on xHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VxHS - 0.3V to VxHS +VDD
Voltage on xLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 0.3V to VDD +0.3V
Voltage on xHO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VxHS - 0.3V to VxHB +0.3V
Phase slew rate (on xHS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
Thermal Resistance (Typical)
θ
(°C/W)
75
51
θ
(°C/W)
22
22
DD
JA
JC
SOIC Package (Notes 4, 6) . . . . . . . . . . . . .
SOIC Package HIP4086AABZ (Notes 5, 6)
PDIP* Package (Notes 4, 6) . . . . . . . . . . . .
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temp Range . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
70
29
*Pb-free PDIPs can be used for through-hole wave solder processing only.
They are not intended for use in Reflow solder processing applications.
Maximum Recommended Operating
Conditions
Supply Voltage, V Relative to GND. . . . . . . . . . . . . . . . . . . . . . . 7V to 15V
DD
Logic Inputs (xLI, xHI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
Voltage on xHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VxHS + VDD
Voltage on xHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 80V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
5. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
6. For θ , the “case temp” location is taken at the package top center.
JC
7. Replace x with A, B, or C.
DC Electrical Specifications
V
= V
= 12V, V = V
SS
= 0V, R
= 20k, R = ∞, Gate Capacitance (C
UV
) = 1000pF,
GATE
DD
xHB
xHS
DEL
unless otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +150°C.
T = +25°C T = -40°C TO +150°C
J
J
MIN
MAX
MIN
MAX
PARAMETER
SUPPLY CURRENTS
TEST CONDITIONS
(Note 9) TYP (Note 9)
(Note 9)
(Note 9)
UNITS
xHI = 5V, xLI = 5V (HIP4086)
xHI = 5V, xLI = 5V (HIP4086A)
f = 20kHz, 50% Duty Cycle (HIP4086)
f = 20kHz, 50% Duty Cycle (HIP4086A)
xHI = 0V (HIP4086)
2.7
2.3
6.3
3.1
-
3.4
2.4
8.25
3.6
40
4.2
2.6
10.5
4.1
80
2.1
2.1
5
4.3
2.7
11
mA
mA
mA
mA
µA
V
V
Quiescent Current
Operating Current
DD
DD
2.8
-
4.4
100
200
1.4
1.2
2.0
1.2
50
xHB On Quiescent Current
xHB Off Quiescent Current
xHI = 0V (HIP4086A)
80
100
1.3
1
µA
xHI = V (HIP4086)
DD
0.6
0.8
0.7
0.8
7
0.8
0.9
0.9
0.9
24
0.5
mA
mA
mA
mA
µA
xHI = V (HIP4086A)
DD
0.7
f = 20kHz, 50% Duty Cycle (HIP4086)
f = 20kHz, 50% Duty Cycle (HIP4086A)
1.3
1
-
-
-
xHB Operating Current
xHB, xHS Leakage Current
V
= 80V, V
= 93V
= 22V
45
xHS
xHB
xHB
Charge Pump, HIP4086 only, (Note 8)
Q
Q
Output Voltage
Output Current
No Load
= 12V, V
11.5
50
12.5
100
14
10.5
-
14.5
140
V
PUMP
PUMP
V
130
µA
xHS
UNDERVOLTAGE PROTECTION
V
V
Rising Undervoltage Threshold
Falling Undervoltage Threshold
R
R
R
UV open
6.2
5.75
5
7.1
6.6
6.2
8.0
7.5
6.8
6.1
5.6
4.9
8.1
7.6
6.9
V
V
V
DD
DD
UV open
Minimum Undervoltage Threshold
= V
DD
UV
INPUT PINS: ALI, BLI, CLI, AHI, BHI, CHI, AND DIS
Low Level Input Voltage
-
-
1.0
-
0.8
V
FN4220.9
February 1, 2013
5
HIP4086, HIP4086A
DC Electrical Specifications
V
= V
= 12V, V = V
SS
= 0V, R
= 20k, R = ∞, Gate Capacitance (C
UV
) = 1000pF,
GATE
DD
xHB
xHS
DEL
unless otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +150°C. (Continued)
T = +25°C T = -40°C TO +150°C
J
J
MIN
MAX
MIN
MAX
PARAMETER
High Level Input Voltage
Input Voltage Hysteresis
Low Level Input Current
High Level Input Current
TEST CONDITIONS
(Note 9) TYP (Note 9)
(Note 9)
(Note 9)
UNITS
V
2.5
-
-
35
-100
-
-
-
2.7
-
-
-
mV
µA
V
V
= 0V
= 5V
-60
-1
-135
+1
-55
-10
-140
+10
IN
IN
µA
GATE DRIVER OUTPUT PINS: ALO, BLO, CLO, AHO, BHO, AND CHO
Low Level Output Voltage (V
Peak Turn-On Current
NOTES:
- V
)
I
= 30mA
= 0V
-
100
0.5
-
-
-
200
1.0
mV
A
OUT SS SINKING
V
0.3
0.7
OUT
8. the specified charge pump current is the total amount available to drive external loads across xHO and xHS.
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
AC Electrical Specifications
V
= V
= 12V, V = V
SS
= 0V, C
= 1000pF, R
= 10k, unless otherwise specified.
DEL
DD
xHB
xHS
GATE
Boldface limits apply over the operating junction temperature range, -40°C to +150°C.
T = +25°C
T = -40°C TO +150°C
J
J
MIN
MAX
MIN
MAX
PARAMETER
TEST CONDITIONS
(Note 9) TYP (Note 9)
(Note 9)
(Note 9)
UNITS
TURN-ON DELAY AND PROPAGATION DELAY
R
R
R
= 100kΩ
= 10kΩ
= 10kΩ
3.8
0.38
-
4.5
0.5
7
6
3
0.3
-
7
µs
µs
%
DEL
DEL
DEL
Dead Time (Figure 3)
0.65
15
0.7
20
Dead Time Channel Matching
Lower Turn-Off Propagation Delay
(xLI to xLO turn-off) (Figure 3 or 4)
No Load
No Load
No Load
No Load
-
-
-
-
30
75
45
65
45
90
75
90
-
-
-
-
65
100
90
ns
ns
ns
ns
Upper Turn-Off Propagation Delay
(xHI to xHO turn-off) (Figure 3 or 4)
Lower Turn-On Propagation Delay
(xLI to xLO turn-on) (Figure 3 or 4)
Upper Turn-On Propagation Delay
(xHI to xHO turn-on) (Figure 3 or 4)
100
Rise Time
Fall Time
C
C
= 1000pF
= 1000pF
-
-
20
10
40
20
-
-
50
25
ns
ns
GATE
GATE
Disable Turn-Off Propagation Delay
(DIS to xLO turn-off) (Figure 5)
-
-
-
-
55
80
55
2.0
80
90
80
-
-
-
-
-
90
100
100
-
ns
ns
ns
µs
Disable Turn-Off Propagation Delay
(DIS to xHO turn-off) (Figure 5)
Disable to Lower Turn-On Propagation Delay
(DIS to xLO turn-on) (Figure 5)
Disable to Upper Enable
(DIS to xHO turn-on) (Figure 5)
R
Open
= 10kΩ, C
DEL
RFSH
FN4220.9
February 1, 2013
6
HIP4086, HIP4086A
Test Waveforms and Timing Diagrams
xLI to xLO
turn-off
xLI to xLO
turn-on
xLI to xLO
turn-off
xLI to xHO
turn-off
+ delay
xLI
xHI
xLO
xHO
xHI to xHO
turn-on
+ delay
Dead
time
Dead
time
xHI to xHO
turn-off
FIGURE 3. PROP DELAYS WITH PROGRAMMED TURN-ON DELAYS (RDEL CONNECTED TO VDD WITH A RESISTOR)
xLI to xLO
turn-off
xLI to xLO
turn-on
xLI to xLO
turn-off
xLI to xLO
turn-on
xLI
xHI
xLO
xHO
xLO and xHO are on
simulateously
xHI to xHO
turn-on
xHI to xHO
turn-off
xHI to xHO
turn-on
FIGURE 4. PROP DELAYS WITH NO PROGRAMMED TURN-ON DELAYS (RDEL CONNECTED TO VSS)
DIS to xLO
turn-on
delay
DIS to xLO
turn-on
delay
DIS to xHO
turn-off
delay
DIS
or
refresh pulse
refresh pulse
UV
xHI,
xLI
xLO
xHO
xHO turn-on delay
FIGURE 5. DISABLE FUNCTION
FN4220.9
February 1, 2013
7
HIP4086, HIP4086A
Typical Performance Curves
6
5
4
3
2
30
25
20
15
10
ALL GATE CONTROL INPUTS = 5V
C
= 1000pF
GATE
V
= 16V
DD
200kHz
V
V
= 15V
= 12V
DD
100kHz
50kHz
DD
V
= 10V
= 8V
= 7V
DD
20kHz
10kHz
V
V
DD
DD
-60 -40 -20
0
20
40
60
80 100 120 140 160
-60 -40 -20
0
20
40
60
80 100 120 140 160
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 6. V SUPPLY CURRENT vs V SUPPLY VOLTAGE
FIGURE 7. V SUPPLY CURRENT vs SWITCHING FREQUENCY
DD
DD
DD
4000
3000
2000
1000
0
1.8
V
= 15V
DD
T
= +25°C
J
1.6
1.4
1.2
1.0
0.8
0.6
C
= 1000pF
GATE
V
= 10V
DD
V
V
= 8V
= 7V
DD
DD
V
= 12V
DD
C
= NO LOAD
GATE
-60 -40 -20
0
20
40
60
80 100 120 140 160
0
20
40
60
80
100 120 140 160 180 200
JUNCTION TEMPERATURE (°C)
SWITCHING FREQUENCY (kHz)
FIGURE 9. OFF-STATE I
BIAS CURRENT
FIGURE 8. FLOATING I
BIAS CURRENT
XHB
XHB
14
13
12
11
10
9
200
150
100
50
V
= 15V
DD
V
- V
= 10V
xHS
xHB
V
= 12V
DD
V
= 10V
DD
V
= 8V
DD
8
V
= 7V
DD
7
0
6
-60 -40 -20
0
20
40
60
80 100 120 140 160
-60 -40 -20
0
20
40 60 80 100 120 140 160
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 10. CHARGE PUMP OUTPUT CURRENT (HIP4086 only)
FIGURE 11. CHARGE PUMP OUTPUT VOLTAGE(HIP4086 only)(
FN4220.9
February 1, 2013
8
HIP4086, HIP4086A
Typical Performance Curves(Continued)
1
0.8
0.6
0.4
0.2
0
2
1.6
1.2
0.8
C
= 1000pF
C
= 1000pF
GATE
GATE
V
= 15V
DD
V
= 15V
DD
V
= 12V
DD
V
= 12V
V
= 10V
DD
DD
V
V
= 10V
DD
V
= 8V
= 7V
DD
= 8V
DD
V
DD
V
= 7V
DD
0.4
0
-60 -40 -20
0
20
40
60
80 100 120 140 160
-60 -40 -20
0
20
40
60
80 100 120 140 160
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 12. AVERAGE TURN-ON CURRENT (0 TO 5V)
FIGURE 13. AVERAGE TURN-OFF CURRENT (V TO 4V)
DD
100
40
30
20
10
0
V
= XHB-XHS = 12V, C
= 1000pF
GATE
DD
80
60
40
20
xHI to xHO
RISE
FALL
xLI to xLO
-60 -40 -20
0
20
40
60
80 100 120 140 160
-60 -40 -20
0
20
40
60
80 100 120 140 160
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 14. RISE AND FALL TIMES (10 to 90%)
FIGURE 15. PROPAGATION DELAY
80
60
40
20
0
100
T
= +25°C
J
UPPER DISABLE TURN-OFF
LOWER DISABLE TURN-OFF
LOWER ENABLE TURN-ON
10
-60 -40 -20
0
50
100 150 200 250 300 350 400 450 500
(pF)
0
20
40
60
80 100 120 140 160
C
JUNCTION TEMPERATURE (°C)
RFSH
FIGURE 17. REFRESH TIME
FIGURE 16. DISABLE PIN PROPAGATION DELAY
FN4220.9
February 1, 2013
9
HIP4086, HIP4086A
Typical Performance Curves(Continued)
6
4
2
11.0
10.5
10.0
9.5
RDEL = 100kΩ
ENABLE (50kΩ, UVLO TO GND)
9.0
8.5
TRIP (50k, UVLO TO GND)
8.0
TRIP/ENABLE (0kΩ, UVLO TO V
)
DD
ENABLE (UVLO OPEN)
TRIP (UVLO OPEN)
7.5
7.0
RDEL = 10kΩ
6.5
6.0
0
-60 -40 -20
0
20
40
60
80 100 120 140 160
-60 -40 -20
0
20
40
60
80 100 120 140 160
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 18. DEAD TIME
FIGURE 19. UNDERVOLTAGE THRESHOLD
25
V
= 80V
xHS
20
15
10
-60 -40 -20
0
20
40
60
80 100 120 140 160
JUNCTION TEMPERATURE (°C)
FIGURE 20. I
LEAKAGE CURRENT
xHS
enabled if the voltage on the RDEL pin is greater than 100mV.
The voltage on RDEL will be greater than 100mV for any value of
programming resistor in the specified range. If the voltage on
RDEL is less than 100mV, the delay timers are disabled and no
shoot-thru protection is provided by the internal logic of the
HIP4086/A. When the dead time is to be disabled, RDEL should
be shorted to VSS.
Functional Description
Input Logic
NOTE: When appropriate for brevity, input and output pins will be
prefixed with an “x” as a substitute for A, B, or C. For example,
xHS refers to pins AHS, BHS, and CHS.
The HIP4086/A is a three phase bridge driver designed
specifically for motor drive applications. Three identical half
bridge sections, A, B, and C, can be controlled individually by
their input pins, ALI, AHI, BLI, BHI, and CLI, CHI (xLI, xHI) or the 2
corresponding input pins for each section can be tied together to
form a PWM input (xLI connected to xHI = xPWM). When
controlling individual inputs, the programmable dead time is
optional but shoot-thru protection must then be incorporated in
the timing of the input signals. If the PWM mode is chosen, then
the internal programmable dead time must be used.
Refresh Pulse
To insure that the boot capacitors are charged prior to turning on
the high-side drivers, a refresh pulse is triggered when DIS is low
or when the UV comparator transitions low (VDD is greater than
the programmed undervoltage threshold). Please refer to the
“Block Diagram (for clarity, only one phase is shown)” on page 2.
When triggered, the refresh pulse turns on all of the low-side
drivers (xLO = 1) and turns off all of the high-side drivers
(xHO = 0) for a duration set by a resistor tied between RDEL and
VSS. When xLO = 1, the low-side bridge FETs charge the boot
caps from VDD through the boot diodes.
Shoot-Thru Protection
Dead time, to prevent shoot-thru, is implemented by delaying the
turn-on of the high-side and low-side drivers. The delay timers are
FN4220.9
February 1, 2013
10
HIP4086, HIP4086A
Equation 1 calculates the total charge required for the Period
Charge Pump
duration. This equation assumes that all of the parameters are
constant during the Period duration. The error is insignificant if
Ripple is small.
The internal charge pump of the HIP4086/A is used to maintain
the bias on the boot cap for 100% duty cycle. There is no limit for
the duration of this period. The user must understand that this
charge pump is only intended to provide the static bias current of
the high-side drivers and the gate leakage current of the
high-side bridge FETs. It cannot provide in a reasonable time, the
majority of the charge on the boot cap that is consumed, when
the xHO drivers source the gate charge to turn on the high-side
bridge FETs. The boot caps should be sized so that they do not
discharge excessively when sourcing the gate charge. See
“Application Information” on page 11 for methods to size the
boot caps.
Q
C
C
= Q
+ Period × (I + V ⁄ R + I
)
C
gate80V
HB
HO
GS
gate_leak
∗
= Q ⁄ (Ripple VDD)
boot
boot
C
(EQ. 1)
= 0.52μF
If the gate to source resistor is removed (R is usually not
GS
needed or recommended), then:
C
= 0.33µF
boot
These values of C
will sustain the high side driver bias during
boot
The charge pump has sufficient capacity to source a worst-case
minimum of 50µA to the external load. The gate leakage current
of most power MOSFETs is about 100nA so there is more than
sufficient current to maintain the charge on the boot caps.
Because the charge pump current is small, a gate-source resistor
on the high-side bridge FETs is not recommended. When
calculating the leakage load on the outputs of xHS, also include
the leakage current of the boot capacitor. This is rarely a problem
but it could be an issue with electrolytic capacitors at high
temperatures.
Period with only a small amount of Ripple. But in the case of the
HIP4086, the charge pump reduces the value of C even
boot
more. The specified charge pump current is a minimum of 50µA
which is more than sufficient to source I . Also, because
gate_leak
the specified charge pump current is in excess of what is needed
for I , the total charge required to be sourced by the boot
HB
capacitor is just
(EQ. 2)
Q
= Q
or C
= 0.13μF
C
gate80V
boot
Not only is the required boot cap smaller in value, there is no
restriction on the duration of Period.
Application Information
Selecting the Boot Capacitor Value
The boot capacitor value is chosen not only to supply the internal
bias current of the high-side driver but also, and more
significantly, to provide the gate charge of the driven FET without
causing the boot voltage to sag excessively. In practice, the boot
capacitor should have a total charge that is about 20 times the
gate charge of the driven power FET for approximately a 5% drop
in voltage after charge has been transferred from the boot
capacitor to the gate capacitance.
The following parameters shown in Table 1 are required to
calculate the value of the boot capacitor for a specific amount of
voltage droop when using the HIP4086/A (no charge pump). In
Table 1, the values used are arbitrary. They should be changed to
comply with the actual application.
TABLE 1.
FIGURE 21. TYPICAL GATE VOLTAGE vs GATE CHARGE
V
V
= 10V
V
can be any value between 7 and 15VDC
DD
HB
DD
= V - 0.6V
DD
High side driver bias voltage (V - boot diode
DD
= V
voltage) referenced to V
HS
HO
Period = 1ms
= 100µA
This is the longest expected switching period
I
Worst case high side driver current when
HB
xHO = high (this value is specified for V = 12V
DD
but the error is not significant)
R
= 100kΩ
Gate-source resistor (usually not needed)
GS
Ripple = 5%
Desired ripple voltage on the boot cap (larger
ripple is not recommended)
I
= 100nA
From the FET vendor’s datasheet
From Figure 21.
gate_leak
Qgate80V = 64nC
FN4220.9
February 1, 2013
11
HIP4086, HIP4086A
Typical Application Circuit
VDD
VDD
CHB
BHB
AHB
RDEL
AHO
BHO
CHO
CHS
BHS
AHS
Battery
24V...48V
Speed
Brake
AHI
ALI
BHI
BLI
CHI
CLI
Controller
VSS
ALO
BLO
CLO
FIGURE 22. TYPICAL APPLICATION CIRCUIT
Figure 22 is an example of how the HIP4086 and HIP4086A
3-phase drivers can be applied to drive a 3-phase motor.
When the high-side bridge FET turns off, because of the inductive
characteristics of a motor load, the current that was flowing in
the high-side FET (blue) must rapidly commutate to flow through
the low-side FET (red). The amplitude of the negative transient
impressed on the xHS node is (di/dt x L) where L is the total
parasitic inductance of the low-side FET drain-source path and
di/ddt is the rate at which the high-side FET is turned off. With
the increasing power levels of new generation motor drives,
clamping this transient becomes more and more significant for
the proper operation of the HIP4086/A.
Depending on the application, the switching speed of the bridge
FETs can be reduced by adding series connected resistors
between the xHO outputs and the FET gates. Gate-Source
resistors are recommended on the low-side FETs to prevent
unexpected turn-on of the bridge should the bridge voltage be
applied before V . Gate-source resistors on the high-side FETs
DD
are not usually required if low-side gate-source resistors are
used. If relatively small gate-source resistors are used on the
high-side FETs, be aware that they will load the charge pump of
the HIP4086 negating the ability of the charge pump to keep the
high-side driver biased during very long periods.
There are several ways of reducing the amplitude of this
transient. If the bridge FETs are turned off more slowly to reduce
di/dt, the amplitude will be reduced but at the expense of more
switching losses in the FETs. Careful PCB design will also reduce
the value of the parasitic inductance. However, these two
solutions by themselves may not be sufficient. Figure 23
illustrates a simple method for clamping the negative transient.
Two series connected, fast PN junction, 1A diodes are connected
between xHS and VSS as shown. It is important that the
components be placed as close as possible to the xHS and VSS
pins to minimize the parasitic inductance of this current path.
Two series connected diodes are required because they are in
parallel with the body diode of the low-side FET. If only one diode
is used for the clamp, it will conduct some of the negative load
current that is flowing in the low-side FET. In severe cases, a
small value resistor in series with the xHS pin as shown, will
further reduce the amplitude of the negative transient.
An important operating condition that is frequently overlooked by
designers is the negative transient on the xHS pins that occurs
when the high-side bridge FET turns off. The Absolute Maximum
transient allowed on the xHS pin is -6V but it is wise to minimize
the amplitude to lower levels. This transient is the result of the
parasitic inductance of the low-side drain-source conductor on
the PCB. Even the parasitic inductance of the low-side FET
contributes to this transient.
x H O
IN D U C T IV E
L O A D
x H S
-
+
Please note that a similar transient with a positive polarity occurs
when the low-side FET turns off. This is less frequently a problem
because xHS node is floating up toward the bridge bias voltage.
The Absolute Max voltage rating for the xHS node does need to
be observed when the positive transient occurs.
x L O
-
+
V S S
FIGURE 23. BRIDGE WITH PARASITIC INDUCTANCES
FN4220.9
February 1, 2013
12
HIP4086, HIP4086A
General PCB Layout Guidelines
The AC performance of the HIP4086/A depends significantly on
the design of the PC board. The following layout design
• It may be necessary to add resistance to dampen resonating
parasitic circuits especially on xHO and xLO. If an external gate
resistor is unacceptable, then the layout must be improved to
minimize lead inductance.
guidelines are recommended to achieve optimum performance:
• Place the driver as close as possible to the driven power FETs.
• Keep high dv/dt nodes away from low level circuits. Guard
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for control circuits
that source the input signals to the HIP4086/A.
• Understand where the switching power currents flow. The high
amplitude di/dt currents of the driven power FET will induce
significant voltage transients on the associated traces.
• Keep power loops as short as possible by paralleling the
source and return traces.
• Avoid having a signal ground plane under a high amplitude
dv/dt circuit. This will inject di/dt currents into the signal
ground paths.
• Use planes where practical; they are usually more effective
than parallel traces.
• Do power dissipation and voltage drop calculations of the
power traces. Many PCB/CAD programs have built in tools for
calculation of trace resistance.
• Avoid paralleling high amplitude di/dt traces with low level
signal lines. High di/dt will induce currents and consequently,
noise voltages in the low level signal lines.
• Large power components (Power FETs, Electrolytic caps, power
resistors, etc.) will have internal parasitic inductance which
cannot be eliminated. This must be accounted for in the PCB
layout and circuit design.
• When practical, minimize impedances in low level signal
circuits. The noise, magnetically induced on a 10kΩ resistor, is
10x larger than the noise on a 1kΩ resistor.
• Be aware of magnetic fields emanating from motors,
transformers and inductors. Gaps in these magnetic structures
are especially bad for emitting flux.
• If you simulate your circuits, consider including parasitic
components especially parasitic lead inductance.
• If you must have traces close to magnetic devices, align the
traces so that they are parallel to the flux lines to minimize
coupling.
• The use of low inductance components such as chip resistors
and chip capacitors is highly recommended.
• Use decoupling capacitors to reduce the influence of parasitic
inductance in the VDD and GND leads. To be effective, these
caps must also have the shortest possible conduction paths. If
vias are used, connect several paralleled vias to reduce the
inductance of the vias.
FN4220.9
February 1, 2013
13
HIP4086, HIP4086A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
FN4220.9
CHANGE
January 28, 2013
Corrected following typo in the second paragraph of page 1:
From: (0.5ms to 4.5ms)
To: (0.5µs to 4.5µs)
September 27, 2012
June 1, 2011
FN4220.8
FN4220.7
Removed evaluation board from “Ordering Information” and “Related Literature” since it is inactive.
Added alternate parameters for HIP4086A in DC Electrical Specifications Table Supply Currents on page 5.
Added to Charge Pump Figures 10 and 11 in Typical Performance Curves "HIP4086 Only"
March 18, 2011
-Converted to new Intersil datasheet template.
-Changed Title from "80V, 500mA, 3-Phase Driver" to "80V, 500mA, 3-Phase MOSFET Driver".
-Rewrote description on page 1 by adding HIP4086A and stating the differences between parts.
-Updated “Ordering Information” on page 4 by adding part number HIP4086AABZ and Eval Board. Added MSL
note. Removed obsolete part HIP4086AP.
-Updated “TYPICAL APPLICATION” on page 1.
-Added “CHARGE PUMP OUTPUT CURRENT” on page 1.
-Updated “Features” and “Applications” section on page 1.
-Added “Related Literature” on page 1.
-Updated “Block Diagram” on page 2 by adding color and notes.
-Updated “Thermal Information” and notes on page 5.
-Added “Boldface limits apply..” to common conditions of Electrical Specifications tables. Added Note 9 to MIN
and MAX columns of Electrical Specifications tables.
-Updated all timing diagrams for better clarification on page 7.
-Added “Functional Description”, “Application Information” and “General PCB Layout Guidelines” sections
beginning on page 10.
-Updated Package Outline Drawing M24.3 by removing table listing dimensions and putting dimensions on
drawing. Added Land Pattern.
-Added “Revision History” and “About Intersil” to page 14.
July 26, 2004
FN4220.6
FN4220.5
Added Pb-Free parts to “Ordering Information” on page 4.
February 18, 2003
Revised “Pin Descriptions” on page 3.
Revised “Low Level Input Current” specs on page 6.
May, 1999
FN4220.4
Initial Release.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,
personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of
our winning team, visit our website and career page at www.intersil.com.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.
Also, please check the product information page to ensure that you have the most updated datasheet: HIP4086, HIP4086A
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4220.9
February 1, 2013
14
HIP4086, HIP4086A
Dual-In-Line Plastic Packages (PDIP)
E24.3 (JEDEC MS-001-AF ISSUE D)
24 LEAD NARROW BODY DUAL-IN-LINE PLASTIC
PACKAGE
N
E1
INDEX
AREA
1 2
3
N/2
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-A-
A
A1
A2
B
-
4
D
E
0.015
0.115
0.014
0.045
0.008
1.230
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
31.24
0.13
7.62
6.10
4
BASE
PLANE
A2
A
C
0.195
0.022
0.070
0.014
1.280
-
4.95
0.558
1.77
0.355
32.51
-
-
-C-
SEATING
PLANE
-
L
C
L
B1
C
8
D1
B1
e
A1
A
A
D1
-
e
e
C
B
B
D
5
e
0.010 (0.25) M
C
B S
D1
E
5
0.325
0.280
8.25
7.11
6
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
E1
e
5
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
e
e
6
A
B
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
-
0.430
0.150
-
10.92
3.81
7
4. Dimensions A, A1 and L are measured with the package seated in
L
0.115
2.93
4
9
JEDEC seating plane gauge GS-3.
N
24
24
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
Rev. 0 12/93
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
FN4220.9
February 1, 2013
15
HIP4086, HIP4086A
Package Outline Drawing
M24.3
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)
Rev 2, 3/11
24
INDEX
AREA
7.60 (0.299)
7.40 (0.291)
10.65 (0.419)
10.00 (0.394)
DETAIL "A"
1
2
3
TOP VIEW
1.27 (0.050)
0.40 (0.016)
SEATING PLANE
2.65 (0.104)
2.35 (0.093)
15.60 (0.614)
15.20 (0.598)
0.75 (0.029)
x 45°
0.25 (0.010)
0.30 (0.012)
0.10 (0.004)
1.27 (0.050)
8°
0°
0.51 (0.020)
0.33 (0.013)
0.32 (0.012)
0.23 (0.009)
SIDE VIEW “A”
SIDE VIEW “B”
1.981 (0.078)
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Package length does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
3. Package width does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm
(0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
9.373 (0.369)
7. Controlling dimension: MILLIMETER. Converted inch dimensions in
(
) are not necessarily exact.
8. This outline conforms to JEDEC publication MS-013-AD ISSUE C.
1.27 (0.050)
0.533 (0.021)
TYPICAL RECOMMENDED LAND PATTERN
FN4220.9
February 1, 2013
16
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