HIP6004DCR-T [RENESAS]
SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PQCC20, 5 X 5 MM, PLASTIC, MO-220VHHC, QFN-20;
| 型号： | HIP6004DCR-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PQCC20, 5 X 5 MM, PLASTIC, MO-220VHHC, QFN-20 开关 |
| 文件： | 总14页 (文件大小：826K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NS
at
SIG
DE
DATASHEET
W
LA
rt
po
ters
NE
EP
R
FO
D R
l S
ED
DE
ND
EN
ME
MM
CO
OM
EC
RE
T R
NO
NO
co
T
EN
M
CE
er
nt
Ce
il.c
up
ica
hn
ec
r T
ou
NT
8-I
ct
nta
c
/ts
om
.in
ww
r w
L o
SI
ER
88
1-
HIP6004D
FN4855
Rev 3.00
July 13, 2005
Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor
The HIP6004D provides complete control and protection for
a DC-DC converter optimized for high-performance
Features
• Drives Two N-Channel MOSFETs
• Operates from +5V or +12V Input
microprocessor applications. It is designed to drive two
N-Channel MOSFETs in a synchronous-rectified buck
topology. The HIP6004D integrates all of the control, output
adjustment, monitoring and protection functions into a single
package.
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
The output voltage of the converter is easily adjusted and
precisely regulated. The HIP6004D includes a fully TTL-
compatible 5-input digital-to-analog converter (DAC) that
adjusts the output voltage from 1.1V
to 1.85V in 25mV
• Excellent Output Voltage Regulation
DC
DC
increments steps. The precision reference and voltage-
mode regulator hold the selected output voltage to within
1% over temperature and line voltage variations.
- 1% Over Line Voltage and Temperature
• TTL-Compatible 5-Bit Digital-to-Analog Output
Voltage Selection
The HIP6004D provides simple, single feedback loop,
voltage-mode control with fast transient response. It includes
a 200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/s slew rate which enables high converter bandwidth for
fast transient performance. The resulting PWM duty ratio
ranges from 0% to 100%.
- 25mV Binary Steps . . . . . . . . . 1.100V
to 1.850V
DC
DC
• Power-Good Output Voltage Monitor
• Over-Voltage and Over-Current Fault Monitors
- Does Not Require Extra Current Sensing Element,
Uses MOSFET’s r
DS(ON)
• Small Converter Size
- Constant Frequency Operation
The HIP6004D monitors the output voltage with a window
comparator that tracks the DAC output and issues a Power
Good signal when the output is within 10%. The HIP6004D
protects against over-current and overvoltage conditions by
inhibiting PWM operation. Additional built-in overvoltage
protection triggers an external SCR to crowbar the input
supply. The HIP6004D monitors the current by using the
- 200kHz Free-Running Oscillator Programmable from
50kHz to over 1MHz
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
r
of the upper MOSFET which eliminates the need for
DS(ON)
• Pb-Free plus anneal available (RoHS compliant)
a current sensing resistor.
Applications
Ordering Information
• Power Supply for K7™, and Other Microprocessors
TEMP.
PKG.
DWG. #
o
PART NUMBER RANGE ( C)
PACKAGE
20 Ld SOIC
•
•
High-Power DC-DC Regulators
HIP6004DCB
0 to 70
0 to 70
M20.3
M20.3
Low-Voltage Distributed Power Supplies
HIP6004DCBZ
(See Note)
20 Ld SOIC
(Pb-free)
HIP6004DCR
0 to 70
0 to 70
20 Ld 5x5 QFN
L20.5x5
L20.5x5
HIP6004DCRZ
(See Note)
20 Ld 5x5 QFN
(Pb-free)
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
FN4855 Rev 3.00
July 13, 2005
Page 1 of 14
HIP6004D
Pinouts
HIP6004D (SOIC, TSSOP)
HIP6004D (QFN)
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
9
RT
V
20
19
SEN
OCSET
SS
OVP
20 19 18 17 16
18 V
CC
VID0
VID1
VID2
VID3
VID4
COMP
17 LGATE
16 PGND
15 BOOT
14 UGATE
13 PHASE
VID0
VID1
VID2
VID3
VID4
VCC
1
2
3
4
5
15
14
13
12
11
LGATE
PGND
BOOT
UGATE
GND
21
12
PGOOD
FB 10
11 GND
6
7
8
9
10
Typical Application
+12V
VCC
V
= +5V OR +12V
IN
HIP6004D
PGOOD
OCSET
EN
MONITOR AND
PROTECTION
SS
OVP
BOOT
RT
OSC
UGATE
PHASE
VID0
VID1
VID2
VID3
VID4
+V
OUT
D/A
LGATE
PGND
-
+
+
-
FB
COMP
VSEN
GND
FN4855 Rev 3.00
July 13, 2005
Page 2 of 14
HIP6004D
Block Diagram
V
CC
V
SEN
POWER-ON
110%
RESET (POR)
+
-
PGOOD
90%
+
-
OVER-
VOLTAGE
1µA
115%
+
OVP
SS
-
SOFT-
START
+
-
OCSET
OVER-
CURRENT
BOOT
REFERENCE
200µA
4V
UGATE
PHASE
VID0
VID1
VID2
VID3
VID4
PWM
TTL D/A
CONVERTER
(DAC)
COMPARATOR
DACOUT
GATE
CONTROL
LOGIC
INHIBIT
PWM
+
-
+
-
ERROR
AMP
LGATE
PGND
GND
FB
COMP
RT
OSCILLATOR
FN4855 Rev 3.00
July 13, 2005
Page 3 of 14
HIP6004D
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V
Thermal Resistance
JA ( C/W) JC ( C/W)
CC
Boot Voltage, V
- V
. . . . . . . . . . . . . . . . . . . . . . . .+15V
BOOT
PHASE
SOIC Package (Note 1) . . . . . . . . . . . .
QFN Package (Notes 2, 3). . . . . . . . . .
65
33
NA
5
Input, Output or I/O Voltage. . . . . . . . . . . .GND -0.3V to V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
+0.3V
CC
o
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
o
o
Operating Conditions
(SOIC - Lead Tips Only)
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . +12V 10%
CC
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
3. For , the “case temp” location is the center of the exposed metal pad on the package underside. See Tech Brief TB379
JC
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
UGATE and LGATE Open
-
5
-
mA
CC
POWER-ON RESET
Rising V
Threshold
Threshold
V
V
= 4.5V
-
8.2
-
-
-
10.4
V
V
V
CC
OCSET
OCSET
Falling V
= 4.5V
-
-
CC
Rising V
Threshold
1.26
OCSET
OSCILLATOR
Free Running Frequency
Total Variation
RT = OPEN
185
-15
-
200
-
215
+15
-
kHz
%
6k < RT to GND < 200k
RT = Open
Ramp Amplitude
V
OSC
1.9
V
P-P
REFERENCE AND DAC
DAC (VID0-VID4) Input Low Voltage
DAC (VID0-VID4) Input High Voltage
DACOUT Voltage Accuracy
ERROR AMPLIFIER
DC Gain
-
-
-
-
0.8
-
V
V
2.0
-1.0
+1.0
%
-
-
-
88
15
6
-
-
-
dB
Gain-Bandwidth Product
Slew Rate
GBWP
SR
MHz
V/s
COMP = 10pF
GATE DRIVERS
Upper Gate Source
I
V
- V
= 12V, V = 6V
UGATE
350
500
5.5
450
3.5
-
10
-
mA
UGATE
BOOT
PHASE
Upper Gate Sink
R
I
= 0.3A
-
300
-
UGATE
LGATE
Lower Gate Source
I
V
= 12V, V
= 6V
mA
LGATE
CC
LGATE
Lower Gate Sink
R
I
= 0.3A
6.5
LGATE
LGATE
PROTECTION
Over-Voltage Trip (VSEN/DACOUT)
OCSET Current Source
OVP Sourcing Current
Soft Start Current
-
170
60
-
115
200
-
120
%
µA
mA
µA
I
V
V
= 4.5V
230
OCSET
OCSET
DC
I
= 5.5V, V
= 0V
-
-
OVP
SEN
OVP
I
10
SS
FN4855 Rev 3.00
July 13, 2005
Page 4 of 14
HIP6004D
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)
PARAMETER
POWER GOOD
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Upper Threshold (VSEN/DACOUT)
Lower Threshold (VSEN/DACOUT)
Hysteresis (VSEN/DACOUT)
PGOOD Voltage Low
VSEN Rising
VSEN Falling
106
-
-
111
%
%
%
V
89
-
94
-
Upper and Lower Threshold
2
V
I
= -5mA
-
0.5
-
PGOOD
PGOOD
Typical Performance Curves
80
70
60
50
40
C
= 3300pF
GATE
1000
R
PULLUP
TO +12V
T
C
= C
= C
LOWER GATE
UPPER
100
10
C
= 1000pF
GATE
30
20
10
0
R
PULLDOWN TO V
SS
T
C
= 10pF
800
GATE
10
100
SWITCHING FREQUENCY (kHz)
1000
100 200
300
400
500
600
700
900 1000
SWITCHING FREQUENCY (kHz)
FIGURE 1. R RESISTANCE vs FREQUENCY
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
T
the converter over-current (OC) trip point according to the
following equation:
Functional Pin Descriptions
1
2
3
4
5
6
7
8
9
RT
VSEN
OCSET
SS
20
19
I
x R
OCSET
OCSET
----------------------------------------------------
I
=
OVP
PEAK
r
DSON
18 VCC
An over-current trip cycles the soft-start function.
VID0
17 LGATE
16 PGND
VID1
SS (Pin 3)
VID2
BOOT
15
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10µA current source, sets the soft-
start interval of the converter.
VID3
14 UGATE
13 PHASE
VID4
12
COMP
PGOOD
VID0-4 (Pins 4-8)
FB 10
11 GND
VID0-4 are the input pins to the 5-bit DAC. The states of
these five pins program the internal voltage reference
(DACOUT). The level of DACOUT sets the converter output
voltage. It also sets the PGOOD and OVP thresholds. Table
1 specifies DACOUT for the all combinations of DAC inputs.
V
(Pin 1)
SEN
This pin is connected to the converter’s output voltage. The
PGOOD and OVP comparator circuits use this signal to
report output voltage status and for overvoltage protection.
COMP (Pin 9) and FB (Pin 10)
OCSET (Pin 2)
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
Connect a resistor (R
upper MOSFET. R
OCSET
) from this pin to the drain of the
, an internal 200µA current source
OCSET
(I
), and the upper MOSFET on-resistance (r
) set
DS(ON)
OCS
FN4855 Rev 3.00
July 13, 2005
Page 5 of 14
HIP6004D
GND (Pin 11)
Functional Description
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
Initialization
The HIP6004D automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary. The
Power-On Reset (POR) function continually monitors the input
supply voltages. The POR monitors the bias voltage at the VCC
pin and the input voltage (V ) on the OCSET pin. The level on
OCSET is equal to V less a fixed voltage drop (see over-
IN
PGOOD (Pin 12)
PGOOD is an open collector output used to indicate the
status of the converter output voltage. This pin is pulled low
when the converter output is not within 10%of the
DACOUT reference voltage. Exception to this behavior is the
‘11111’ VID pin combination which disables the converter; in
this case PGOOD asserts a high level.
IN
current protection). The POR function initiates soft start
operation after both input supply voltages exceed their POR
thresholds. For operation with a single +12V power source, V
IN
PHASE (Pin 13)
and V
are equivalent and the +12V power source must
CC
Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET
for over-current protection. This pin also provides the return
path for the upper gate drive.
exceed the rising VCC threshold before POR initiates
operation.
Soft Start
The POR function initiates the soft start sequence. An internal
UGATE (Pin 14)
10µA current source charges an external capacitor (C ) on
SS
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET.
the SS pin to 4V. Soft start clamps the error amplifier output
(COMP pin) and reference input (+ terminal of error amp) to the
SS pin voltage. Figure 3 shows the soft start interval with
BOOT (Pin 15)
C
= 0.1F. Initially the clamp on the error amplifier (COMP
SS
This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
pin) controls the converter’s output voltage. At t in Figure 3,
1
the SS voltage reaches the valley of the oscillator’s triangle
wave. The oscillator’s triangular waveform is compared to the
ramping error amplifier voltage. This generates PHASE pulses
of increasing width that charge the output capacitor(s). This
PGND (Pin 16)
This is the power ground connection. Tie the lower MOSFET
source to this pin.
interval of increasing pulse width continues to t . With sufficient
2
output voltage, the clamp on the reference input controls the
LGATE (Pin 17)
output voltage. This is the interval between t and t in Figure 3.
2
3
At t the SS voltage exceeds the DACOUT voltage and the
Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET.
3
output voltage is in regulation. This method provides a rapid
and controlled output voltage rise. The PGOOD signal toggles
‘high’ when the output voltage (VSEN pin) is within 10% of
DACOUT. The 2% hysteresis built into the power good
comparators prevents PGOOD oscillation due to nominal
output voltage ripple.
V
(Pin 18)
CC
Provide a 12V bias supply for the chip to this pin.
OVP (Pin 19)
The OVP pin can be used to drive an external SCR in the
event of an overvoltage condition. Output rising 15% more
than the DAC-set voltage triggers a high output on this pin
and disables PWM gate drive circuitry.
PGOOD
(2V/DIV)
RT (Pin 20)
0V
This pin provides oscillator switching frequency adjustment.
By placing a resistor (R ) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
SOFT-START
(1V/DIV)
T
OUTPUT
VOLTAGE
(1V/DIV)
6
5 x 10
--------------------
Fs 200kHz +
(R to GND)
T
0V
R k
T
0V
Conversely, connecting a pull-up resistor (R ) from this pin
T
t
t
t
3
1
2
to V
reduces the switching frequency according to the
CC
TIME (5ms/DIV)
following equation:
FIGURE 3. SOFT START INTERVAL
7
4 x 10
--------------------
Fs 200kHz –
(R to 12V)
T
R k
T
FN4855 Rev 3.00
July 13, 2005
Page 6 of 14
HIP6004D
2. The minimum I
3. Determine I
from the specification table.
Over-Current Protection
OCSET
for I
I
+ I 2 ,
The over-current function protects the converter from a
shorted output by using the upper MOSFET’s on-resistance,
PEAK
where I is the outputPinEdAuKctoOr rUipTpMleAcXu rrent.
r
to monitor the current. This method enhances the
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
DS(ON)
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
A small ceramic capacitor should be placed in parallel with
R
to smooth the voltage across R in the
OCSET
OCSET
presence of switching noise on the input voltage.
4V
2V
0V
Output Voltage Program
The output voltage of a HIP6004D converter is programmed
to discrete levels between 1.100V
and 1.850V . The
DC
DC
voltage identification (VID) pins program an internal voltage
reference (DACOUT) with a TTL-compatible 5-bit digital-to-
analog converter (DAC). The level of DACOUT also sets the
PGOOD and OVP thresholds. Table 1 specifies the DACOUT
voltage for the 32 different combinations of connections on the
VID pins. The output voltage should not be adjusted while the
converter is delivering power. Remove input power before
changing the output voltage. Adjusting the output voltage
during operation could toggle the PGOOD signal and exercise
the overvoltage protection.
15A
10A
5A
0A
TIME (20ms/DIV)
FIGURE 4. OVER-CURRENT OPERATION
‘11111’ VID pin combination resulting in a 0V output setting
activates the Power-On Reset function and disables the gate
drives circuitry. For this specific VID combination, though,
PGOOD asserts a high level. This unusual behavior has been
implemented in order to allow for operation in dual-
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R
)
OCSET
programs the over-current trip level. An internal 200A current
sink develops a voltage across R that is referenced to
OCSET
. When the voltage across the upper MOSFET (also
V
IN
microprocessor systems where AND-ing of the PGOOD signals
from two individual power converters is implemented.
referenced to V ) exceeds the voltage across R
, the
IN OCSET
over-current function initiates a soft-start sequence. The soft-
start function discharges C with a 10A current sink and
inhibits PWM operation. The soft-start function recharges
SS
Application Guidelines
C
, and PWM operation resumes with the error amplifier
SS
clamped to the SS voltage. Should an overload occur while
recharging C , the soft start function inhibits PWM operation
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
SS
while fully charging C to 4V to complete its cycle. Figure 4
shows this operation with an overload condition. Note that the
inductor current increases to over 15A during the C
charging interval and causes an over-current trip. The
converter dissipates very little power with this method. The
measured input power for the conditions of Figure 4 is 2.5W.
SS
SS
The over-current function will trip at a peak inductor current
(I
determined by:
PEAK)
I
x R
OCSET
OCSET
----------------------------------------------------
I
=
PEAK
r
DSON
where I
is the internal OCSET current source (200A
OCSET
typical). The OC trip point varies mainly due to the
MOSFET’s r variations. To avoid over-current
DS(ON)
tripping in the normal operating load range, find the R
OCSET
resistor from the equation above with:
1. The maximum r
temperature.
at the highest junction
DS(ON)
FN4855 Rev 3.00
July 13, 2005
Page 7 of 14
HIP6004D
TABLE 1. OUTPUT VOLTAGE PROGRAM
PIN NAME
PIN NAME
NOMINAL OUTPUT
VOLTAGE DACOUT
NOMINAL OUTPUT
VOLTAGE DACOUT
VID4
1
VID3
VID2
1
VID1
1
VID0
1
VID4
0
VID3
1
VID2
1
VID1
1
VID0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
1
1
1
0
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
0
1
1
1
0
1
1
0
1
0
1
1
0
1
1
1
0
0
0
1
1
0
0
1
0
1
1
0
1
0
1
1
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
0
1
1
0
0
0
0
1
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
1
1
0
1
1
0
1
0
0
1
0
1
1
1
0
0
0
0
1
0
0
1
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
NOTE: 0 = connected to GND or V , 1 = connected to V
SS
through pull-up resistors.
DD
current paths on the SS pin and locate the capacitor, C
SS
close to the SS pin because the internal current source is
only 10A. Provide local V decoupling between V and
V
IN
HIP6004D
CC
GND pins. Locate the capacitor, C
CC
as close as
BOOT
practical to the BOOT and PHASE pins.
UGATE
Q
Q
1
L
O
V
OUT
PHASE
+V
IN
BOOT
D
1
C
Q
1
IN
2
L
O
C
C
LGATE
PGND
BOOT
O
D
2
V
OUT
PHASE
VCC
HIP6004D
C
O
+12V
SS
Q
2
RETURN
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
C
VCC
C
SS
GND
Figure 5 shows the critical power components of the converter.
To minimize the voltage overshoot the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 5 should be located as close together as possible.
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Please note that the capacitors C and C each represent
IN
O
Figure 7 highlights the voltage-mode control loop for a
numerous physical capacitors. Locate the HIP6004D within 3
synchronous-rectified buck converter. The output voltage
(V ) is regulated to the Reference voltage level. The
inches of the MOSFETs, Q and Q . The circuit traces for the
1
2
OUT
MOSFETs’ gate and source connections from the HIP6004D
must be sized to handle up to 1A peak current.
error amplifier (Error Amp) output (V ) is compared with
E/A
the oscillator (OSC) triangular wave to provide a pulse-
width modulated (PWM) wave with an amplitude of V at
the PHASE node.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
IN
FN4855 Rev 3.00
July 13, 2005
Page 8 of 14
HIP6004D
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
V
IN
DRIVER
DRIVER
OSC
PWM
L
O
COMPARATOR
V
OUT
Compensation Break Frequency Equations
-
PHASE
+
1
1
V
C
O
OSC
------------------------------------
--------------------------------------------------------
F
=
F
=
Z1
P1
2 x R x C
C
x C
2
1
1
2
---------------------
2 x R
x
ESR
(PARASITIC)
2
C
+ C
2
1
Z
FB
1
1
------------------------------------------------------
2 x R + R x C
------------------------------------
2 x R x C
F
=
F
=
V
E/A
Z2
P2
1
3
3
3
3
Z
-
IN
+
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
REFERENCE
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
Z
FB
V
OUT
C
2
Z
IN
C
C
R
Check the compensation gain at F with the capabilities of
R
3
1
3
2
P2
the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 8 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
R
1
COMP
FB
-
+
compensation transfer function and plotting the gain.
HIP6004D
The compensation gain uses external impedance networks
DACOUT
Z
and Z to provide a stable, high bandwidth (BW)
FB
IN
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
The PWM wave is smoothed by the output filter (L and C ).
O
O
The modulator transfer function is the small-signal transfer
function of V /V . This function is dominated by a DC
OUT E/A
Gain and the output filter (L and C ), with a double pole
100
F
F
P1
F
F
Z2
Z1
P2
O
O
80
60
40
20
0
break frequency at F and a zero at F
the modulator is simply the input voltage (V ) divided by the
peak-to-peak oscillator voltage V
OSC
. The DC Gain of
LC ESR
OPEN LOOP
ERROR AMP GAIN
IN
.
20LOG
(R /R )
Modulator Break Frequency Equations
2
1
20LOG
1
1
(V /V
)
IN OSC
------------------------------------------
-------------------------------------------
F
=
F
=
LC
ESR
2 x ESR x C
2 x
L
x C
MODULATOR
GAIN
O
O
O
COMPENSATION
GAIN
-20
-40
-60
The compensation network consists of the error amplifier
(internal to the HIP6004D) and the impedance networks Z
CLOSED LOOP
GAIN
IN
F
LC
F
ESR
100K
FREQUENCY (Hz)
and Z . The goal of the compensation network is to provide
FB
10
100
1K
10K
1M
10M
a closed loop transfer function with the highest 0dB crossing
frequency (f
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f and
0dB
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
0dB
180degrees The equations below relate the compensation
network’s poles, zeros and gain to the components (R , R ,
1
2
Component Selection Guidelines
R , C , C , and C ) in Figure 7. Use these guidelines for
3
1
2
3
Output Capacitor Selection
locating the poles and zeros of the compensation network:
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
1. Pick Gain (R /R ) for desired converter bandwidth.
2
1
ST
2. Place 1 Zero Below Filter’s Double Pole (~75% FLC).
ND
3. Place 2
Zero at Filter’s Double Pole.
ST
4. Place 1 Pole at the ESR Zero.
ND
5. Place 2
Pole at Half the Switching Frequency.
FN4855 Rev 3.00
July 13, 2005
Page 9 of 14
HIP6004D
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (Effective Series Resistance) and voltage rating
requirements rather than actual capacitance requirements.
equations give the approximate response time interval for
application and removal of a transient load:
L x I
L x I
TRAN
OUT
TRAN
V
OUT
t
=
t
=
FALL
RISE
V
- V
IN
where: I
is the transient load current step, t
is the
is the
TRAN
RISE
response time to the application of load, and t
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
FALL
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
DACOUT setting. Be sure to check both of these equations
at the minimum and maximum output levels for the worst
case response time. With a +12V input, and output voltage
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
level equal to DACOUT, t
is the longest response time.
FALL
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q turns on. Place the
small ceramic capacitors physically close to the MOSFETs
1
and between the drain of Q and the source of Q .
1
2
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
V
- V
V
OUT
IN
OUT
DV
= DI x ESR
DI =
x
OUT
Fs x L
V
IN
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
MOSFET Selection/Considerations
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6004D will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The HIP6004D requires 2 N-Channel power MOSFETs. These
should be selected based upon r
, gate supply
DS(ON)
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor (see the equations
below). Only the upper MOSFET has switching losses, since
the Schottky rectifier clamps the switching node before the
synchronous rectifier turns on. These equations assume linear
The response time to a transient is different for the
application of load and the removal of load. The following
FN4855 Rev 3.00
July 13, 2005
Page 10 of 14
HIP6004D
voltage-current transitions and do not adequately model power
loss due the reverse-recovery of the lower MOSFET’s body
diode. The gate-charge losses are dissipated by the HIP6004D
and don't heat the MOSFETs. However, large gate-charge
Figure 10 shows the upper gate drive supplied by a direct
connection to V . This option should only be used in
CC
converter systems where the main input voltage is +5V
or
DC
less. The peak upper gate-to-source voltage is approximately
increases the switching interval, t
which increases the upper
V
less the input supply. For +5V main power and +12V
SW
CC
DC
for the bias, the gate-to-source voltage of Q is 7V. A logic-
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
1
level MOSFET is a good choice for Q and a logic-level
MOSFET can be used for Q if its absolute gate-to-source
voltage rating exceeds the maximum voltage applied to V
1
2
.
CC
+12V
1
2
2
Io x V x t
IN SW
x F
S
P
= Io x r
x D +
+5V OR LESS
UPPER
LOWER
DS(ON)
DS(ON)
2
V
CC
P
= Io x r
x (1 - D)
BOOT
Where: D is the duty cycle = V
/ V ,
IN
OUT
HIP6004D
t
is the switch ON time, and
SW
Q
Q
1
UGATE
PHASE
F
is the switching frequency.
S
NOTE:
G-S V -5V
V
Standard-gate MOSFETs are normally recommended for
use with the HIP6004D. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET’s absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
CC
D
2
LGATE
PGND
2
-
+
NOTE:
V
G-S V
CC
GND
Figure 9 shows the upper gate drive (BOOT pin) supplied by a
FIGURE 10. UPPER GATE DRIVE - DIRECT V
DRIVE OPTION
CC
bootstrap circuit from V . The boot capacitor, C
CC BOOT
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
Schottky Selection
CC
Rectifier D is a clamp that catches the negative inductor
2
less the boot diode drop (V ) when the lower MOSFET, Q
D
2
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency will drop
one or two percent as a result. The diode’s rated reverse
breakdown voltage must be greater than the maximum
input voltage.
turns on. Logic-level MOSFETs can only be used if the
MOSFET’s absolute gate-to-source voltage rating exceeds
the maximum voltage applied to VCC.
+12V
D
BOOT
+5V OR +12V
+ V
-
D
V
CC
BOOT
C
HIP6004D
BOOT
Q1
UGATE
PHASE
NOTE:
G-S V -V
V
CC
D
Q2
D2
LGATE
PGND
-
+
NOTE:
G-S V
V
CC
GND
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
FN4855 Rev 3.00
July 13, 2005
Page 11 of 14
HIP6004D
HIP6004D DC-DC Converter Application Circuit
Figure 11 shows an application circuit of a DC-DC Converter
for a microprocessor. Detailed information on the circuit,
including a complete Bill-of-Materials and circuit board
description, can be found in Application Note AN9672.
Although the Application Note details the HIP6004, the same
evaluation platform can be used to evaluate the HIP6004D.
+5V
V
=
OR
IN
L
- 1H
1
+12V
F
2 x 1F
2N6394
C
1
IN
5x 1000F
+12V
2K
D
1
0.1F
1000pF
1K
V
OVP
19
CC
18
2
12
15
OCSET
PGOOD
BOOT
MONITOR
AND
PROTECTION
SS
3
1
0.1F
V
SEN
0.1F
RT 20
OSC
14 UGATE
13 PHASE
Q
Q
L
3H
1
2
4
VID0
VID1
VID2
VID3
VID4
5
6
7
8
+V
OUT
HIP6004D
D/A
D
2
C
17 LGATE
16 PGND
-
2
OUT
+
+
-
9x 1000F
FB 10
11
GND
9
COMP
2.2nF
20K
8.2nF
0.1F
15
1.33K
Component Selection Notes:
C
C
- Each 1000µF 6.3W VDC, Sanyo MV-GX or Equivalent.
OUT
- Each 330µF 25W VDC, Sanyo MV-GX or Equivalent.
IN
L
L
D
D
- Core: Micrometals T50-52B; Winding: 10 Turns of 16AWG.
- Core: Micrometals T50-52; Winding: 5 Turns of 18AWG.
- 1N4148 or Equivalent.
2
1
1
2
- 3A, 40V Schottky, Motorola MBR340 or Equivalent.
Q , Q - Intersil MOSFET; RFP70N03.
1
2
FIGURE 11. MICROPROCESSOR DC-DC CONVERTER
FN4855 Rev 3.00
July 13, 2005
Page 12 of 14
HIP6004D
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC MS-013-AC ISSUE C)
N
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
M
M
B
0.25(0.010)
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.35
0.23
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.014
0.1043
0.0118
0.019
-
0.30
-
1
2
3
L
0.49
9
SEATING PLANE
A
0.0091
0.4961
0.2914
0.0125
0.32
-
-A-
0.5118 12.60
13.00
7.60
3
D
h x 45°
0.2992
7.40
4
-C-
0.050 BSC
1.27 BSC
-
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
M
M
S
B
0.25(0.010)
C
A
N
20
20
7
0°
8°
0°
8°
-
NOTES:
Rev. 2 6/05
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
© Copyright Intersil Americas LLC 2003-2005. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4855 Rev 3.00
July 13, 2005
Page 13 of 14
HIP6004D
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L20.5x5
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
0.90
-
-
-
0.02
-
0.65
9
0.20 REF
9
0.23
2.95
2.95
0.30
0.38
3.25
3.25
5, 8
D
5.00 BSC
-
D1
D2
E
4.75 BSC
9
3.10
7, 8
5.00 BSC
-
E1
E2
e
4.75 BSC
9
3.10
7, 8
0.65 BSC
-
k
0.20
0.35
-
0.60
20
5
-
-
L
0.75
8
N
2
Nd
Ne
P
3
5
3
-
-
-
0.60
12
9
-
9
Rev. 4 11/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220VHHC Issue I except for the "b"
dimension.
FN4855 Rev 3.00
July 13, 2005
Page 14 of 14
相关型号：
HIP6004DCRZ
SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PQCC20, 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHC, QFN-20
RENESAS
HIP6004DCRZ-T
SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PQCC20, 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHC, QFN-20
RENESAS
HIP6004ECB
SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PDSO20, PLASTIC, MS-013AC, SOIC-20
RENESAS
HIP6004ECBZ
Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor; SOIC20, TSSOP20; Temp Range: 0° to 70°
RENESAS
HIP6004ECBZ
Switching Controller, Voltage-mode, 1000kHz Switching Freq-Max, PDSO20, LEAD FREE, PLASTIC, MS-013AC, SOIC-20
ROCHESTER
HIP6004ECBZ-T
Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor; SOIC20, TSSOP20; Temp Range: 0° to 70°
RENESAS
©2020 ICPDF网 联系我们和版权申明