HIP6601ABE
更新时间：2024-09-18 14:55:29
品牌：RENESAS
描述：0.73A HALF BRDG BASED MOSFET DRIVER, PDSO8, PLASTIC, EPSOIC-8
概述
规格参数
数据手册HIP6601ABE 概述
0.73A HALF BRDG BASED MOSFET DRIVER, PDSO8, PLASTIC, EPSOIC-8 MOSFET 驱动器
HIP6601ABE 规格参数
| 生命周期： | Obsolete | 零件包装代码： | SOIC |
| 包装说明： | LSOP, | 针数： | 8 |
| Reach Compliance Code： | unknown | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.66 |
| 高边驱动器： | YES | 接口集成电路类型： | HALF BRIDGE BASED MOSFET DRIVER |
| JESD-30 代码： | R-PDSO-G8 | 长度： | 4.89 mm |
| 功能数量： | 1 | 端子数量： | 8 |
| 最高工作温度： | 85 °C | 最低工作温度： | |
| 标称输出峰值电流： | 0.73 A | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | LSOP | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE, LOW PROFILE | 认证状态： | Not Qualified |
| 座面最大高度： | 1.68 mm | 最大供电电压： | 13.2 V |
| 最小供电电压： | 10.8 V | 标称供电电压： | 12 V |
| 电源电压1-最大： | 12 V | 电源电压1-分钟： | 5 V |
| 表面贴装： | YES | 温度等级： | OTHER |
| 端子形式： | GULL WING | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 宽度： | 3.35 mm |
| Base Number Matches： | 1 |
HIP6601ABE 数据手册
通过下载HIP6601ABE数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载HIP6601A, HIP6603A
TM
Data Sheet
September 2000
File Number 4884.1
Synchronous-Rectified Buck MOSFET
Drivers
Features
• Drives Two N-Channel MOSFETs
• Adaptive Shoot-Through Protection
• Internal Bootstrap Device
The HIP6601A and HIP6603A are high frequency, dual
MOSFET drivers specifically designed to drive two power
N-Channel MOSFETs in a synchronous-rectified buck
converter topology. These drivers combined with a HIP630x
Multi-Phase Buck PWM controller and Intersil UltraFETs®
form a complete core-voltage regulator solution for
advanced microprocessors.
• Supports High Switching Frequency
- Fast Output Rise Time
- Propagation Delay 30ns
• Small 8 Lead SOIC and EPSOIC Package
• Dual Gate-Drive Voltages for Optimal Efficiency
• Three-State Input for Output Stage Shutdown
• Supply Under Voltage Protection
The HIP6601A drives the lower gate in a synchronous-
rectifier to 12V, while the upper gate can be independently
driven over a range from 5V to 12V. The HIP6603A drives
both upper and lower gates over a range of 5V to 12V. This
drive-voltage flexibility provides the advantage of optimizing
applications involving trade-offs between switching losses
and conduction losses.
Applications
• Core Voltage Supplies for Intel Pentium® III, AMD®
Athlon™ Microprocessors
The output drivers in the HIP6601A and HIP6603A have the
capacity to efficiently switch power MOSFETs at frequencies
up to 2MHz. Each driver is capable of driving a 3000pF load
with a 30ns propagation delay and 50ns transition time. Both
products implement bootstrapping on the upper gate with
only an external capacitor required. This reduces
• High Frequency Low Profile DC-DC Converters
• High Current Low Voltage DC-DC Converters
Related Literature
implementation complexity and allows the use of higher
performance, cost effective, N-Channel MOSFETs. Adaptive
shoot-through protection is integrated to prevent both
MOSFETs from conducting simultaneously.
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Pinout
Ordering Information
HIP6601ACB, HIP6603ACB (SOIC)
HIP6601ABE, HIP6603ABE (EPSOIC)
TOP VIEW
TEMP. RANGE
o
PART NUMBER
HIP6601ACB
( C)
PACKAGE
8 Ld SOIC
8 Ld SOIC
PKG. NO.
M8.15
0 to 85
0 to 85
UGATE
BOOT
PWM
1
2
3
4
8
7
6
5
PHASE
PVCC
VCC
HIP6603ACB
M8.15
HIP6601ACB-T
HIP6603ACB-T
HIP6601ABE
8 Ld SOIC Tape and Reel
8 Ld SOIC Tape and Reel
0 to 85
0 to 85
8 Ld EPSOIC M8.15B
8 Ld EPSOIC M8.15B
GND
LGATE
HIP6603ABE
HIP6601ABE-T
HIP6603ABE-T
8 Ld EPSOIC Tape and Reel
8 Ld EPSOIC Tape and Reel
Block Diagram
PVCC
BOOT
VCC
UGATE
PHASE
+5V
† VCC FOR HIP6601A
PVCC FOR HIP6603A
SHOOT-
10K
THROUGH
PROTECTION
PWM
CONTROL
LOGIC
†
LGATE
GND
10K
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
Pentium® is a registered trademark of Intel Corporation. | AMD® is a registered trademark of Advanced Micro Devices, Inc.
Athlon™ is a trademark of Advanced Micro Devices, Inc. | UltraFET® is a registered trademark of Intersil Corporation.
HIP6601A, HIP6603A
Typical Application - 3 Channel Converter Using HIP6301 and HIP6601A Gate Drivers
+12V
+5V
BOOT
PVCC
UGATE
PHASE
VCC
DRIVE
HIP6601A
PWM
LGATE
+12V
+5V
+5V
+V
CORE
BOOT
VFB
COMP
PWM1
PVCC
UGATE
PHASE
VCC
VCC
VSEN
PWM
DRIVE
HIP6601A
PWM2
PWM3
PGOOD
LGATE
MAIN
CONTROL
HIP6301
VID
ISEN1
ISEN2
ISEN3
+12V
FS
GND
+5V
BOOT
PVCC
UGATE
PHASE
VCC
DRIVE
HIP6601A
PWM
LGATE
2
HIP6601A, HIP6603A
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
Thermal Resistance (Note 1)
θ
( C/W)
JA
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPSOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . .
97
38
BOOT Voltage (V
- V
). . . . . . . . . . . . . . . . . . . . . . . .15V
BOOT
PHASE
o
Input Voltage (V
) . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V
PWM
Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
o
UGATE. . . . . . . . . . . . . . . . . . . . . . V
LGATE . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V
- 0.3V to V
+ 0.3V
+ 0.3V
PHASE
BOOT
PVCC
o
ESD Rating
(SOIC - Lead Tips Only)
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV
Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .200V
Operating Conditions
o
o
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0 C to 85 C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125 C
o
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10%
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . . . . . . 5V to 12V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
VCC SUPPLY CURRENT
Bias Supply Current
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
HIP6601A, f
HIP6603A, f
HIP6601A, f
HIP6603A, f
= 1MHz, V
= 1MHz, V
= 1MHz, V
= 1MHz, V
= 12V
= 12V
= 12V
= 12V
-
-
-
-
4.4
2.5
200
1.8
6.2
3.6
430
3.3
mA
mA
µA
VCC
PWM
PWM
PWM
PWM
PVCC
PVCC
PVCC
PVCC
Upper Gate Bias Current
I
PVCC
mA
POWER-ON RESET
VCC Rising Threshold
VCC Falling Threshold
PWM INPUT
9.7
9.0
9.95
9.2
10.4
9.5
V
V
Input Current
I
V
= 0 or 5V (See Block Diagram)
-
500
3.6
1.45
20
-
µA
V
PWM
PWM
PWM Rising Threshold
PWM Falling Threshold
UGATE Rise Time
3.45
-
-
1.55
V
t
t
V
V
V
V
V
V
= 12V, 3nF Load
= 12V, 3nF Load
= 12V, 3nF Load
= 12V, 3nF Load
= 12V, 3nF Load
= 12V, 3nF Load
-
-
ns
ns
ns
ns
ns
ns
V
RUGATE
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
LGATE Rise Time
t
-
50
-
RLGATE
FUGATE
UGATE Fall Time
-
20
-
LGATE Fall Time
t
-
20
-
FLGATE
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
Shutdown Window
t
-
-
30
-
-
PDLUGATE
t
20
PDLLGATE
1.4
-
-
3.6
-
Shutdown Holdoff Time
OUTPUT
230
ns
Upper Drive Source Impedance
R
R
V
V
V
V
V
V
V
V
= 5V
-
1.7
3.0
2.3
1.1
580
730
730
1.6
3.0
5.0
4.0
2.0
-
Ω
Ω
UGATE
UGATE
LGATE
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
= 12V
-
-
Upper Drive Sink Impedance
Lower Drive Source Current
= 5V
Ω
= 12V
-
Ω
I
= 5V, HIP6603A
= 12V, HIP6603A
= 5V or 12V, HIP6601A
= 5V or 12V
400
500
500
-
mA
mA
mA
Ω
-
-
Lower Drive Sink Impedance
R
4.0
LGATE
3
HIP6601A, HIP6603A
For the HIP6603A, this pin supplies both the upper and
lower gate drive bias. Connect this pin to either +12V or +5V.
Functional Pin Description
UGATE (Pin 1)
PHASE (Pin 8)
Upper gate drive output. Connect to gate of high-side power
N-Channel MOSFET.
Connect this pin to the source of the upper MOSFET and the
drain of the lower MOSFET. The PHASE voltage is
monitored for adaptive shoot-through protection. This pin
also provides a return path for the upper gate drive.
BOOT (Pin 2)
Floating bootstrap supply pin for the upper gate drive.
Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFET. See the Internal Bootstrap
Device section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
Description
Operation
Designed for versatility and speed, the HIP6601A and
HIP6603A dual MOSFET drivers control both high-side and
low-side N-Channel FETs from one externally provided PWM
signal.
PWM (Pin 3)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller.
The upper and lower gates are held low until the driver is
initialized. Once the VCC voltage surpasses the VCC Rising
Threshold (See Electrical Specifications), the PWM signal
takes control of gate transitions. A rising edge on PWM
initiates the turn-off of the lower MOSFET (see Timing
GND (Pin 4)
Bias and reference ground. All signals are referenced to this
node.
Diagram). After a short propagation delay [t
lower gate begins to fall. Typical fall times [t
], the
PDLLGATE
] are
FLGATE
LGATE (Pin 5)
provided in the Electrical Specifications section. Adaptive
Lower gate drive output. Connect to gate of the low-side
power N-Channel MOSFET.
shoot-through circuitry monitors the LGATE voltage and
determines the upper gate delay time [t
] based
PDHUGATE
on how quickly the LGATE voltage drops below 2.2V. This
prevents both the lower and upper MOSFETs from
conducting simultaneously or shoot-through. Once this delay
period is complete the upper gate drive begins to rise
VCC (Pin 6)
Connect this pin to a +12V bias supply. Place a high quality
bypass capacitor from this pin to GND.
[t
] and the upper MOSFET turns on.
RUGATE
PVCC (Pin 7)
For the HIP6601A, this pin supplies the upper gate drive
bias. Connect this pin from +12V down to +5V.
Timing Diagram
PWM
t
PDHUGATE
t
PDLUGATE
t
RUGATE
t
FUGATE
UGATE
LGATE
t
RLGATE
t
FLGATE
t
t
PDHLGATE
PDLLGATE
4
HIP6601A, HIP6603A
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t ] is encountered before the
The bootstrap capacitor must have a maximum voltage
rating above VCC + 5V. The bootstrap capacitor can be
chosen from the following equation:
PDLUGATE
upper gate begins to fall [t
]. Again, the adaptive shoot-
FUGATE
through circuitry determines the lower gate delay time,
. The PHASE voltage is monitored and the lower
Q
GATE
-----------------------
C
≥
BOOT
∆V
BOOT
t
PDHLGATE
gate is allowed to rise after PHASE drops below 0.5V. The
Where Q
is the amount of gate charge required to fully
GATE
charge the gate of the upper MOSFET. The ∆V
defined as the allowable droop in the rail of the upper drive.
lower gate then rises [t ], turning on the lower
RLGATE
term is
BOOT
MOSFET.
Three-State PWM Input
As an example, suppose a HUF76139 is chosen as the
A unique feature of the HIP660X drivers is the addition of a
shutdown window to the PWM input. If the PWM signal
enters and remains within the shutdown window for a set
holdoff time, the output drivers are disabled and both
MOSFET gates are pulled and held low. The shutdown state
is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.
upper MOSFET. The gate charge, Q
GATE
, from the data
sheet is 65nC for a 10V upper gate drive. We will assume a
200mV droop in drive voltage over the PWM cycle. We find
that a bootstrap capacitance of at least 0.325µF is required.
The next larger standard value capacitance is 0.33µF.
Gate Drive Voltage Versatility
The HIP6601A and HIP6603A provide the user total
flexibility in choosing the gate drive voltage. The HIP6601A
lower gate drive is fixed to VCC [+12V], but the upper drive
rail can range from 12V down to 5V depending on what
voltage is applied to PVCC. The HIP6603A ties the upper
and lower drive rails together. Simply applying a voltage from
5V up to 12V on PVCC will set both driver rail voltages.
Adaptive Shoot-Through Protection
Both drivers incorporate adaptive shoot-through protection
to prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to rise.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
will push the IC beyond the maximum recommended
operating junction temperature of 125oC. The maximum
allowable IC power dissipation for the SO8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 2.2V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the PHASE voltage during UGATE turn-off. Once
PHASE has dropped below a threshold of 0.5V, the LGATE
is allowed to rise. PHASE continues to be monitored during
the lower gate rise time. If PHASE has not dropped below
0.5V within 250ns, LGATE is taken high to keep the
bootstrap capacitor charged. If the PHASE voltage exceeds
the 0.5V threshold during this period and remains high for
longer than 2µs, the LGATE transitions low. Both upper and
lower gates are then held low until the next rising edge of the
PWM signal.
3
2
--
P = 1.05f
V Q + V Q + I
V
DDQ
Power-On Reset (POR) Function
sw
U
L
L
CC
U
During initial startup, the VCC voltage rise is monitored and
gate drives are held low until a typical VCC rising threshold
of 9.95V is reached. Once the rising VCC threshold is
exceeded, the PWM input signal takes control of the gate
drives. If VCC drops below a typical VCC falling threshold of
9.2V during operation, then both gate drives are again held
low. This condition persists until the VCC voltage exceeds
the VCC rising threshold.
where f is the switching frequency of the PWM signal. V
sw
U
and V represent the upper and lower gate rail voltage. Q
L
U
and Q is the upper and lower gate charge determined by
L
MOSFET selection and any external capacitance added to
the gate pins. The I product is the quiescent power
V
DDQ CC
of the driver and is typically 30mW.
The power dissipation approximation is a result of power
transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip
during the refresh cycle. Expressing this power in terms of
the upper MOSFET total gate charge is explained below.
Internal Bootstrap Device
Both drivers feature an internal bootstrap device. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit.
5
HIP6601A, HIP6603A
The bootstrap device conducts when the lower MOSFET or
1000
800
600
400
200
PVCC = VCC = 12V
it’s body diode conducts and pulls the PHASE node toward
GND. While the bootstrap device conducts, a current path is
formed that refreshes the bootstrap capacitor. Since the
upper gate is driving a MOSFET, the charge removed from
the bootstrap capacitor is equivalent to the total gate charge
of the MOSFET. Therefore, the refresh power required by the
bootstrap capacitor is equivalent to the power used to
charge the gate capacitance of the MOSFET.
C
= C = 3nF
L
U
C
= C = 1nF
L
U
C
= C = 2nF
L
U
1
--
2
1
--
2
P
=
f
Q
V
=
f
Q V
SW
REFRESH
SW
LOSS
U
U
PVCC
C
C
= C = 4nF
L
U
U
= C = 5nF
L
where Q
is the total charge removed from the bootstrap
LOSS
capacitor and provided to the upper gate load.
0
500
1000
FREQUENCY (kHz)
1500
2000
The 1.05 factor is a correction factor derived from the
following characterization. The base circuit for characterizing
the drivers for different loading profiles and frequencies is
FIGURE 1. POWER DISSIPATION vs FREQUENCY
provided. C and C are the upper and lower gate load
U
L
capacitors. Decoupling capacitors [0.15µF] are added to the
PVCC and VCC pins. The bootstrap capacitor value is
0.01µF.
1000
PVCC = VCC = 12V
C
C
= 3nF
= 0nF
U
L
In Figure 1, C and C values are the same and frequency
800
600
400
200
U
L
is varied from 50kHz to 2MHz. PVCC and VCC are tied
together to a +12V supply. Curves do exceed the 800mW
cutoff, but continuous operation above this point is not
recommended.
C
= C = 3nF
L
U
C
C
= 3nF
= 0nF
L
U
Figure 2 shows the dissipation in the driver with 3nF loading
on both gates and each individually. Note the higher upper
gate power dissipation which is due to the bootstrap device
refresh cycle. Again PVCC and VCC are tied together and to
a +12V supply.
0
500
1000
FREQUENCY (kHz)
1500
2000
Test Circuit
FIGURE 2. 3nF LOADING PROFILE
+5V OR +12V
The impact of loading on power dissipation is shown in
Figure 3. Frequency is held constant while the gate
+5V OR +12V
+12V
0.01µF
capacitors are varied from 1nF to 5nF. VCC and PVCC are
tied together and to a +12V supply. Figures 4 through 6
show the same characterization for the HIP6603A with a
+5V supply on PVCC and VCC tied to a +12V supply.
BOOT
PVCC
2N7002
0.15µF
UGATE
C
U
PHASE
VCC
Since both upper and lower gate capacitance can vary,
Figure 7 shows dissipation curves versus lower gate
capacitance with upper gate capacitance held constant at
three different values. These curves apply only to the
HIP6601A due to power supply configuration.
LGATE
0.15µF
PWM
100kΩ
2N7002
C
L
GND
6
HIP6601A, HIP6603A
Typical Performance Curves
600
400
PVCC = VCC = 12V
FREQUENCY = 800kHz
500
PVCC = 5V VCC = 12V
= C = 5nF
320
240
160
80
C
U
L
C
= C = 4nF
L
U
400
FREQUENCY = 500kHz
C
= C = 3nF
L
U
300
200
100
C
C
= C = 2nF
L
U
U
= C = 1nF
L
FREQUENCY = 200kHz
4.0
1.0
2.0
3.0
5.0
0
500
1000
1500
2000
GATE CAPACITANCE (C = C ) (nF)
FREQUENCY (kHz)
U
L
FIGURE 3. POWER DISSIPATION vs LOADING
FIGURE 4. POWER DISSIPATION vs FREQUENCY (HIP6603A)
250
300
240
180
120
60
PVCC = 5V, VCC = 12V
PVCC = 5V, VCC = 12V
= C = 3nF
200
C
U
L
FREQUENCY = 800kHz
150
C
C
= 3nF
= 0nF
U
L
100
FREQUENCY = 500kHz
C
= 3nF
= 0nF
L
C
U
50
FREQUENCY = 200kHz
0
1.0
2.0
3.0
4.0
5.0
0
500
1000
FREQUENCY (kHz)
1500
2000
GATE CAPACITANCE (C = C ) (nF)
U
L
FIGURE 5. 3nF LOADING PROFILE (HIP6603A)
FIGURE 6. VARIABLE LOADING PROFILE (HIP6603A)
400
PVCC = 5V, VCC = 12V
C
C
= 5nF
= 3nF
U
U
350
300
200
150
100
C
= 1nF
U
1.0
2.0
3.0
4.0
5.0
FREQUENCY (kHz)
FIGURE 7. POWER DISSIPATION vs FREQUENCY (HIP6601A)
7
HIP6601A, HIP6603A
Small Outline Exposed Pad Plastic Packages (EPSOIC)
M8.15B
N
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.43
0.03
0.35
0.19
4.80
3.31
MAX
1.68
0.13
0.49
0.25
4.98
3.39
NOTES
A
A1
B
C
D
E
e
0.056
0.001
0.0138
0.0075
0.189
0.150
0.066
0.005
0.0192
0.0098
0.196
0.157
-
1
2
3
-
TOP VIEW
9
-
L
3
SEATING PLANE
A
4
-A-
D
0.050 BSC
1.27 BSC
-
o
h x 45
H
h
0.230
0.010
0.016
0.244
0.016
0.035
5.84
0.25
0.41
6.20
0.41
0.64
-
-C-
5
α
L
6
e
B
A1
C
N
8
8
7
0.10(0.004)
o
o
o
o
0
8
0
8
-
11
α
P
0.25(0.010) M
SIDE VIEW
C A M B S
-
-
0.090
0.090
-
-
2.286
2.286
P1
11
Rev. 0 6/00
NOTES:
1
2
3
1. Symbols are defined in the “MO Series Symbol List” in
Section 2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P1
3. Dimension “D” does not include mold flash, protrusions or
gate burrs. Mold flash, protrusion and gate burrs shall not
exceed 0.15mm (0.006 inch) per side.
N
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm
(0.010 inch) per side.
P
BOTTOM VIEW
5. The chamfer on the body is optional. If it is not present, a
visual index feature must be located within the crosshatched
area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or
greater above the seating plane, shall not exceed a
maximum value of 0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical
enhanced variations. Values shown are maximum size of
exposed pad within lead count and body size.
8
HIP6601A, HIP6603A
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
8
8
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
EUROPE
ASIA
Intersil Corporation
Intersil SA
Intersil Ltd.
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
Mercure Center
8F-2, 96, Sec. 1, Chien-kuo North,
Taipei, Taiwan 104
Republic of China
TEL: 886-2-2515-8508
FAX: 886-2-2515-8369
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
9
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