HM4-6617B/883 [RENESAS]
2KX8 OTPROM, 105ns, CQCC32;
| 型号： | HM4-6617B/883 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 2KX8 OTPROM, 105ns, CQCC32 可编程只读存储器 OTP只读存储器 内存集成电路 |
| 文件： | 总7页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM-6617/883
2K x 8 CMOS PROM
January 2001
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HM-6617/883 is a 16,384-bit fuse link CMOS PROM in
a 2K word by 8-bit/word format with “Three-State” outputs.
This PROM is available in the standard 0.600 inch wide 24
pin SBDIP, the 0.300 inch wide slim SBDIP, and the JEDEC
standard 32 pad CLCC.
• Low Power Standby and Operating Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . .20mA at 1MHz
The HM-6617/883 utilizes a synchronous design technique.
This includes on-chip address latches and a separate output
enable control which makes this device ideal for applications
utilizing recent generation microprocessors. This design
technique, combined with the Intersil advanced self-aligned
silicon gate CMOS process technology offers ultra-low
standby current. Low ICCSB is ideal for battery applications
or other systems with low power requirements.
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 90/120ns
• Industry Standard Pinout
• Single 5.0V Supply
• CMOS/TTL Compatible Inputs
• High Output Drive . . . . . . . . . . . . . . . . 12 LSTTL Loads
• Synchronous Operation
The Intersil NiCr fuse link technology is utilized on this and
other Intersil CMOS PROMs. This gives the user a PROM
with permanent, stable storage characteristics over the full
industrial and military temperature voltage ranges. NiCr fuse
technology combined with the low power characteristics of
CMOS provides an excellent alternative to standard bipolar
PROMs or NMOS EPROMs.
• On-Chip Address Latches
• Separate Output Enable
o
o
• Operating Temperature Range . . . . . . -55 C to +125 C
All bits are manufactured storing a logical “0” and can be
selectively programmed for a logical “1” at any bit location.
Ordering Information
PACKAGE
TEMPERATURE RANGE
90ns
HM1-6617B/883
HM6-6617B/883
HM4-6617B/883
120ns
HM1-6617/883
HM6-6617/883
HM4-6617/883
PACKAGE NO.
D24.6
o
o
SBDIP
-55 C to +125 C
o
o
SLIM SBDIP
CLCC
-55 C to +125 C
D24.3
o
o
-55 C to +125 C
J32.A
Pinouts
HM-6617/883 (SBDIP)
TOP VIEW
HM-6617/883 (CLCC)
TOP VIEW
PIN DESCRIPTION
PIN
DESCRIPTION
No Connect
1
2
24
23
22
21
20
19
18
17
16
15
14
13
A7
A6
V
1
CC
4
3
2
32 31 30
NC
29
28
27
26
A8
A9
P
A8
A9
NC
P
A6
A5
5
6
A0-A10
Address Inputs
Chip Enable
3
A5
4
A4
E
A4
A3
A2
A1
A0
NC
Q0
7
8
5
A3
G
Q
Data Output
6
A2
A10
E
25 G
9
V
Power (+5V)
Output Enable
Program Enable
7
A1
CC
A10
10
11
12
13
24
23
22
8
A0
Q7
Q6
Q5
Q4
Q3
G
E
9
Q0
Q1
Q2
GND
P (Note)
Q7
10
11
12
NOTE: P should be hardwired to V
21 Q6
CC
except during programming.
14
15 16 17 18 19 20
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3016.2
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2001
1
HM-6617/883
Functional Diagram
MSB
A10
A
A
A9
A8
LATCHED
7
7
GATED
ROW
Q0
Q1
128 x 128
MATRIX
ADDRESS
A7
128
REGISTER
DECODER
A6
A5
A4
LSB
Q2
Q3
L
G
16 16 16 16 16 16 16 16
GATED COLUMN
DECODER AND DATA
OUTPUT CONTROL
G
8
Q4
Q5
E
A
A
4
4
Q6
Q7
G
L
LATCHED ADDRESS
REGISTER
ALL LINES POSITIVE LOGIC: ACTIVE HIGH
THREE-STATE BUFFERS:
MSB
LSB
A HIGH
OUTPUT ACTIVE
ADDRESS LATCHES AND GATED DECODERS:
A3
A2
A1
A0
LATCH ON FALLING EDGE OF E
GATE ON FALLING EDGE OF G
2
HM-6617/883
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
Typical Derating Factor. . . . . . . . . . . . 5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
SBDIP Package. . . . . . . . . . . . . . . . . . 48 C/W
Slim SBDIP . . . . . . . . . . . . . . . . . . . . . 65 C/W
CLCC Package . . . . . . . . . . . . . . . . . . 58 C/W
Maximum Storage Temperature Range . . . . . . . . .-65 C to +150 C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300 C
θ
θ
JC
JA
o
o
9 C/W
o
o
14 C/W
o
o
19 C/W
o
o
o
Operating Conditions
o
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . +2.4V to VCC +0.3V
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5473 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TABLE 1. HM-6617/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
LIMITS
(NOTES 1, 4)
GROUP A
PARAMETER
SYMBOL
VOH1
VOL
CONDITIONS
SUBGROUPS
TEMPERATURE
MIN
2.4
-
MAX
-
UNITS
o
o
High Level Output Voltage
Low Level Output Voltage
VCC = 4.5V, IO = -2.0mA
VCC = 4.5V, IO = +4.8mA
1, 2, 3
1, 2, 3
1, 2, 3
-55 C ≤ TA ≤ +125 C
V
V
o
o
-55 C ≤ TA ≤ +125 C
0.4
1.0
o
o
High Impedance Output
Leakage Current
IIOZ
VCC = 5.5V, G = 5.5V,
VI/O = GND or VCC
-55 C ≤ TA ≤ +125 C
-1.0
µA
o
o
Input Leakage Current
Standby Supply Current
Operating Supply Current
II
VCC = 5.5V, VI = GND or
VCC, P Not Tested
1, 2, 3
1, 2, 3
1, 2, 3
-55 C ≤ TA ≤ +125 C
-1.0
1.0
100
20
µA
µA
mA
o
o
ICCSB VI = VCC or GND,
VCC = 5.5V, IO = 0mA
-55 C ≤ TA ≤ +125 C
-
-
o
o
ICCOP VCC = 5.5V, G = GND,
(Note 3), f = 1MHz, IO =
-55 C ≤ TA ≤ +125 C
0mA, VI = VCC or GND
o
o
Functional Test
FT
VCC = 4.5V (Note 6)
7, 8A, 8B
-55 C ≤ TA ≤ +125 C
-
-
TABLE 2. HM-6617/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
LIMITS
LIMITS
HM-6617B/883 HM-6617/883
(NOTES 1, 2, 4)
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUPS TEMPERATURE
MIN
MAX
MIN
MAX UNITS
o
o
Address Access Time
TAVQV
VCC = 4.5V and 5.5V
(Note 5)
9, 10, 11
9, 10, 11
9, 10, 11
-55 C ≤ TA ≤ +125 C
-
105
-
140
50
ns
ns
ns
o
o
Output Enable Access
Time
TGLQV
TELQV
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
-55 C ≤ TA ≤ +125 C
-
-
40
90
-
-
o
o
Chip Enable Access
Time
-55 C ≤ TA ≤ +125 C
120
o
o
Address Setup Time
Address Hold Time
TAVEL
TELAX
TELEH
TEHEL
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 C ≤ TA ≤ +125 C
15
20
95
40
-
-
-
-
20
25
-
-
-
-
ns
ns
ns
ns
o
o
-55 C ≤ TA ≤ +125 C
o
o
Chip Enable Low Width
Chip Enable High Width
-55 C ≤ TA ≤ +125 C
120
40
o
o
-55 C ≤ TA ≤ +125 C
3
HM-6617/883
TABLE 2. HM-6617/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested
LIMITS
LIMITS
HM-6617B/883 HM-6617/883
(NOTES 1, 2, 4)
GROUP A
PARAMETER
Read Cycle Time
NOTES:
SYMBOL
CONDITIONS
SUBGROUPS TEMPERATURE
MIN
MAX
MIN
MAX UNITS
ns
o
o
TELEL
VCC = 4.5V and 5.5V
9, 10, 11
-55 C ≤ TA ≤ +125 C
136
-
160
-
1. All voltages referenced to Device GND.
2. AC measurements assume transition time ≤ 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1TTL equiva-
lent load and CL 50pF.
3. Typical derating = 5mA/MHz increase in ICCOP.
4. All tests performed with P hardwired to VCC.
5. TAVQV = TELQV + TAVEL.
6. Tested as follows: f = 1MHz, VIH = 2.4V, VIL = 0.8V, IOH = -1mA, IOL = +1mA, VOH ≥ 1.5V, VOL ≤ 1.5V.
TABLE 3. HM-6617/883 AC AND DC ELECTRICAL PERFORMANCE SPECIFICATIONS
LIMITS
LIMITS
HM-6617B/883 HM-6617/883
(NOTES 1, 2)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
MIN
MAX UNITS
o
Input Capacitance
CIN
VCC = Open, f = 1MHz, All
Measurements Referenced to
Device GND
2, 3
+25 C
-
10
-
10
pF
o
VCC = Open, f = 1MHz, All
Measurements Referenced to
Device GND
2, 4
2, 5
2, 3
+25 C
-
-
-
12
10
12
-
-
-
12
10
12
pF
pF
pF
o
+25 C
o
I/O Capacitance
CI/O
VCC = Open, f = 1MHz, All
Measurements Referenced to
Device GND
+25 C
o
VCC = Open, f = 1MHz, All
Measurements Referenced to
Device GND
2, 4
2, 5
2
+25 C
-
-
14
12
-
-
-
14
12
-
pF
pF
ns
ns
ns
ns
V
o
+25 C
o
o
Chip Enable Time
Output Enable Time
Chip Disable Time
Output Disable Time
Output High Voltage
TELQX
TGLQX
TEHQZ
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
-55 C ≤ TA ≤ +125 C
5
5
-
5
5
-
o
o
2
-55 C ≤ TA ≤ +125 C
-
-
o
o
2
-55 C ≤ TA ≤ +125 C
45
40
-
50
50
-
o
o
TGHQZ VCC = 4.5V and 5.5V
VOH2 VCC = 4.5V, IO = 100µA
2
-55 C ≤ TA ≤ +125 C
-
-
o
o
2
-55 C ≤ TA ≤ +125 C VCC-
VCC-
1V
1V
NOTES:
1. All tests performed with P hardwired to VCC.
2. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-
acterized upon initial design changes which would affect these characteristics.
3. Applies to 0.600 inch SBDIP device types only.
4. Applies to 0.300 inch SBDIP device types only.
5. Applies to Ceramic Leadless Chip Carrier (CLCC) device types only.
4
HM-6617/883
TABLE 4. APPLICABLE SUBGROUPS
METHOD
CONFORMANCE GROUPS
Initial Test
SUBGROUPS
100%/5004
100%/5004
-
Interim Test
PDA
1, 7, 9
100%/5004
1
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
Group A
Samples/5005
Samples/5005
Groups C & D
Switching Waveforms
TAVQV
1.5V
3.0V
0V
VALID
ADDRESSES
VALID
ADDRESS
1.5V
ADDRESSES
TELEL
TAVEL
TELAX
1.5V
TELEH
TGLQV
3.0V
0V
1.5V
1.5V
1.5V
TEHEL
E
TEHQZ
TELQV
3.0V
0V
G
1.5V
1.5V
TGLQX
TELQX
TGHQZ
DATA
OUTPUT
Q0-Q7
VALID
DATA
T
S
FIGURE 1. READ CYCLE
Test Circuit
DUT
C
L
(NOTE)
I
OH
1.5V
I
OL
±
NOTE:
TEST HEAD
CAPACITANCE
EQUIVALENT CIRCUIT
FIGURE 2. TEST CIRCUIT
5
HM-6617/883
Burn-In Circuits
HM-6617/883 (.300 INCH) SBDIP
HM-6617/883 (.600 INCH) SBDIP
VCC
VCC
C
C
f8
f7
f6
f5
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
24
23
22
21
20
19
18
17
16
15
1
2
24
23
22
21
20
19
18
17
16
1
2
f8
VCC
A8
A9
P
VCC
A6
A5
P
f9
f7
f6
f5
f4
f3
f2
f1
f11
f10
3
3
f12
VCC
f12
f11
f0
VCC
4
4
5
5
f4
f3
f2
f1
G
G
f1
6
6
f13
A10
A10
7
7
f0
E
Q7
Q6
E
Q7
Q6
2.4K
8
8
2.4K
2.4K
2.4K
2.4K
2.4K
2.4K
2.4K
9
9
VCC/2
Q5
10
11
12
10
11
12
Q5 15
VCC/2
VCC/2
VCC/2
Q4 14
Q3
14
Q4
13
13
Q3
GND
GND
HM-6617/883 CLCC
VCC
f10
C
NC NC NC
NC NC
32 31 30
4
3
2
1
f11
f9
29
5
6
f12
f8
f7
f6
f5
f4
f3
28
27
26
25
24
23
22
21
7
8
NC
VCC
9
f1
f13
f0
10
11
12
13
NC
VCC/2
VCC/2
14
15 16 17 18 19 20
NC
VCC/2
VCC/2
NOTES:
f0 = 100KHz ± 10%.
All resistors = 47kΩ Unless Otherwise Noted.
VCC = 5.5V ± 0.05V.
C = 0.01 µF min.
6
HM-6617/883
Die Characteristics
DIE DIMENSIONS:
GLASSIVATION:
Type: SiO
140 x 232 x 19 ± 1mils
2
Thickness: 7kÅ ± 9kÅ
METALLIZATION:
Type: Si - Al
WORST CASE CURRENT DENSITY:
5
2
Thickness: 11kÅ ± 15kÅ
1.7 x 10 A/cm
Metallization Mask Layout
HM-6617/883
A4 A5
A6 A7 VCC A8 A9
P
G
A3
A2
A10
A1
A0
E
Q7
Q0
Q1 Q2 GND
Q3 Q4
Q5 Q6
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
7
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