HM62256BLTM-8SL [RENESAS]
IC,SRAM,32KX8,CMOS,TSSOP,28PIN,PLASTIC;
| 型号： | HM62256BLTM-8SL |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,SRAM,32KX8,CMOS,TSSOP,28PIN,PLASTIC 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM62256B Series
32,768-word × 8-bit High Speed CMOS Static RAM
The Hitachi HM62256B is a CMOS static RAM
Ordering Information
organized 32-kword × 8-bit. It realizes higher
performance and low power consumption by
employing 0.8 µm Hi-CMOS process technology.
The device, packaged in 8 × 14 mm TSOP, 8 × 13.4
mm TSOP with thickness of 1.2 mm, 450-mil SOP
(foot print pitch width), 600-mil plastic DIP, or
300-mil plastic DIP, is available for high density
mounting. It offers low power standby power
dissipation; therefore, it is suitable for battery back-
up systems.
Type No.
Access time Package
————————————————————–
HM62256BLP-7
HM62256BLP-8
HM62256BLP-10
HM62256BLP-12
70 ns
600-mil
85 ns
28-pin
100 ns
120 ns
plastic DIP
(DP-28)
—————————————
HM62256BLP-7SL
HM62256BLP-8SL
HM62256BLP-10SL
HM62256BLP-12SL
70 ns
85 ns
100 ns
120 ns
————————————————————–
HM62256BLSP-7
HM62256BLSP-8
HM62256BLSP-10
HM62256BLSP-12
70 ns
300-mil
85 ns
28-pin
100 ns
120 ns
plastic DIP
(DP-28NA)
Features
—————————————
HM62256BLSP-7SL
HM62256BLSP-8SL
HM62256BLSP-10SL 100 ns
HM62256BLSP-12SL 120 ns
————————————————————–
HM62256BLFP-7T
HM62256BLFP-8T
HM62256BLFP-10T
HM62256BLFP-12T
—————————————
HM62256BLFP-7SLT 70 ns
HM62256BLFP-8SLT 85 ns
HM62256BLFP-10SLT 100 ns
HM62256BLFP-12SLT 120 ns
70 ns
85 ns
• High speed
Fast access time: 70/85/100/120 ns (max)
• Low power
Standby: 1.5 µW (typ)
Operation: 25 mW (typ) (f = 1 MHz)
• Single 5 V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
Three state output
• Directly TTL compatible
All inputs and outputs
• Capability of battery back up operation
70 ns
85 ns
100 ns
120 ns
450-mil
28-pin
plastic SOP
(FP-28DA)
————————————————————–
HM62256BLT-8
HM62256BLT-10
HM62256BLT-12
85 ns
100 ns
120 ns
8 mm × 14 mm
32-pin TSOP
(TFP-32DA)
—————————————
HM62256BLT-7SL
70 ns
HM62256BLT-8SL
85 ns
————————————————————–
HM62256BLTM-8
—————————————
HM62256BLTM-7SL
85 ns
8 mm × 13.4 mm
28-pin TSOP
(TFP-28DA)
70 ns
HM62256BLTM-8SL
85 ns
————————————————————
1
HM62256B Series
HM62256B Series
Pin Arrangement
HM62256BLP/BLFP/BLSP Series
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A14
A12
A7
2
3
4
A6
5
A9
A5
6
A11
OE
A10
CS
A4
7
A3
8
A2
9
A1
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
A0
I/O0
I/O1
I/O2
VSS
(Top View)
HM62256BLT Series
OE
A10
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
NC
A9
NC
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A8
A13
WE
VCC
A14
A12
A7
A6
A5
NC
A4
NC
A1
A3
A2
(Top View)
HM62256BLTM Series
A10
CS
OE
A11
A9
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
I/O7
I/O6
I/O5
I/O4
I/O3
A8
A13
WE
V
CC
V
A14
A12
A7
SS
I/O2
I/O1
I/O0
A0
2
3
A6
4
A5
5
A1
A2
A4
6
A3
7
8
(Top View)
2
HM62256B Series
HM62256B Series
Pin Description
Symbol
Function
Symbol
Function
————————————————————
————————————————————
OE
Output enable
————————————————————
A0 – A14
Address
————————————————————
NC
No connection
I/O0 – I/O7
Input/output
————————————————————
————————————————————
V
Power supply
CS
Chip select
CC
————————————————————
————————————————————
V
Ground
WE
Write enable
SS
————————————————————
————————————————————
Block Diagram
V CC
V SS
A12
A5
•
A7
•
•
•
•
•
•
•
•
•
Memory Matrix
A6
Row
Decoder
×
512 512
A8
A13
A14
A4
A3
I/O0
•
•
•
•
Column I/O
•
•
•
•
•
•
Input
Data
Control
Column Decoder
•
•
•
•
•
•
•
•
•
I/O7
A1 A0 A10 A9 A11
A2
•
•
Timing Pulse Generator
Read/Write Control
CS
WE
OE
3
HM62256B Series
HM62256B Series
Function Table
WE
CS
OE
Mode
V
current
I/O pin
Ref. cycle
CC
———————————————————————————————————————————
X
H
X
Not selected
I
, I
High-Z
—
SB SB1
———————————————————————————————————————————
H
L
H
Output disable
I
High-Z
—
CC
———————————————————————————————————————————
H
L
L
Read
I
Dout
Read cycle (1)–(3)
CC
———————————————————————————————————————————
L
L
H
Write
I
Din
Write cycle (1)
CC
———————————————————————————————————————————
L
L
L
Write
I
Din
Write cycle (2)
CC
———————————————————————————————————————————
Note: X: H or L
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
———————————————————————————————————————————
*1
Power supply voltage
V
–0.5 to +7.0
V
CC
———————————————————————————————————————————
*1
2
*3
+ 0.3
CC
Terminal voltage
V
–0.5* to V
V
T
———————————————————————————————————————————
Power dissipation
P
1.0
W
T
———————————————————————————————————————————
Operating temperature
Topr
0 to + 70
°C
———————————————————————————————————————————
Storage temperature
Tstg
–55 to +125
°C
———————————————————————————————————————————
Storage temperature under bias
Tbias
–10 to +85
°C
———————————————————————————————————————————
Note: 1. Relative to V
SS
2. V min: –3.0 V for pulse half-width ≤ 50 ns
T
3. Maximum voltage is 7.0 V
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit
———————————————————————————————————————————
Supply voltage
V
4.5
5.0
5.5
V
CC
———————————————————————————————
V
0
0
0
V
SS
———————————————————————————————————————————
Input high (logic 1) voltage
V
2.2
—
V
+0.3
V
IH
CC
———————————————————————————————————————————
*1
Input low (logic 0) voltage
V
–0.5
—
0.8
V
IL
———————————————————————————————————————————
Note: 1. V min: –3.0 V for pulse half-width ≤ 50 ns
IL
4
HM62256B Series
HM62256B Series
DC Characteristics (Ta = 0 to +70°C, V = 5 V ±10%, V = 0 V)
CC
SS
Parameter
Symbol Min
Typ*1 Max
Unit
Test conditions
——————————————————————————————————————————
Input leakage current
|I |
—
—
1
µA
Vin = V to V
LI
SS CC
——————————————————————————————————————————
Output leakage current
|I
|
—
—
1
µA
CS = V or OE = V or WE = V
I/O
LO
IH IH IL,
= V to V
SS CC
V
——————————————————————————————————————————
Operating power supply
current
I
—
6
15
mA
CS = V others = V /V
CC
IL, IH IL
Iout = 0 mA
——————————————————————————————————————————
Average
HM62256B-7
I
—
33
60
mA
min cycle, duty = 100 %, I = 0 mA
CC1
I/O
operating ——————
—————————
CS = V others = V /V
IL, IH IL
power
supply
current
HM62256B-8
——————
HM62256B-10
——————
HM62256B-12
—
29
50
—————————
—
26
50
—————————
—
24
45
—————————————————————————————————————
I
—
5
15
mA
Cycle time = 1 µs, I = 0 mA
CC2
I/O
CS = V
V
= V , V = 0
IL, IH CC IL
——————————————————————————————————————————
Standby V
current
I
—
0.3
2
mA
CS = V
CC
SB
IH
———————————————————————————————
I
—
0.3
100
µA
Vin ≥ 0 V,
SB1
—————————
—
CS > V
– 0.2 V,
CC
0.3*2
50*2
——————————————————————————————————————————
Output low voltage
V
—
—
0.4
V
I
= 2.1 mA
OL
OL
——————————————————————————————————————————
Output high voltage
V
2.4
—
—
V
I
= –1.0 mA
OH
OH
——————————————————————————————————————————
Notes: 1. Typical values are at V
= 5.0 V, Ta = +25°C and not guaranteed.
CC
2. This characteristics is guaranteed only for L-SL version.
*1
Capacitance (Ta = 25°C, f = 1.0 MHz)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
——————————————————————————————————————————
Input capacitance
Cin
—
—
8
pF
Vin = 0 V
——————————————————————————————————————————
Input/output capacitance
C
—
—
10
pF
V
= 0 V
I/O
I/O
——————————————————————————————————————————
Note: 1. This parameter is sampled and not 100% tested.
5
HM62256B Series
HM62256B Series
AC Characteristics (Ta = 0 to +70°C, V = 5 V ± 10%, unless otherwise noted.)
CC
Test Conditions
• Input pulse levels: 0.8 V to 2.4 V
• Input and output timing reference level: 1.5 V
• Input rise and fall times: 5 ns
• Output load: 1 TTL Gate + CL (100 pF)
(Including scope & jig)
Read Cycle
HM62256B-7 HM62256B-8 HM62256B-10 HM62256B-12
———— ———— ———— —————
Symbol Min Max Min Max Min Max Min Max Unit Notes
Parameter
———————————————————————————————————————————
Read cycle time
t
70
—
85
—
100
—
120
—
ns
RC
———————————————————————————————————————————
Address access time
t
—
70
—
85
—
100
—
120
ns
AA
———————————————————————————————————————————
Chip select access time
t
—
70
—
85
—
100
—
120
ns
ACS
———————————————————————————————————————————
Output enable to output valid
t
—
40
—
45
—
50
—
60
ns
OE
———————————————————————————————————————————
Chip selection to output in low-Z
t
10
—
10
—
10
—
10
—
ns
2
CLZ
———————————————————————————————————————————
Output enable to output in low-Z
t
5
—
5
—
5
—
5
—
ns
2
OLZ
———————————————————————————————————————————
Chip deselection to output in high-Z
t
0
25
0
30
0
35
0
40
ns
1, 2
CHZ
———————————————————————————————————————————
Output disable to output in high-Z
t
0
25
0
30
0
35
0
40
ns
1, 2
OHZ
———————————————————————————————————————————
Output hold from address change
t
5
—
5
—
10
—
10
—
ns
OH
———————————————————————————————————————————
Read Timing Waveform (1)*3
t RC
Address
tAA
tACS
CS
*2
t CLZ
tOH
t OE
*2
OLZ
t
OE
*1, *2
*1, *2
tOHZ
tCHZ
Dout
Valid Data
6
HM62256B Series
HM62256B Series
Read Timing Waveform (2)*3 *4 *6
t
RC
Address
t
OH
t
t
OH
AA
Dout
Valid Data
Read Timing Waveform (3)*3 *5 *6
CS
t
*1, *2
ACS
t
CHZ
*2
t
CLZ
Valid Data
Dout
Notes: 1. t
and t
defined as the time at which the outputs achieve the open circuit conditions and
CHZ
OHZ
are not referred to output voltage levels.
2. This parameter is sampled and not 100 % tested.
3. WE is high for read cycle.
4. Device is continuously selected, CS = V
IL
5. Address must be valid prior to or coincident with CS transition Low.
6. OE = V
IL
7
HM62256B Series
HM62256B Series
Write Cycle
HM62256B-7 HM62256B-8 HM62256B-10 HM62256B-12
———— ————– ————– ————–
Symbol Min Max Min Max Min Max Min Max
Parameter
Unit Notes
——————————————————————————————————————————
Write cycle time
t
70
—
85
—
100
—
120
—
ns
WC
——————————————————————————————————————————
Chip selection to
t
60
—
75
—
80
—
85
—
ns
2
CW
end of write
——————————————————————————————————————————
Address setup time
t
0
—
0
—
0
—
0
—
ns
3
AS
——————————————————————————————————————————
Address valid to
t
60
—
75
—
80
—
85
—
ns
AW
end of write
——————————————————————————————————————————
Write pulse width
t
50
—
55
—
60
—
70
—
ns
1, 12
WP
——————————————————————————————————————————
Write recovery time
t
0
—
0
—
0
—
0
—
ns
4
WR
——————————————————————————————————————————
WE to output in high-Z
t
0
25
0
30
0
35
0
40
ns
10, 11
WHZ
——————————————————————————————————————————
Data to write time overlap
t
30
—
35
—
40
—
50
—
ns
DW
——————————————————————————————————————————
Data hold from write time
t
0
—
0
—
0
—
0
—
ns
DH
——————————————————————————————————————————
Output active from
t
5
—
5
—
5
—
5
—
ns
10
OW
end of write
——————————————————————————————————————————
Output disable to output t
0
25
0
30
0
35
0
40
ns
10, 11
OHZ
in high-Z
——————————————————————————————————————————
8
HM62256B Series
HM62256B Series
Write Timing Waveform (1) (OE Clock)
tWC
Address
*4
tAW
tWR
OE
CS
*2
tCW
*6
*1
*3
tWP
tAS
WE
*5, *10
tOHZ
Dout
Din
tDW
tDH
Valid Data
9
HM62256B Series
HM62256B Series
12
Write Timing Waveform (2) (OE Low Fixed)*
tWC
Address
*4
tWR
*2
tCW
CS
*6
tAW
*1, *12
tWP
tOH
*3
WE
tAS
*10
*5, *10
tWHZ
tOW
*8
*7
Dout
Din
tDW
tDH
*9
Valid Data
Notes: 1. A write occurs during the overlap(t ) of a low CS and a low WE. A write begins at the later
WP
transition of CS going low or WE going low. A write ends at the earlier transition of CS going
high or WE going high. t
is measured from the beginning of write to the end of write.
WP
2.
3.
4.
t
t
t
is measured from CS going low to the end of write.
is measured from the address valid to the beginning of write.
CW
AS
is measured from the earlier of WE or CS going high to the end of write cycle.
WR
5. During this period, I/O pins are in the output state so that the input signals of the opposite
phase to the outputs must not be applied.
6. If the CS low transition occurs simultaneously with the WE low transition or after the WE
transition, the outputs remain in a high impedance state.
7. Dout is the same phase of the write data of this write cycle.
8. Dout is the read data of next address.
9. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of
the opposite phase to the output must not be applied to them.
10. This parameter is sampled and not 100% tested.
11. t
and t
are defined as the time at which the outputs achieve the open circuit conditions
OHZ
WHZ
and are not referred to output voltage levels.
12. In the write cycle with OE low fixed, t must satisfy the following equation to avoid a problem
WP
of data bus contention, t
≥ t
max + t
min.
WP
WHZ
DW
10
HM62256B Series
HM62256B Series
Low V Data Retention Characteristics (Ta = 0 to +70°C)
CC
1
Parameter
Symbol Min
Typ* Max
Unit
Test conditions
———————————————————————————————————————————
V
for data retention
V
2.0
—
5.5
V
CS > V
–0.2 V,
CC
DR
CC
Vin > 0 V*5
———————————————————————————————————————————
Data retention current
I
—
0.2
—————————————
0.2 µA
10*3
30*2
µA
V
= 3.0 V, Vin > 0 V*5
CCDR
CC
—
CS > V
–0.2 V,
CC
———————————————————————————————————————————
Chip deselect to data retention time
t
0
—
—
ns
See retention waveform
CDR
————————————————————————————————
*4
Operation recovery time
t
t
—
—
ns
R
RC
———————————————————————————————————————————
Low V
Data Retention Timing Waveform
CC
Data retention mode
VCC
4.5 V
tR
tCDR
2.4 V
VDR
CS
0 V
≥
CS VCC – 0.2 V
Notes: 1. Typical values are at V
= 3.0 V, Ta = 25°C and not guaranteed.
CC
2. 10 µA max at Ta = 0 to + 40˚C.
3. 3 µA max at Ta = 0 to + 40˚C. (only for L-SL version)
4. t
= read cycle time.
RC
5. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data retention
mode, Vin levels (address, WE, OE, I/O) can be in the high impedance state.
11
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