HM64YLB36512 [RENESAS]
16M Synchronous Late Write Fast Static RAM (512-kword × 36-bit); 16M同步后写高速静态RAM （ 512千字× 36位）
| 型号： | HM64YLB36512 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 16M Synchronous Late Write Fast Static RAM (512-kword × 36-bit) |
| 文件： | 总31页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM64YLB36512 Series
16M Synchronous Late Write Fast Static RAM
(512-kword × 36-bit)
REJ03C0270-0300
Rev.3.00
Jan.13.2006
Description
The HM64YLB36512 is a synchronous fast static RAM organized as 512-kword × 36-bit. It has realized high speed
access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most
appropriate for the application which requires high speed, high density memory and wide bit width configuration, such
as cache and buffer memory in system. It is packaged in standard 119-bump BGA.
Note: All power supply and ground pins must be connected for proper operation of the device.
Features
•
•
•
•
•
•
•
•
•
•
•
•
2.5 V ± 5% operation and 1.5 V (VDDQ)
16M bit density
Byte write control (4 byte write selects, one for each 9-bit)
Optional ×18 configuration
HSTL compatible I/O
Programmable impedance output drivers
Asynchronous G output control
Asynchronous sleep mode
FC-BGA 119pin package with SRAM JEDEC standard pinout
Limited set of boundary scan JTAG IEEE 1149.1 compatible
Mode selectable among late write, associative late write (late select) and register-latch
Late select mode:
Synchronous register to register operation
Late SAS select, selects which half of 72-bit core data to return on reads
SAS serves as way select
Differential HSTL clock inputs
•
•
Late write mode:
Synchronous register to register operation
Differential HSTL clock inputs
Register-latch mode:
Synchronous register to latch operation
Differential pseudo-HSTL clock inputs
Rev.3.00 Jan 13, 2006 page 1 of 29
HM64YLB36512 Series
Ordering Information
Type No.
Organization
Modes
Access time Cycle time
Package
HM64YLB36512BP-28 512k × 36
Late select mode
Late write mode
1.6 ns
2.8 ns
3.3 ns
6.5 ns
119-bump 1.27 mm
14 mm × 22 mm BGA
PRBG0119DB-A (BP-119E)
HM64YLB36512BP-33 512k × 36
Late select mode
Late write mode
1.6 ns
Register-latch mode 5.5 ns
Note: HM: Hitachi Memory prefix, 64: External Cache SRAM, Y: VDD = 2.5 V, L: Dual Mode SRAM, B: VDDQ = 1.5 V
Pin Arrangement
1
2
3
4
NC
5
6
7
A
B
C
D
E
F
VDDQ
NC
SA14
SA15
SA16
DQc8
DQc6
DQc4
DQc2
DQc0
VDD
SA13
SA12
SA11
VSS
SA6
SA5
SA4
VSS
SA7
VDDQ
NC
NC
SA9
NC
VDD
ZQ
SA8
NC
DQc7
DQc5
VDDQ
DQc3
DQc1
VDDQ
DQd1
DQd3
VDDQ
DQd5
DQd7
NC
DQb8
DQb6
DQb4
DQb2
DQb0
VDD
DQb7
DQb5
VDDQ
DQb3
DQb1
VDDQ
DQa1
DQa3
VDDQ
DQa5
DQa7
NC
VSS
SS
G
VSS
VSS
VSS
G
H
J
SWEc
VSS
NC
SWEb
VSS
NC
VREF
VSS
VDD
K
VREF
VSS
K
L
DQd0
DQd2
DQd4
DQd6
DQd8
SA10
NC
DQa0
DQa2
DQa4
DQa6
DQa8
SA1
SWEd
VSS
K
SWEa
VSS
M
N
P
R
T
SWE
SA17
SAS/SA0
VDD
SA3
TCK
VSS
VSS
VSS
VSS
M1
M2
NC
SA18
TDI
SA2
TDO
NC
ZZ
U
VDDQ
TMS
NC
VDDQ
(Top view)
Note: 4P pin is SAS in both the late select mode and the late write mode, or is SA0 in the register-latch mode.
Rev.3.00 Jan 13, 2006 page 2 of 29
HM64YLB36512 Series
Block Diagram (Late Select Mode)
Read
add. reg.
SA1 to SA18
Write
add. reg.
1
0
Memory array
(way0)
256k × 36
Memory array
(way1)
256k × 36
SA1 to SA18
compare
Match0
0
1
0
1
0 1
Read
Write
SAS
add. reg.
Match1
add. reg.
SWEx
1st reg.
SWEx
2nd reg.
Byte write
control
(x: a to d)
Output
reg.
Din
reg.
Output
reg.
SS
reg.
Way select
0
1
SWE
reg.
Output enable
K
Impedance
control
ZQ
DQxn
(x: a to d,
n: 0 to 8)
Block Diagram (Late Write Mode)
Read
add. reg.
SAS
SA1 to SA18
Write
add. reg.
1
0
Memory array
(way0)
512k × 36
SAS
SA1 to SA18
compare
Match0
0
1
SWEx
1st reg.
SWEx
2nd reg.
Byte write
control
(x: a to d)
Din
reg.
Output
reg.
SS
reg.
SWE
reg.
Output enable
K
Impedance
control
ZQ
DQxn
(x: a to d,
n: 0 to 8)
Rev.3.00 Jan 13, 2006 page 3 of 29
HM64YLB36512 Series
Block Diagram (Register-Latch Mode)
Read
add. reg.
SA0 to SA18
Write
add. reg.
1
0
Memory array
(way0)
512k × 36
SA0 to SA18
compare
Match0
0
1
SWEx
1st reg.
SWEx
2nd reg.
Byte write
control
(x: a to d)
Din
reg.
Output
latch
SS
reg.
SWE
reg.
Output enable
K
Impedance
control
ZQ
DQxn
(x: a to d,
n: 0 to 8)
Rev.3.00 Jan 13, 2006 page 4 of 29
HM64YLB36512 Series
Pin Descriptions
Name I/O type
Descriptions
Notes
VDD
VSS
VDDQ
VREF
K
Supply
Supply
Supply
Supply
Input
Core power supply
Ground
Output power supply
Input reference, provides input reference voltage
Clock input, active high
K
SS
SWE
SAn
Input
Clock input, active low
Input
Synchronous chip select
Input
Synchronous write enable
Input
Synchronous address input
n: 1 to 18
(Late select mode)
(Late write mode)
n: 0 to 18
(Register-latch mode)
SAS
Input
Late select: Synchronous way select
Late write: Synchronous address input
SA0 in the register-latch
mode
SWEx
G
Input
Input
Input
Input
I/O
Synchronous byte write enables
Asynchronous output enable
Power down mode select
x: a to d
ZZ
ZQ
Output impedance control
Synchronous data input/output
1
DQxn
x: a to d
n: 0 to 8
M1, M2 Input
Output protocol mode select
Boundary scan test mode select
Boundary scan test clock
Boundary scan test data input
Boundary scan test data output
No connection
TMS
TCK
TDI
Input
Input
Input
Output
TDO
NC
M1
M2
VSS
Protocol
Notes
VSS
VSS
VDD
Synchronous register to register operation (late select mode)
Synchronous register to register operation (late write mode)
Synchronous register to latch operation (register-latch mode)
2
3
2
VDD
VSS
Notes: 1. ZQ is to be connected to VSS via a resistance RQ where 175 Ω ≤ RQ ≤ 300 Ω. If ZQ = VDDQ or open, output
buffer impedance will be maximum.
2. Mode control pins M1 and M2 are used to select different read protocols.
These mode control input pins are set at power-up and will not change the states during the SRAM operates.
Late select mode: Single clock, late SAS select, pipelined read protocol
Late write mode: Single clock, pipelined read protocol
Register-latch mode: Single differential clock register-latch mode protocol
3. Mode control pin M2 can be set to VDDQ instead of VDD
.
Rev.3.00 Jan 13, 2006 page 5 of 29
HM64YLB36512 Series
Truth Table
Late select mode
Late write mode
Register-latch mode
ZZ
SS
G
SWE
SWEa
SWEb
SWEc
SWEd
K
K
Operation
DQ (n)
DQ (n+1)
DQ (n)
DQ (n+1)
H
×
×
×
×
×
×
×
×
×
Sleep
mode
High-Z
High-Z
High-Z
High-Z
L
L
L
H
×
L
×
H
L
×
H
H
×
×
×
×
×
×
×
×
×
×
×
×
L-H H-L Dead
(not
×
High-Z
High-Z
High-Z
×
selected)
Dead
×
×
High-Z
×
High-Z
(dummy
read)
L-H H-L Read
×
DOUT
(a, b, c,
d)
DOUT
(a, b, c,
d)
×
0 to 8
0 to 8
L
L
×
L
L
L
L
L
L-H H-L Write
High-Z
DIN
High-Z
DIN
a, b, c, d
(a, b, c,
d)
(a, b, c,
d)
byte
0 to 8
0 to 8
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
×
×
×
×
×
×
×
×
L
L
L
L
L
L
L
L
H
L
L
H
L
L
L
L
L
L-H H-L Write
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DIN
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DIN
b, c, d
byte
(b, c, d)
0 to 8
(b, c, d)
0 to 8
L-H H-L Write
DIN
DIN
a, c, d
byte
(a, c, d)
0 to 8
(a, c, d)
0 to 8
L
H
L
L
L-H H-L Write
DIN
DIN
a, b, d
byte
(a, b, d)
0 to 8
(a, b, d)
0 to 8
L
L
H
L
L-H H-L Write
DIN
DIN
a, b, c
byte
(a, b, c)
0 to 8
(a, b, c)
0 to 8
H
L
H
H
L
L
L-H H-L Write
DIN
DIN
c, d byte
(c, d)
0 to 8
(c, d)
0 to 8
H
H
L
L
L-H H-L Write
a, d byte
DIN
DIN
(a, d)
0 to 8
(a, d)
0 to 8
L
H
H
L-H H-L Write
a, b byte
DIN
DIN
(a, b)
0 to 8
(a, b)
0 to 8
H
L
L-H H-L Write
b, c byte
DIN
DIN
(b, c)
0 to 8
(b, c)
0 to 8
L
L
L
L
L
L
L
L
×
×
×
×
L
L
L
L
H
H
H
L
H
H
L
H
L
L
H
H
H
L-H H-L Write
d byte
High-Z
High-Z
High-Z
High-Z
DIN (d)
0 to 8
High-Z
High-Z
High-Z
High-Z
DIN (d)
0 to 8
L-H H-L Write
c byte
DIN (c)
0 to 8
DIN (c)
0 to 8
H
H
L-H H-L Write
b byte
DIN (b)
0 to 8
DIN (b)
0 to 8
H
L-H H-L Write
a byte
DIN (a)
0 to 8
DIN (a)
0 to 8
Notes: 1. H: VIH, L: VIL, ×: VIH or VIL
2. SWE, SS, SWEa to SWEd, SA and SAS are sampled at the rising edge of K clock.
Rev.3.00 Jan 13, 2006 page 6 of 29
HM64YLB36512 Series
Programmable Impedance Output Drivers
Output buffer impedance can be programmed by terminating the ZQ pin to VSS through a precision resistor (RQ). The
value of RQ is five times the output impedance desired. The allowable value of RQ to guarantee impedance matching
with a tolerance of 15% is 250 Ω. If the status of ZQ pin is open, output impedance is maximum value. Maximum
impedance also occurs with ZQ connected to VDDQ. The impedance update of the output driver occurs when the SRAM
is in high-Z. Write and deselect operations will synchronously switch the SRAM into and out of high-Z, therefore will
trigger an update. At power up, the output buffer is in high-Z. It will take 4,096 cycles for the impedance to be
completely updated.
Absolute Maximum Ratings
Parameter
Symbol
VIN
Rating
−0.5 to VDDQ + 0.5
−0.5 to +3.13
−0.5 to +2.1
0 to +85
Unit
Notes
1, 4
Input voltage on any pin
Core supply voltage
Output supply voltage
Operating temperature
Storage temperature
Output short-circuit current
Latch up current
V
V
V
VDD
1
VDDQ
TOPR
TSTG
IOUT
1, 4
°C
−55 to +125
25
°C
mA
ILI
200
mA
Package junction to top thermal resistance
Package junction to board thermal resistance
θJ-top
θJ-board
6.5
°C/W
°C/W
5
5
12
Notes: 1. All voltage is referenced to VSS
.
2. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation
should be restricted the operation conditions. Exposure to higher voltages than recommended voltages for
extended periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the
tables after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN.
Remember, according to the absolute maximum ratings table, VDDQ is not to exceed 2.1 V, whatever the
instantaneous value of VDDQ
5. See figure below.
.
θJ-top
θJ-board
Thermocouple
Thermo grease
Teflon block
Thermocouple
Water
Water
Cold plate
SRAM
SRAM
Water
Water
Cold plate
JEDEC/2S2P BGA
Thermal board
JEDEC/2S2P
Thermal board
BGA
Thermo grease
Teflon block
Rev.3.00 Jan 13, 2006 page 7 of 29
HM64YLB36512 Series
Note: The following DC and AC specifications shown in the tables, this device is tested under the minimum transverse
air flow exceeding 500 linear feet per minute.
Recommended DC Operating Conditions
(Ta = 0 to +85°C)
Late select mode
Late write mode
Register-latch mode
Parameter
Symbol
VDD
Unit Notes
Min
2.38
Typ
Max
2.63
Min
2.38
Typ Max
Power supply
voltage: core
2.50
1.50
0.75
2.50
1.50
0.75
2.63
V
Power supply
voltage: I/O
VDDQ
VREF
1.40
0.60
1.60
0.90
1.40
0.70
1.60
0.80
V
Input reference
voltage: I/O
V
1
Input high voltage VIH
Input low voltage VIL
VREF + 0.10
−0.30
VDDQ + 0.30 VREF + 0.15
REF − 0.10 −0.50
VDDQ + 0.30 0.10
VDDQ + 0.50 V
REF − 0.15 V
VDDQ + 0.30 V
4
V
V
4
Clock differential VDIF
voltage
0.10
2, 3
Clock common
mode voltage
VCM
0.60
0.90
0.90
1.30
V
3
Notes: 1. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF
2. Minimum differential input voltage required for differential input clock operation.
3. See figure below.
.
4. VREF = 0.75 V (typ).
Differential Voltage / Common Mode Voltage
VDDQ
VDIF
VCM
VSS
Rev.3.00 Jan 13, 2006 page 8 of 29
HM64YLB36512 Series
DC Characteristics
(Ta = 0 to +85°C, VDD = 2.5 V ± 5%)
Late select mode
Late write mode
Register-latch
mode
Parameter
Symbol
ILI
Unit Notes
Min
Max
Min
Max
Input leakage current
2
5
2
5
µA
1
2
3
4
5
6
Output leakage current
ILO
µA
mA
mA
mA
W
Standby current
ISBZZ
IDD
150
450
200
2.3
150
350
200
2.3
VDD operating current, excluding output drivers
Quiescent active power supply current
IDD2
Maximum power dissipation, including output drivers P
Parameter
Output low voltage
Output high voltage
Symbol
VOL
Min
Typ
Max
Unit Notes
VSS
VSS + 0.4
V
7
VOH1
VOH2
RQ
IOL
VDDQ − 0.4
VDDQ
VDDQ
V
V
Ω
8
1.3
12
ZQ pin connect resistance
Output “Low” current
Output “High” current
250
(VDDQ/2) / {(RQ/5) − 15%}
(VDDQ/2) / {(RQ/5) + 15%}
mA 9, 11
IOH
(VDDQ/2) / {(RQ/5) + 15%}
(VDDQ/2) / {(RQ/5) − 15%}
mA 10, 11
Notes: 1. 0 ≤ VIN ≤ VDDQ for all input pins (except VREF, ZQ, M1, M2 pin)
2. 0 ≤ VOUT ≤ VDDQ, DQ in high-Z
3. All inputs (except clock) are held at either VIH or VIL, ZZ is held at VIH, IOUT = 0 mA. Specification is
guaranteed at +75°C junction temperature.
4. IOUT = 0 mA, read 50% / write 50%, VDD = VDD max, frequency = min. cycle
5. IOUT = 0 mA, read 50% / write 50%, VDD = VDD max, frequency = 3 MHz
6. Output drives a 12 pF load and switches every cycle. This parameter should be used by the SRAM designer
to determine electrical and package requirements for the SRAM device.
7. RQ = 250 Ω, IOL = 6.8 mA
8. RQ = 250 Ω, IOH = −6.8 mA
9. Measured at VOL = 1/2 VDDQ
10.Measured at VOH = 1/2 VDDQ
11.The total external capacitance of ZQ pin must be less than 7.5 pF.
12.RQ = 250 Ω, IOH = −100 µA
Rev.3.00 Jan 13, 2006 page 9 of 29
HM64YLB36512 Series
AC Characteristics
(Ta = 0 to +85°C, VDD = 2.5 V ± 5%)
Late Select Mode, Late Write Mode
HM64YLB36512BP
-28 -33
Parameter
CK clock cycle time
Symbol
tKHKH
Unit
ns
Notes
Min
2.8
Max
Min
3.3
Max
CK clock high width
tKHKL
tKLKH
tAVKH
tDVKH
tKHAX
tKHDX
tKHQV
tKHQX
tKHQX2
tKHQZ
tGLQX
tGLQV
tGHQZ
tZZR
1.2
1.2
0.3
0.3
0.6
0.6
1.3
1.3
0.3
0.3
0.6
0.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK clock low width
Address setup time
2
2
Data setup time
Address hold time
Data hold time
Clock high to output valid
Clock high to output hold
Clock high to output low-Z (SS control)
Clock high to output high-Z
Output enable low to output low-Z
Output enable low to output valid
Output enable high to output high-Z
Sleep mode recovery time
Sleep mode enable time
1.6
1.6
1
0.65
0.65
0.65
0.65
1, 6
1, 4, 6
1, 3, 6
1, 4, 6
1, 4
0.65 2.0
0.1
0.65 2.0
0.1
2.0
2.0
2.0
2.0
1, 3
20.0
20.0
5
tZZE
15.0
15.0 ns
1, 3, 5
Register-Latch Mode
HM64YLB36512BP
-33
Parameter
CK clock cycle time
Symbol
Unit
ns
Notes
Min
Max
tKHKH
tKHKL
tKLKH
tAVKH
tDVKH
tKHAX
tKHDX
tKHQV
tKLQV
tKLQX
tKLQX2
tKHQZ
tGLQX
tGLQV
tGHQZ
tZZR
6.5
1.2
1.2
0.4
0.4
1.0
1.0
1.7
0.5
0.5
0.5
0.5
0.1
CK clock high width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK clock low width
Address setup time
2
2
Data setup time
Address hold time
Data hold time
Clock high to output valid
Clock low to output valid
Clock low to output hold
Clock low to output low-Z (SS control)
Clock high to output high-Z
Output enable low to output low-Z
Output enable low to output valid
Output enable high to output high-Z
Sleep mode recovery time
Sleep mode enable time
Notes: 1. See figure in ”AC Test Conditions”.
5.5
2.3
1
1, 4, 6
1, 3, 6
1, 4, 6
1, 4
2.3
2.3
2.3
1, 3
20.0
5
tZZE
15.0
1, 3, 5
2. Parameters may be guaranteed by design, i.e., without tester guardband.
3. Transitions are measured ±50 mV of output high impedance from output low impedance.
4. Transitions are measured ±50 mV from steady state voltage.
5. When ZZ is switching, clock input K must be at the same logic level for the reliable operation.
6. Minimum value is verified by design and tested without guardband.
Rev.3.00 Jan 13, 2006 page 10 of 29
HM64YLB36512 Series
Timing Waveforms (Late Select Mode)
Read Cycle-1
tKHKH
tKHKL
tKLKH
K,
tAVKH
tKHAX
A1
A2
A3
A4
SA
A00
A10
A20
A30
SAS
tAVKH
tKHAX
tAVKH
tKHAX
tKHQX
Q0
DQ
Q1
Q2
tKHQV
Read Cycle-2 (SS Controlled)
tKHKH
tKHKL
tKLKH
K,
tKHAX
A1
A4
SA
A3
tAVKH
tKHAX
A10
A30
SAS
tAVKH
tKHAX
tAVKH
tKHAX
tKHQX2
tKHQZ
DQ
Q0
Q1
Q3
Notes: G, ZZ = VIL, x: a to d
Rev.3.00 Jan 13, 2006 page 11 of 29
HM64YLB36512 Series
Read Cycle-3 (G Controlled)
tKHKH
tKHKL
tKLKH
K,
tAVKH
tKHAX
A1
A2
A3
A4
SA
A00
A10
A20
A30
SAS
tAVKH
tKHAX
tAVKH
tKHAX
tGLQX
tGHQZ
Q1
DQ
Q0
Q3
tGLQV
Read operation (late select mode)
During read cycle, N-1 bits of address (SA) are registered during the first rising clock edge. The Nth bit of address
(SAS) is registered one clock edge later (the second edge). The setup time requirements for all address bits are the
same. SAS is used as the Nth bit of address on both read and write.
The internal array is read between this first edge and second edge, and data is captured in the output register at the
second clock edge. This requires the Nth address bit (SAS) to be used as the MUX select before the output register.
Alternatively, the Nth address bit can be registered, and used as the MUX select during the data drive cycle. In that
case, the output drive should still have a monotonic edge transition (no glitches due to logic switch).
Rev.3.00 Jan 13, 2006 page 12 of 29
HM64YLB36512 Series
Write Cycle
tKHKH
tKHKL tKLKH
K,
tAVKH
tAVKH
tAVKH
tAVKH
tAVKH
tKHAX
tKHAX
A1
A2
A3
A4
SA
SAS
A10
A20
A30
A40
tKHAX
tKHAX
tKHAX
tDVKH
tKHDX
D0
D1
D2
D3
DQ
Notes: ZZ = VIL, x: a to d
Write operation (late write and late select mode)
During writes, the write data follows the write address by one cycle. All N bits of address are presented during the
same cycle. Any subsequent read to this address should get the latest data. Because in the actual implementation the
data will be written into the SRAM array only after the next write address is received, a one-entry buffer is needed to
hold the write data and to allow bypassing of data from the write buffer to the output if there is a read of the same
address.
Rev.3.00 Jan 13, 2006 page 13 of 29
HM64YLB36512 Series
Read-Write Cycle
READ
DEAD
( control)
READ
tKHKH
WRITE
READ
WRITE
(
control)
tKHKL tKLKH
K,
tAVKH
tKHAX
tKHAX
tKHAX
tKHAX
tKHAX
SA
A1
A3
A4
A6
A7
tAVKH
tAVKH
tAVKH
tAVKH
SAS
A10
A30
A40
A60
tGHQZ tDVKH tKHDX
D3
tGLQV
tKHQV
DQ
Q0
Q1
Q4
D6
tKHQX
tGLQX
tKHQZ
Notes: ZZ = VIL, x: a to d
ZZ Control
tKHKH
tKHKL tKLKH
K,
tAVKH
tKHAX
SA
A1
tAVKH
tKHAX
tKHAX
tKHAX
SAS
A10
tAVKH
tAVKH
ZZ
Sleep active
Sleep off
Sleep active
Q1
DQ
tZZE
tZZR
Notes: G = VIL, x: a to d
When ZZ is switching, clock input K must be at the same logic level for the reliable operation.
Rev.3.00 Jan 13, 2006 page 14 of 29
HM64YLB36512 Series
Timing Waveforms (Late Write Mode)
Read Cycle-1
tKHKH
tKHKL
tKLKH
K,
tAVKH
tKHAX
A1
A2
A3
A4
SA
tAVKH
tKHAX
tAVKH
tKHAX
tKHQX
DQ
Q1
Q2
tKHQV
Read Cycle-2 (SS Controlled)
tKLKH
tKHKH
tKHKL
K,
tAVKH
tKHAX
A1
A3
A4
SA
tAVKH
tKHAX
tAVKH
tKHAX
tKHQX2
tKHQZ
Q0
Q1
Q3
DQ
Rev.3.00 Jan 13, 2006 page 15 of 29
HM64YLB36512 Series
Read Cycle-3 (G Controlled)
tKHKH
tKHKL tKLKH
K,
tAVKH
tKHAX
tKHAX
tKHAX
A1
A2
A3
A4
SA
tAVKH
tAVKH
tGLQX
tGHQZ
Q1
DQ
Q0
Q3
tGLQV
Read operation (late write mode)
During read cycle, the address is registered during the first rising clock edge, the internal array is read between this
first edge and second edge, and data is captured in the output register.
Rev.3.00 Jan 13, 2006 page 16 of 29
HM64YLB36512 Series
Write Cycle
tKHKH
tKHKL
tKLKH
K,
tAVKH
tAVKH
tAVKH
tAVKH
tKHAX
A1
A2
A3
A4
SA
tKHAX
tKHAX
tKHAX
tDVKH
tKHDX
D0
D1
D2
D3
DQ
Notes: ZZ = VIL, x: a to d
Write operation (late write and late select mode)
During write cycle, the write data follows the write address by one cycle. All N bits of address are presented during
the same cycle. Any subsequent read to this address should get the latest data. Because in the actual implementation
the data will be written into the SRAM array only after the next write address is received, a one-entry buffer is
needed to hold the write data and to allow bypassing of data from the write buffer to the output if there is a read of
the same address.
Rev.3.00 Jan 13, 2006 page 17 of 29
HM64YLB36512 Series
Read-Write Cycle
READ
DEAD
( control)
READ
tKHKH
WRITE
READ
WRITE
(
control)
tKHKL tKLKH
K,
tAVKH
tKHAX
tKHAX
tKHAX
tKHAX
SA
A1
A3
A4
A6
A7
tAVKH
tAVKH
tAVKH
tKHQV
tGHQZ tDVKH tKHDX
D3
tGLQV
DQ
Q0
Q1
Q4
D6
tGLQX
tKHQX
tKHQZ
Notes: ZZ = VIL, x: a to d
ZZ Control
tKHKL
tKLKH
tKHKH
tAVKH
K,
tKHAX
SA
A1
tAVKH
tKHAX
tAVKH
tKHAX
ZZ
DQ
Sleep active
Sleep off
Q1
Sleep active
tZZE
tZZR
Notes: G = VIL, x: a to d
When ZZ is switching, clock input K must be at the same logic level for the reliable operation.
Rev.3.00 Jan 13, 2006 page 18 of 29
HM64YLB36512 Series
Timing Waveforms (Register-Latch Mode)
Read Cycle-1
tKHKH
tKHKL
tKLKH
K,
tAVKH
tKHAX
tKHAX
tKHAX
A1
A2
A3
A4
SA
tAVKH
tAVKH
tKHQV
DQ
Q0
Q1
tKLQX
Q2
Q3
tKLQV
Note: ZZ = VIL
Read Cycle-2 (SS Controlled)
tKHKH
tKHKL
tKLKH
K,
tAVKH
tKHAX
A1
A4
SA
A3
tKHAX
tAVKH
tKHAX
tAVKH
tKLQX2
tKHQV
Q0
tKHQZ
Q1
Q3
DQ
Note: ZZ = VIL
Rev.3.00 Jan 13, 2006 page 19 of 29
HM64YLB36512 Series
Read Cycle-3 (G Controlled)
tKHKH
tKHKL
tKLKH
K,
tAVKH
tKHAX
A1
A2
A3
A4
SA
tAVKH
tKHAX
tAVKH
tKHAX
tGLQX
tGHQZ
Q2
DQ
Q0
Q1
Q3
tGLQV
Note: ZZ = VIL
Write Cycle
tKHKH
tKHKL
tKLKH
K,
tAVKH
tAVKH
tAVKH
tAVKH
tKHAX
A1
A2
A3
A4
SA
tKHAX
tKHAX
tKHAX
tDVKH
tKHDX
D0
D1
D2
D3
DQ
Note: ZZ = VIL
Rev.3.00 Jan 13, 2006 page 20 of 29
HM64YLB36512 Series
Read-Write Cycle-1
DEAD
WRITE
READ
tKHKH
READ
WRITE
READ
(
control)
tKHKL tKLKH
K,
tAVKH
tKHAX
tKHAX
tKHAX
tKHAX
SA
A1
A2
A3
A4
A6
A7
tAVKH
tAVKH
tAVKH
tGHQZ tDVKH tKHDX tGLQV
Q2
tKHQV
DQ
Q0
tKLQX
tKLQV
Q1
D6
D3
Q4
tGLQX
tKHQZ
Note: ZZ = VIL
Read-Write Cycle-2
DEAD
WRITE
READ
tKHKH
READ
WRITE
READ
(
control)
tKHKL tKLKH
K,
tAVKH
tKHAX
tKHAX
tKHAX
tKHAX
SA
A1
A2
A3
A4
A5
A6
A7
tAVKH
tAVKH
tAVKH
Low fixed
tKHQZ tDVKH tKHDX
tKHQV
DQ
Q0
tKLQX
tKLQV
Q1
Q2
D3
Q4
tKLQV tKHQZ
D6
Note: G, ZZ = VIL
During this period DQ pins are in the output state so that the input signal of opposite phase to the
outputs must not be applied.
Rev.3.00 Jan 13, 2006 page 21 of 29
HM64YLB36512 Series
ZZ Control
tKHKH
tKHKL tKLKH
K,
tAVKH
tAVKH
tAVKH
tKHAX
SA
A1
tKHAX
tKHAX
ZZ
Sleep off
Sleep active
Sleep active
Q1
DQ
tZZE
tZZR
Rev.3.00 Jan 13, 2006 page 22 of 29
HM64YLB36512 Series
Input Capacitance
(VDD = 2.5 V, VDDQ = 1.5 V, Ta = +25°C, f = 1 MHz)
Parameter
Input capacitance
Symbol
CIN
Min Max Unit
Pin name
Notes
1, 3
4
5
5
pF
pF
pF
SAn, SAS, SS, SWE, SWEx
Clock input capacitance
I/O capacitance
CCLK
CIO
K, K
DQxn
1, 2, 3
1, 3
Notes: 1. This parameter is sampled and not 100% tested.
2. Exclude G
3. Connect pins to GND, except VDD, VDDQ, and the measured pin.
AC Test Conditions
Conditions
Register-latch mode
Late select mode
Late write mode
Parameter
Symbol
Unit Note
Input and output timing reference levels VREF
0.75
0.75
V
Input signal amplitude
Input rise / fall time
Clock input timing reference level
VDIF to clock
VIL, VIH
tr, tf
0.25 to 1.25
0.5 (10% to 90%)
Differential cross point
0.75
0.25 to 1.25
0.5 (10% to 90%)
Differential cross point
0.75
V
ns
V
V
VCM to clock
0.75
1.10
Output loading conditions
See figure below
See figure below
Note: Parameters are tested with RQ = 250 Ω and VDDQ = 1.5 V.
Output Loading Conditions
50 Ω
16.7 Ω
16.7 Ω
50 Ω
50 Ω
0.75 V
16.7 Ω
5 pF
DQ
50 Ω
0.75 V
5 pF
0.75 V
Rev.3.00 Jan 13, 2006 page 23 of 29
HM64YLB36512 Series
Boundary Scan Test Access Port Operations
Overview
In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary scan test access
port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 - 1990. But does not implement all
of the functions required for 1149.1 compliance. The HM64YLB series contains a TAP controller. Instruction register,
boundary scans register, bypass register and ID register.
Test Access Port Pins
Symbol I/O
Name
TCK
TMS
TDI
Test clock
Test mode select
Test data in
TDO
Test data out
Note: This device does not have a TRST (TAP reset) pin. TRST is optional in IEEE 1149.1.
To disable the TAP, TCK must be connected to VSS. TDO should be left unconnected.
To test boundary scan, the ZZ pin needs to be kept below VREF − 0.4 V.
TAP DC Operating Characteristics
(Ta = 0 to +85°C)
Max Notes
Parameter
Boundary scan input high voltage
Symbol
Min
1.4 V
VIH
VIL
ILI
3.6 V
0.8 V
+10 µA
0.2 V
Boundary scan input low voltage
Boundary scan input leakage current
Boundary scan output low voltage
Boundary scan output high voltage
Boundary scan output leakage current
Notes: 1. 0 ≤ VIN ≤ 3.6 V for all logic input pins
2. IOL = 2 mA at VDD = 2.5 V.
−0.3 V
−10 µA
1
2
3
4
VOL
VOH
ILO
2.1 V
−5 µA
+5 µA
3. IOH = −2 mA at VDD = 2.5 V.
4. 0 ≤ VOUT ≤ VDD, TDO in high-Z
Rev.3.00 Jan 13, 2006 page 24 of 29
HM64YLB36512 Series
TAP AC Operating Characteristics
(Ta = 0 to +85°C)
Unit Note
Parameter
Test clock cycle time
Symbol
Min
Max
tTHTH
tTHTL
tTLTH
tMVTH
tTHMX
tCS
67
30
30
10
10
10
10
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test clock high pulse width
Test clock low pulse width
Test mode select setup
Test mode select hold
Capture setup
1
1
Capture hold
tCH
TDI valid to TCK high
TCK high to TDI don’t care
TCK low to TDO unknown
TCK low to TDO valid
tDVTH
tTHDX
tTLQX
tTLQV
20
Note: 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
TAP AC Test Conditions
(VDD = 2.5 V)
Temperature
0°C ≤ Ta ≤ +85°C
1.1 V
Input timing measurement reference level
Input pulse levels
0 to 2.5 V
Input rise/fall time
1.5 ns typical (10% to 90%)
1.25 V
Output timing measurement reference level
Test load termination supply voltage (VT)
Output load
1.25 V
See figure below
Boundary Scan AC Test Load
VT
DUT
50 Ω
Z0 = 50 Ω
TDO
Rev.3.00 Jan 13, 2006 page 25 of 29
HM64YLB36512 Series
TAP Controller Timing Diagram
tTHTH
tTHTL tTLTH
TCK
TMS
tMVTH tTHMX
tDVTH tTHDX
TDI
tTLQV
tTLQX
TDO
tCS tCH
RAM
ADDRESS
Test Access Port Registers
Register name
Instruction register
Length
Symbol
Note
3 bits
1 bit
IR [2:0]
BP
Bypass register
ID register
32 bits
70 bits
ID [31:0]
Boundary scan register
BS [70:1]
TAP Controller Instruction Set
IR2 IR1 IR0
Instruction
SAMPLE-Z
Operation
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Tristate all data drivers and capture the pad value
Tristate all data drivers and capture the pad value
IDCODE
SAMPLE-Z
BYPASS
SAMPLE
BYPASS
PRIVATE
BYPASS
Do not use. They are reserved for vendor use only
Note: This device does not perform EXTEST, INTEST or the preload portion of the PRELOAD command in IEEE
1149.1.
Rev.3.00 Jan 13, 2006 page 26 of 29
HM64YLB36512 Series
Boundary Scan Order (HM64YLB36512)
Bit #
Bump ID
Signal name
Bit #
Bump ID
Signal name
1
5R
4P
4T
6R
5T
7T
6P
7P
6N
7N
6M
6L
M2
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
3B
2B
3A
3C
2C
2A
2D
1D
2E
1E
2F
2G
1G
2H
1H
3G
4D
4E
4G
4H
4M
3L
SA12
SA15
SA13
SA11
SA16
SA14
DQc8
DQc7
DQc6
DQc5
DQc4
DQc2
DQc3
DQc0
DQc1
SWEc
ZQ
2
SAS/SA0
SA3
3
4
SA1
5
SA2
6
ZZ
7
DQa8
DQa7
DQa6
DQa5
DQa4
DQa2
DQa3
DQa0
DQa1
SWEa
K
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
7L
6K
7K
5L
4L
4K
4F
5G
7H
6H
7G
6G
6F
7E
6E
7D
6D
6A
6C
5C
5A
6B
5B
K
SS
NC
G
SWEb
DQb1
DQb0
DQb3
DQb2
DQb4
DQb5
DQb6
DQb7
DQb8
SA7
NC
SWE
SWEd
DQd1
DQd0
DQd3
DQd2
DQd4
DQd5
DQd6
DQd7
DQd8
SA18
SA10
SA17
M1
1K
2K
1L
2L
2M
1N
2N
1P
2P
3T
2R
4N
3R
SA8
SA4
SA6
SA9
SA5
Notes: 1. Bit#1 is the first scan bit to exit the chip.
2. Bit#2 is SAS in both the late select mode and the late write mode, or is SA0 in the register-latch mode.
3. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register
by a “Place Holder”. Place holder registers are internally connected to VSS
.
4. In boundary scan mode, differential input K and K are referenced to each other and must be at the opposite
logic levels for the reliable operation.
5. ZZ must remain VIL during boundary scan.
6. In boundary scan mode, ZQ must be driven to VDDQ or VSS supply rail to ensure consistent results.
7. M1 and M2 must be driven to VDD, VDDQ or VSS supply rail to ensure consistent results.
Rev.3.00 Jan 13, 2006 page 27 of 29
HM64YLB36512 Series
ID Register
Revision
number
(31:28)
Device density
and configuration
(27:18)
Vendor
definition
(17:12)
Vendor JEDEC
code (11:1)
Start
bit (0)
Part
HM64YLB36512
0000
0011100100
xxxxxx
00000000111
1
TAP Controller State Diagram
Test-logic-
1
reset
0
1
1
1
Run-test/
idle
Select-
DR-scan
Select-
IR-scan
0
0
0
1
1
Capture-DR
Capture-IR
0
0
Shift-DR
1
Shift-IR
1
0
0
0
0
1
1
Exit1-DR
0
Exit1-IR
0
Pause-DR
1
Pause-IR
1
0
0
Exit2-DR
Exit2-IR
1
1
Update-DR
Update-IR
1
0
1
0
Note: The value adjacent to each state transition in this figure represents the signal present at TMS at the
time of a rising edge at TCK.
No matter what the original state of the controller, it will enter Test-logic-reset when TMS is held high
for at least five rising edges of TCK.
Rev.3.00 Jan 13, 2006 page 28 of 29
HM64YLB36512 Series
Package Dimensions
HM64YLB36512BP Series (PRBG0119DB-A / Previous Code: BP-119E)
JEITA Package Code
P-BGA119-14x22-1.27
RENESAS Code
PRBG0119DB-A
Previous Code
BP-119E
MASS[Typ.]
1.1g
D
A
11.08
B
×4
v
y1
S
S
y
S
e
U
T
Dimension in Millimeters
Reference
Symbol
R
P
N
M
L
Min
Nom
14.00
22.00
Max
D
E
v
0.20
K
J
w
H
G
F
A
1.80
0.61
2.02
0.69
1.27
0.88
2.24
0.77
A1
e
E
D
C
B
A
b
0.82
0.94
0.30
0.20
0.35
x
y
y1
SD
SE
ZD
ZE
1
2
3
4
5
6
7
φ b
φ
×
M
S
A
S
B
φ
0.15
M
Rev.3.00 Jan 13, 2006 page 29 of 29
Revision History
HM64YLB36512 Series Data Sheet
Description
Summary
Rev.
0.0
Date
Page
May. 6, 2002
Aug. 30, 2002
Initial issue
0.1
5
Truth Table
Deletion of Notes3
Input Capacitance
Addition of Notes3
18
6
1.0
Feb. 7, 2003
Jul. 19, 2005
Change of
Programmable Impedance
Output Drivers
2.00
Change format issued by Renesas Technology Corp.
The Former HM64YLB36512BP-33 and the former HM64YLB36514BP-6H are
integrated into the new HM64YLB36512BP-33
Change of Features, adding register-latch mode
Ordering Information
1
2
Addition of Modes
Addition of Renesas package codes
Pin Arrangement
2
4P: SAS to SAS/SA0
Addition of Note
4
5
Addition of Block Diagram in register-latch mode
Pin Descriptions
Change of SAn, SAS Notes, adding register-latch mode
Addition of M1, M2 Protocol in register-latch mode
Change of Notes2, adding register-latch mode
Truth Table: Addition of DQ (n), DQ (n+1) in register-latch mode
Change of
6
7
Programmable Impedance
Output Drivers
8
Recommended DC Operating Conditions
Addition of the values in register-latch mode
DC Characteristics: Addition of the values in register-latch mode
AC Characteristics: Addition of the table in register-latch mode
9
10
19-22 Addition of Timing Waveforms in register-latch mode
23
27
AC Test Conditions: Addition of the values in register-latch mode
Boundary Scan Order
Bit#2: SAS to SAS/SA0
Notes2-6 to Notes3-7
Addition of Notes2
29
9
Package Dimensions
Addition of Renesas package codes
Changed to Renesas formats
3.00
Jan. 13, 2006
DC Characteristics: VOH to VOH1, addition of VOH2
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Renesas Technology (Shanghai) Co., Ltd.
Unit 205, AZIA Center, No.133 Yincheng Rd (n), Pudong District, Shanghai 200120, China
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
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