HM65W8512LTT-15 [RENESAS]
512KX8 PSEUDO STATIC RAM, 150ns, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32;
| 型号： | HM65W8512LTT-15 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 512KX8 PSEUDO STATIC RAM, 150ns, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32 光电二极管 |
| 文件： | 总20页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM65W8512 Series
4 M PSRAM (512-kword × 8-bit)
2 k Refresh
ADE-203-289C(Z)
Rev. 3.0
Nov. 1997
Description
The Hitachi HM65W8512 is a CMOS pseudo static RAM organized 512-kword × 8bit. It realizes higher
density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS process
technology.
It offers low power data retention by self refresh mode. It also offers easy non multiplexed address
interface and easy refresh functions. HM65W8512 is suitable for handy systems which work with battery
back-up systems.
The device is packaged in a small 525-mil SOP (460-mil body SOP) or a 400 mil TSOP TYPE II.
Features
•
•
Single 3.3 V (±0.3V)
High speed
Access time
CE access time: 120/150 ns (max)
Cycle time
Random read/write cycle time:
190/230 ns (min)
•
Low power
Active: 100 mW (typ)
Standby: 85 µW (typ)
Directly TTL/CMOS compatible
All inputs and outputs
Simple address configuration
Non multiplexed address
Refresh cycle
•
•
•
2048 refresh cycles: 32 ms
HM65W8512 Series
•
Easy refresh functions
Address refresh
Automatic refresh
Self refresh
Ordering Information
Type No.
Access time
Package
HM65W8512LFP-12
HM65W8512LFP-15
120 ns
150 ns
525-mil 32-pin plastic SOP (FP-32D)
HM65W8512LFP-12V
HM65W8512LFP-15V
120 ns
150 ns
HM65W8512LTT-12
HM65W8512LTT-15
120 ns
150 ns
400-mil 32-pin plastic TSOP (TTP-32D)
400-mil 32-pin plastic TSOP (TTP-32DR)
HM65W8512LTT-12V
HM65W8512LTT-15V
120 ns
150 ns
HM65W8512LRR-12
HM65W8512LRR-15
120 ns
150 ns
HM65W8512LRR-12
HM65W8512LRR-15V
120 ns
150 ns
2
HM65W8512 Series
Pin Arrangement
HM65W8512FP Series
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A18
A16
A14
A12
A7
2
A15
A17
WE
3
4
5
A13
A8
6
A6
7
A9
A5
8
A11
OE/RFSH
A10
CE
A4
9
A3
10
11
12
13
14
15
16
A2
A1
I/O7
I/O6
I/O5
I/O4
I/O3
A0
I/O0
I/O1
I/O2
VSS
(Top view)
HM65W8512TT Series
A18
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A16
A14
A12
A7
2
A15
A17
WE
3
4
5
A13
A8
A9
A6
6
A5
7
A4
8
A11
OE/RFSH
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A3
9
A2
10
11
12
13
14
15
16
A1
A0
I/O0
I/O1
I/O2
VSS
(Top view)
3
HM65W8512 Series
Pin Arrangement (cont.)
HM65W8512RR Series
VCC
A15
A18
A16
A14
A12
A7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
A17
3
WE
4
A13
5
A8
A6
6
A9
A5
7
A11
A4
8
OE/RFSH
A10
A3
9
A2
10
11
12
13
14
15
16
CE
A1
I/O7
I/O6
I/O5
I/O4
I/O3
A0
I/O0
I/O1
I/O2
VSS
(Top view)
Pin Description
Pin name
A0 to A18
I/O0 to I/O7
CE
Function
Address
Input/ output
Chip enable
OE/RFSH
WE
Output enable/Refresh
Write enable
VCC
Power supply
Ground
VSS
4
HM65W8512 Series
Block Diagram
A0
Address
Latch
Control
Row
Decoder
Memory Matrix
(2048 × 256) × 8
A10
Column I/O
Input
Data
Control
I/O 0
I/O 7
Column Decoder
Address Latch Control
A18
A11
Refresh
Control
CE
OE/RFSH
Timing Pulse Gen.
Read Write Control
WE
Pin Functions
CE: Chip Enable (Input)
CE is a basic clock. RAM is active when CE is low, and is on standby when CE is high.
A0 to A18: Address Inputs (Input)
A0 to A10 are row addresses and A11 to A18 are column addresses. The entire addresses A0 to A18
are fetched into RAM by the falling edge of CE.
OE/RFSH: Output Enable/Refresh (Input)
This pin has two functions. Basically it works as OE when CE is low, and as RFSH when CE is high
(in standby mode). After a read or write cycle finishes, refresh does not start if CE goes high while
OE/RFSH is held low. In order to start a refresh in standby mode, OE/RFSH must go high to reset the
refresh circuits of the RAM. After the refresh circuits are reset, the refresh starts when OE/RFSH goes
low.
I/O0 to I/O7: Input/Output (Inputs and Outputs) These pins are data I/O pins.
5
HM65W8512 Series
WE: Write Enable (Input)
RAM is in write mode when WE is low, and is in read mode when WE is high. I/O data is fetched into
RAM by the rising edge of WE or CE (earlier timing) and the data is written into memory cells.
Refresh
There are three refresh modes : address refresh, automatic refresh and self refresh.
(1) Address refresh: Data is refreshed by accessing all 2048 row addresses every 32 ms. A read is one
method of accessing those addresses. Each row address (2048 addresses of A0 to A10) must be read at
least once every 32 ms. In address refresh mode, OE/RFSH can remain high. In this case, the I/O pins
remain at high impedance, but the refresh is done within RAM.
(2) Automatic refresh: Instead of address refresh, automatic refresh can be used. RAM goes to automatic
refresh mode if OE/RFSH falls while CE is high and it remains low for at least tFAP. One automatic
refresh cycle is executed by one low pulse of OE/RFSH. It is not necessary to input the refresh
address from outside since it is generated internally by an on-chip address counter. 2048 automatic
refresh cycles must be done every 32 ms.
(3) Self refresh: Self refresh mode is suitable for data retention by battery. In standby mode, a self refresh
starts automatically when OE/RFSH stays low for more than 8 µs. Refresh addresses are automatically
specified by the on-chip address counter, and the refresh period is determined by the on-chip timer.
Automatic refresh and self refresh are distinguished from each other by the width of the OE/RFSH low
pulse in standby mode. If the OE/RFSH low pulse is wider than 8 µs, RAM becomes into self refresh
mode; if the OE/RFSH low pulse is less than 8 µs, it is recognized as an automatic refresh instruction.
At the end of self refresh, refresh reset time (tRFS) is required to reset the internal self refresh operation of
the RAM. During tRFS, CE and OE/RFSH must be kept high. If auto refresh follows self refresh, low
transition of OE/RFSH at the beginning of automatic refresh must not occur during tRFS period.
Notes on Using the HM65W8512
Since pseudo static RAM consists of dynamic circuits like DRAM, its clock pins are more noise-sensitive
than conventional SRAM’s.
(1) If a short CE pulse of a width less than tCE min is applied to RAM, an incomplete read occurs and
stored data may be destroyed. Make sure that CE low pulses of less than tCE min are inhibited. Note
that a 10 ns CE low pulse may sometimes occur owing to the gate delay on the board if the CE signal is
generated by the decoding of higher address signals on the board. Avoid these short pulses.
(2) OE/RFSH works as refresh control in standby mode. A short OE/RFSH low pulse may cause an
incomplete refresh that will destroy data. Make sure that OE/RFSH low pulse of less than tFAP min are
also inhibited.
(3) tOHC and tOCD are the timing specs which distinguish the OE function of OE/RFSH from the RFSH
function. The tOHC and tOCD specs must be strictly maintained.
6
HM65W8512 Series
(4) Start the HM65W8512 operating by executing at least eight initial cycles (dummy cycles) at least 100
µs after the power voltage reaches 3.0 V-3.6 V after power-on.
Function Table
CE
L
OE/RFSH
WE
H
I/O pin
Dout
Mode
Read
Write
L
L
X
H
L
L
High-Z
High-Z
High-Z
High-Z
L
H
—
H
H
X
Refresh
Standby
H
X
Note: X means H or L.
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Terminal voltage with respect to VSS
Power dissipation
–0.5 to +6.0
1.0
PT
W
Operating temperature
Storage temperature
Topr
Tstg
Tbias
0 to +70
°C
°C
°C
–55 to +125
–10 to +85
Storage temperature under bias
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
3.0
0
Typ
3.3
0
Max
3.6
0
Unit
V
Note
Supply voltage
VSS
V
Input voltage
VIH
2.4
–0.5
—
5.6
0.8
V
VIL
—
V
1
Note: 1. VIL min = –1.2 V for pulse width 30 ns
7
HM65W8512 Series
DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
Parameter
Symbol Min Typ Max Unit Test conditions
Operating power supply current ICC1
Standby power supply current ISB1
ISB2
—
—
—
—
—
30
—
15
—
25
50
0.8
30
0.8
50
mA
mA
µA
II/O = 0 mA
tcyc = min
CE = VIH , Vin ≥ 0 V
OE/RFSH = VIH
CE ≥ VCC – 0.2 V, Vin ≥ 0 V,
OE/RFSH ≥ VCC – 0.2 V
Operating power supply current ICC2
in self refresh mode
mA
µA
CE = VIH , Vin ≥ 0 V,
OE/RFSH = VIL
ICC3
CE ≥ VCC – 0.2 V, Vin ≥ 0 V,
OE/RFSH ≤ 0.2 V
Input leakage current
Output leakage current
ILI
–5
–5
—
—
5
5
µA
µA
VCC = 3.6 V, Vin = VSS to VCC
ILO
OE/RFSH = VIH
VI/O = VSS to VCC
Output voltage
VOL
VOH
—
—
—
—
—
0.1
0.4
—
V
V
V
V
IOL = 100 µA
IOL = 2 mA
—
2.9
2.4
IOH = –100 µA
IOH = –2 mA
—
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Cin
Typ
Max
Unit
pF
Test conditions
Input capacitance*1
Input /output capacitance*1
—
—
8
Vin = 0 V
VI/O = 0 V
CI/O
10
pF
Note : This parameter is sampled and not 100% tested.
8
HM65W8512 Series
AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
•
•
•
•
•
Input pulse levels: 0.6 V, 2.4 V
Input rise and fall time: 5 ns
Timing measurement level: 1.5 V
Reference levels: VOH = 2.1 V, VOL = 0.9 V
Output load: CL (50 pF) (Including scope and jig)
HM65W8512-12 HM65W8512-15
Parameter
Symbol
tRC
Min
190
—
250
—
0
Max
—
Min
230
—
290
—
0
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Random read or write cycle time
Chip enable access time
Read-modify- write cycle time
Output enable access time
Chip disable to output in high-Z
Chip enable to output in low-Z
Output disable to output in high-Z
Output enable to output in low-Z
Chip enable pulse width
Chip enable precharge time
Address setup time
tCEA
tRWC
tOEA
tCHZ
tCLZ
tOHZ
tOLZ
tCE
120
—
150
—
60
30
—
80
30
—
1, 2
2
20
—
0
20
—
0
30
—
30
—
1, 2
2
120
70
0
10000
—
150
80
0
10000
—
tP
tAS
—
—
Address hold time
tAH
30
0
—
30
0
—
Read command setup time
Read command hold time
Write command pulse width
Chip enable to end of write
tRCS
tRCH
tWP
—
—
0
—
0
—
35
120
0
—
35
150
0
—
tCW
—
—
Chip enable to output enable delay
time
tOCD
—
—
Output enable hold time
tOHC
15
—
15
—
ns
9
HM65W8512 Series
AC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.) (cont.)
HM65W8512-12 HM65W8512-15
Parameter
Symbol
tDW
Min
30
0
Max
—
Min
30
0
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Data in to end of write
Data in hold time for write
Output active from end of write
Write to output in high-Z
Transition time (rise and fall)
Refresh command delay time
Refresh precharge time
tDH
—
—
tOW
5
—
5
—
2
tWHZ
tT
tRFD
tFP
—
3
30
—
3
30
1, 2
6
50
50
70
40
80
—
80
40
80
—
—
—
Refresh command pulse width for
automatic refresh
tFAP
8000
8000
Automatic refresh cycle time
tFC
190
8
—
—
230
8
—
—
ns
Refresh command pulse width for self tFAS
refresh
µs
Refresh reset time from self refresh
Refresh period
tRFS
tREF
600
—
—
600
—
—
ns
9
32
32
ms
2048
cycle
Notes: 1. tCHZ, tOHZ, tWHZ are defined as the time at which the output achieves the open circuit condition.
2. tCHZ, tCLZ, tOHZ, tOLZ, tWHZ and tOW are sampled under the condition of tT = 5 ns and not 100% tested.
3. A write occurs during the overlap of low CE and low WE. Write end is defined at the earlier of
WE going high or CE going high.
4. If the CE low transition occurs simultaneously with or from the WE low transition, the output
buffers remain in high impedance state.
5. In write cycle, OE or WE must disable output buffers prior to applying data to the device and at
the end of write cycle data inputs must be floated prior to OE or WE turning on output buffers.
During this period, I/O pins are in the output state, therefore the input signals of opposite phase
to the outputs must not be applied.
6. Transition time tT is measured between VIH (min) and VIL (max). VIH (min) and VIL (max) are
reference levels for measuring timing of input signals.
7. After power-up, pause for more than 100 µs and execute at least 8 initialization cycles.
8. 2048 cycles of burst refresh or the first cycle of distributed automatic refresh must be executed
within 15 µs after self refresh, in order to meet the refresh specification of 32 ms and 2048
cycles.
9. At the end of self refresh, refresh reset time (tRFS) is required to reset the internal self refresh
operation of the RAM. During tRFS, CE and OE/RFSH must be kept high. If automatic refresh
follows self refresh, low transition of OE/RFSH at the beginning of automatic refresh must not
occur during tRFS period.
10
HM65W8512 Series
Timing Waveform
Read Cycle
t
RC
t
CE
CE
t
P
t
t
AH
AS
Address
A0 to A18
Valid
t
WE
OE/RFSH
Dout
OHC
t
t
t
CEA
RCH
RCS
t
OEA
t
CHZ
t
OLZ
t
OHZ
Valid data out
11
HM65W8512 Series
Write Cycle (1) (OE high)
t
RC
t
CE
CE
t
P
t
t
AH
AS
Address
A0 to A18
Valid
t
CW
t
WP
WE
OE/RFSH
Din
t
OCD
t
t
DH
DW
Valid
Data in
t
t
WHZ
OLZ
t
CLZ
t
OHZ
t
OW
Dout
12
HM65W8512 Series
Write Cycle (2) (OE low)
t
RC
t
CE
CE
t
P
t
t
AH
AS
Address
A0 to A18
Valid
t
DH
t
CW
t
WP
WE
OE/RFSH
Din
t
OHC
t
t
DH
DW
Valid data in
t
WHZ
t
CLZ
Dout
13
HM65W8512 Series
Read-Modify-Write Cycle
t
RWC
t
CE
t
P
CE
t
t
AH
AS
Address
A0 to A18
Valid
t
RCH
t
RCS
t
CW
t
WP
t
CEA
WE
OE/RFSH
Din
t
t
OHC
OCD
t
OEA
t
t
t
DH
DW
Valid data in
t
t
CHZ
OLZ
t
OHZ
OW
t
CLZ
Valid
data
out
Dout
Automatic Refresh Cycle
CE
t
t
t
RFD
FC
FC
t
t
FAP
t
t
FP
FAP
FP
OE/RFSH
14
HM65W8512 Series
Self Refresh Cycle
CE
t
t
RFS
RFD
t
t
FAS
FP
OE/RFSH
15
HM65W8512 Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only for V-version.
Parameter
Symbol
VDR
Min
2.0
—
Typ
—
Max
3.6
25
Unit
V
Test conditions
VCC for data retention
Self refresh current
ICCDR
—
µA
VCC = 2.0 V,
CE ≥ VCC – 0.2 V
OE/RFSH ≤ 0.2
Vin ≥ 0 V
—
—
50
µA
VCC = 3.6 V,
CE ≥ VCC – 0.2 V
OE/RFSH ≤ 0.2
Vin ≥ 0 V
Refresh setup time
tFS
tFR
0
5
—
—
—
—
ns
Operation recovery time
ms
Low VCC Data Retention Timing Waveform
Data Retention mode
t
t
F
R
V
3.0V
1.5V
1.5V
CC
V
DR
Vcc-0.2V
CE
CE
t
RFD
t
FR
(in read/
RFS
t
FP
t
t
write mode)
FS
t
FAS
OE/RFSH
0.2V
OE/RFSH
(in automatic
refresh mode)
16
HM65W8512 Series
Package Dimensions
HM65W8512FP Series (FP-32D)
Unit: mm
20.45
20.95 Max
17
32
14.14 ± 0.30
1.42
1
16
1.0 Max
0 – 8 °
0.10
M
0.8
1.27
+ 0.10
– 0.05
0.40
0.15
HM65W8512TT Series (TTP-32D)
Unit: mm
20.95
21.35 Max
32
17
16
1
1.27
M
0.21
11.76 ± 0.2
0.40 ± 0.10
1.15 Max
0 – 5°
0.10
0.50 ± 0.10
17
HM65W8512 Series
Package Dimensions (cont.)
HM65W8512RR Series (TTP-32DR)
Unit: mm
20.95
21.35 Max
1
16
17
32
1.27
M
0.21
11.76 ± 0.2
0.40 ± 0.10
1.15 Max
0 – 5°
0.10
0.50 ± 0.10
18
HM65W8512 Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Tel: 415-589-8300
Fax: 535-1533
Fax: 415-583-4207
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Berkshire SL6 8YA
United Kingdom
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 0628-585000
Fax: 0628-778322
Tel: 27359218
Fax: 27306071
19
HM65W8512 Series
Revision Record
Rev. Date
3.0 Nov. 1997
Contents of Modification
Change of Subtitle
Drawn by Approved by
20
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