HM6AEB9405BP40 [RENESAS]
4MX9 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, 1 MM PITCH, PLASTIC, FBGA-165;
| 型号： | HM6AEB9405BP40 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4MX9 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, 1 MM PITCH, PLASTIC, FBGA-165 双倍数据速率 静态存储器 |
| 文件： | 总24页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM66AEB36105/HM66AEB18205
HM66AEB9405
36-Mbit DDR II SRAM Separate I/O
2-word Burst
REJ03C0047-0100
Rev.1.00
Sep.06.2006
Description
The HM66AEB36105 is a 1,048,576-word by 36-bit, the HM66AEB18205 is a 2,097,152-word by 18-bit, and the
HM66AEB9405 is a 4,194,304-word by 9-bit synchronous double data rate static RAM fabricated with advanced
CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry
and a burst counter. All input registers controlled by an input clock pair (K and K) and are latched on the positive edge
of K and K. These products are suitable for applications which require synchronous operation, high speed, low voltage,
high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
Features
•
•
•
•
•
•
•
•
•
1.8 V ± 0.1 V power supply for core (VDD
1.4 V to VDD power supply for I/O (VDDQ
DLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports
DDR read or write operation initiated each cycle
Separate data input/output bus
Two-tick burst for low DDR transaction size
Two input clocks (K and K) for precise DDR timing at clock rising edges only
Two output clocks (C and C) for precise flight time and clock skew matching-clock and data delivered together to
receiving device
)
)
•
•
•
•
•
•
Internally self-timed write control
Clock-stop capability with µs restart
User programmable impedance output
Fast clock cycle time: 3.0 ns (333 MHz)/3.3 ns (300 MHz)/4.0 ns (250 MHz)/5.0 ns (200 MHz)/6.0 ns (167 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
Rev.1.00 Sep 06, 2006 page 1 of 20
HM66AEB36105/18205/9405
Part No. Information
Catalogue Part No.
Organi-
zation
Cycle
time
Clock
frequency
Ordering Part No.
Package
HM66AEB36105BP-30
HM66AEB36105BP-33
HM66AEB36105BP-40
HM66AEB36105BP-50
HM66AEB36105BP-60
HM6AEB36105BP30
HM6AEB36105BP33
HM6AEB36105BP40
HM6AEB36105BPL50
HM6AEB36105BPL60
1-M word
× 36-bit
3.0 ns
3.3 ns
4.0 ns
5.0 ns
6.0 ns
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
Plastic FBGA
165-pin
PLBG0165FB-A
(BP-165A)
HM66AEB18205BP-30
HM66AEB18205BP-33
HM66AEB18205BP-40
HM66AEB18205BP-50
HM66AEB18205BP-60
HM6AEB18205BP30
HM6AEB18205BP33
HM6AEB18205BP40
HM6AEB18205BPL50
HM6AEB18205BPL60
2-M word
× 18-bit
3.0 ns
3.3 ns
4.0 ns
5.0 ns
6.0 ns
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
HM66AEB9405BP-30
HM66AEB9405BP-33
HM66AEB9405BP-40
HM66AEB9405BP-50
HM66AEB9405BP-60
HM6AEB9405BP30
HM6AEB9405BP33
HM6AEB9405BP40
HM6AEB9405BPL50
HM6AEB9405BPL60
4-M word
× 9-bit
3.0 ns
3.3 ns
4.0 ns
5.0 ns
6.0 ns
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
Pin Arrangement (165PIN-BGA)
HM66AEB36105
1
2
3
4
5
6
7
8
9
10
NC
11
A
B
C
D
E
F
CQ
VSS
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
NC
R/W
SA
BW2
BW3
SA
K
K
BW1
BW0
SA
LD
SA
SA
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
SA
Q17
Q7
VSS
SA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
D15
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
Q14
D13
VREF
Q4
G
H
J
K
L
D3
Q11
Q1
M
N
P
R
VSS
VSS
D9
SA
SA
SA
SA
D0
SA
SA
C
SA
SA
SA
TMS
(Top view)
Rev.1.00 Sep 06, 2006 page 2 of 20
HM66AEB36105/18205/9405
HM66AEB18205
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
6
7
8
9
SA
10
NC
NC
Q7
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
VSS
Q9
SA
R/W
SA
BW1
NC
K
K
NC
LD
SA
D9
BW0
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
NC
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
SA
VSS
SA
SA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
D11
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
NC
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
Q12
D13
VREF
NC
NC
NC
VREF
Q4
G
H
J
K
L
NC
D3
Q15
NC
NC
Q1
M
N
P
R
D17
NC
VSS
VSS
NC
D0
SA
SA
SA
SA
TCK
SA
SA
C
SA
SA
TMS
(Top view)
HM66AEB9405
1
2
VSS
NC
NC
D5
3
SA
NC
NC
NC
Q5
NC
Q6
VDDQ
NC
NC
D7
4
5
6
7
8
9
SA
10
SA
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
A
B
C
D
E
F
CQ
NC
R/W
SA
NC
NC
SA
K
K
NC
BW
SA
LD
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
NC
NC
NC
D3
NC
VSS
SA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
NC
NC
NC
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
NC
NC
VREF
Q2
G
H
J
NC
DOFF
NC
VREF
NC
NC
Q7
K
L
NC
NC
NC
NC
NC
D0
NC
M
N
P
R
NC
NC
D8
NC
NC
Q8
SA
NC
VSS
VSS
NC
NC
TCK
SA
SA
SA
SA
TDO
SA
SA
C
SA
SA
TMS
(Top view)
Notes on Usage
•
•
•
Power-on initialization cycles are required for all operations, including JTAG functions, to become normal.
Clock recovery initialization cycles are required for read/write operations to become normal.
Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ).
The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance
matching with a tolerance of 10% is 250 Ω typical. The total external capacitance of ZQ ball must be less than 7.5
pF.
Rev.1.00 Sep 06, 2006 page 3 of 20
HM66AEB36105/18205/9405
Pin Descriptions
Name
SA
I/O type
Descriptions
Input
Synchronous address inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. All transactions operate on a burst-of-two words (one clock period of
bus activity). These inputs are ignored when device is deselected.
LD
Input
Input
Input
Synchronous load: This input is brought low when a bus cycle sequence is to be defined. This
definition includes address and READ / WRITE direction. All transactions operate on a burst-of-
two data (one clock period of bus activity).
R/W
Synchronous read / write Input: When LD is low, this input designates the access type (READ
when R/W is high, WRITE when R/W is low) for the loaded address. R/W must meet the setup and
hold times around the rising edge of K.
BW
BWn
Synchronous byte writes: When low, these inputs cause their respective byte to be registered and
written during WRITE cycles. These signals must meet setup and hold times around the rising
edges of K and K for each of the two rising edges comprising the WRITE cycle. See Byte Write
Truth Table for signal to data relationship.
K, K
C, C
Input
Input
Input clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K. K is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising
edges. These balls cannot remain VREF level.
Output clock: This clock pair provides a user-controlled means of tuning device output data. The
rising edge of C is used as the output timing reference for first output data. The rising edge of C is
used as the output timing reference for second output data. Ideally, C is 180 degrees out of phase
with C. C and C may be tied high to force the use of K and K as the output reference clocks
instead of having to provide C and C clocks. If tied high, C and C must remain high and not to be
toggled during device operation. These balls cannot remain VREF level.
DOFF
Input
Input
DLL disable: When low, this input causes the DLL to be bypassed for stable, low frequency
operation.
ZQ
Output impedance matching input: This input is used to tune the device outputs to the system data
bus impedance. Q and CQ output impedance are set to 0.2 × RQ, where RQ is a resistor from this
ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance
mode. This ball cannot be connected directly to VSS or left unconnected.
TMS
TDI
Input
Input
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the JTAG
function is not used in the circuit.
TCK
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG function is not
used in the circuit.
D0 to Dn Input
Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K
and K during WRITE operations. See Pin Arrangement figures for ball site location of individual
signals.
The ×9 device uses D0 to D8. Remaining signals are NC.
The ×18 device uses D0 to D17. Remaining signals are NC.
The ×36 device uses D0 to D35.
CQ, CQ
Output Synchronous echo clock outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as a data valid indication. These signals run freely and
do not stop when Q tri-states.
TDO
Output IEEE 1149.1 test output: 1.8 V I/O level.
Q0 to Qn Output Synchronous data outputs: Output data is synchronized to the respective C and C, or to the
respective K and K if C and C are tied high. This bus operates in response to R/W commands.
See Pin Arrangement figures for ball site location of individual signals.
The ×9 device uses Q0 to Q8. Remaining signals are NC.
The ×18 device uses Q0 to Q17. Remaining signals are NC.
The ×36 device uses Q0 to Q35.
VDD
Supply Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.
VDDQ
Supply Power supply: Isolated output buffer supply. Nominally 1.5 V. 1.8 V is also permissible. See DC
Characteristics and Operating Conditions for range.
Rev.1.00 Sep 06, 2006 page 4 of 20
HM66AEB36105/18205/9405
Name
VSS
I/O type
Descriptions
Supply Power supply: Ground
VREF
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise
margin. Provides a reference voltage for the HSTL input buffers.
NC
No connect: These signals are internally connected. These signals may be connected to ground
to improve package heat dissipation.
Note: 1. All power supply and ground balls must be connected for proper operation of the device.
Block Diagram
HM66AEB36105
19
Address
Address
19
R/
R/
registry
and logic
K
ZQ
36
2
Q0 to Q35
CQ,
Data
registry
and logic
72
72
72
Memory
array
MUX
36
D0 to D35
K
K
C
C,
or
K,
HM66AEB18205
20
Address
Address
registry
20
R/
and logic
K
ZQ
R/
18
2
Q0 to Q17
CQ,
Data
registry
and logic
18
36
36
36
D0 to D17
Memory
array
MUX
K
K
C
C,
or
K,
Rev.1.00 Sep 06, 2006 page 5 of 20
HM66AEB36105/18205/9405
HM66AEB9405
21
Address
Address
registry
21
R/
R/
and logic
K
ZQ
9
2
Q0 to Q8
CQ,
Data
registry
and logic
9
18
18
18
D0 to D8
Memory
array
MUX
K
K
C
C,
or
K,
Truth Table
Operation
K
LD
L
R/W
L
D or Q
WRITE cycle
L→H
Data in
Input
Load address, input write data on
D(A+0)
D(A+1)
consecutive K and K rising edges
data
Input
clock
K(t+1)↑
K(t+1)↑
READ cycle
L→H
L
H
Data out
Load address, read data on
consecutive C and C rising edges
Output
data
Q(A+0)
Q(A+1)
Output
clock
C(t+1)↑
C(t+2)↑
NOP (No operation)
L→H
H
×
×
D = × or Q = High-Z
STANDBY (Clock stopped)
Stopped
×
Previous state
Notes: 1. H: high level, L: low level, ×: don’t care, ↑: rising edge.
2. Data inputs are registered at K and K rising edges. Data outputs are delivered at C and C rising edges,
except if C and C are high, then data outputs are delivered at K and K rising edges.
3. LD and R/W must meet setup/hold times around the rising edges (low to high) of K and are registered at the
rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. When clocks are stopped, the following cases are recommended; the case of K = low, K = high, C = low and
C = high, or the case of K = high, K = low, C = high and C = low. This condition is not essential, but permits
most rapid restart by overcoming transmission line charging symmetrically.
Rev.1.00 Sep 06, 2006 page 6 of 20
HM66AEB36105/18205/9405
Byte Write Truth Table
HM66AEB36105
Operation
K
K
BW0
L
BW1
L
BW2
L
BW3
L
Write D0 to D35
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L
L
L
L
Write D0 to D8
Write D9 to D17
Write D18 to D26
Write D27 to D35
Write nothing
L→H
L→H
L→H
L→H
L→H
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
L
H
H
Notes: 1. H: high level, L: low level, →: rising edge.
2. Assumes a WRITE cycle was initiated. BW0 to BW3 can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
HM66AEB18205
Operation
K
K
BW0
L
BW1
L
Write D0 to D17
Write D0 to D8
Write D9 to D17
Write nothing
L→H
L→H
L→H
L→H
L→H
L
L
L→H
L→H
L→H
L
H
L
H
H
L
H
L
H
H
H
H
Notes: 1. H: high level, L: low level, →: rising edge.
2. Assumes a WRITE cycle was initiated. BW0 and BW1 can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
HM66AEB9405
Operation
K
K
BW
L
Write D0 to D8
L→H
L→H
L→H
L
Write nothing
L→H
H
H
Notes: 1. H: high level, L: low level, →: rising edge.
2. Assumes a WRITE cycle was initiated. BW can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
Rev.1.00 Sep 06, 2006 page 7 of 20
HM66AEB36105/18205/9405
Bus Cycle State Diagram
= L
= H,
Count = 2
= L,
Count = 2
WRITE DOUBLE
Count = Count + 2
R/ = L
LOAD NEW
ADDRESS
Count = 0
= H
NOP
R/ = H
= L,
Count = 2
READ DOUBLE
Count = Count + 2
Supply voltage provided
= H,
Count = 2
POWER UP
Note:
1. State machine control timing sequence is controlled by K.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Notes
Input voltage on any ball
VIN
−0.5 to VDD + 0.5
V
1, 4
(2.5 V max.)
Input/output voltage
VI/O
−0.5 to VDDQ + 0.5
V
1, 4
(2.5 V max.)
Core supply voltage
VDD
VDDQ
Tj
−0.5 to 2.5
−0.5 to VDD
+125 (max)
−55 to +125
V
V
1, 4
1, 4
Output supply voltage
Junction temperature
°C
°C
Storage temperature
TSTG
Notes: 1. All voltage is referenced to VSS.
2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables
after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN.
Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.5 V, whatever the
instantaneous value of VDDQ
.
Rev.1.00 Sep 06, 2006 page 8 of 20
HM66AEB36105/18205/9405
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Power supply voltage -- core
Power supply voltage -- I/O
Input reference voltage -- I/O
Input high voltage
Symbol
VDD
Min
1.7
Typ
1.8
Max
1.9
Unit
V
Notes
VDDQ
1.4
1.5
VDD
V
VREF
0.68
0.75
0.95
V
1
VIH (DC)
VIL (DC)
VREF + 0.1
−0.3
VDDQ + 0.3
V
2, 3
2, 3
Input low voltage
V
REF − 0.1
V
Notes: 1. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF
2. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2
.
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2
Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
During normal operation, VDDQ must not exceed VDD
.
Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH
(min).
3. These are DC test criteria. The AC VIH / VIL levels are defined separately to measure timing parameters.
DC Characteristics
(Ta = 0 to +70°C, VDD = 1.8 V ± 0.1 V)
HM66AEB36105/HM66AEB18205
HM66AEB9405
-30
-33
-40
Max
740
800
-50
-60
Parameter
Operating supply current
Symbol
Unit
Notes
(×9 / ×18)
(×36)
IDD
IDD
900
960
840
900
620
670
550
590
mA
mA
1, 2, 3
1, 2, 3
(READ / WRITE)
Standby supply current
(NOP)
(×9 / ×18 / ×36)
ISB1
350
330
300
280
260
mA
2, 4, 5
Parameter
Input leakage current
Output leakage current
Output high voltage
Symbol
Min
−2
Max
Unit Test conditions Notes
ILI
2
2
µA
µA
V
10
11
ILO
−2
VOH
V
DDQ − 0.2
VDDQ
|IOH| ≤ 0.1 mA
8, 9
(Low)
VOH
VDDQ/2 − 0.08
VDDQ/2 + 0.08
V
V
Notes6
8, 9
8, 9
Output low voltage
VOL
VSS
0.2
I
OL ≤ 0.1 mA
(Low)
VOL
VDDQ/2 − 0.08
VDDQ/2 + 0.08
V
Notes7
8, 9
Notes: 1. All inputs (except ZQ, VREF) are held at either VIH or VIL.
2. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min.
3. Operating supply currents are measured at 100% bus utilization.
4. All address / data inputs are static at either VIN > VIH or VIN < VIL.
5. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed.
6. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
7. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
8. AC load current is higher than the shown DC values. AC I/O curves are available upon request.
9. HSTL outputs meet JEDEC HSTL Class I and Class II standards.
10.0 ≤ VIN ≤ VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball).
11.0 ≤ VOUT ≤ VDDQ (except TDO ball), output disabled.
Rev.1.00 Sep 06, 2006 page 9 of 20
HM66AEB36105/18205/9405
Capacitance
(Ta = +25°C, f = 1.0 MHz, VDD = 1.8 V, VDDQ = 1.5 V)
Parameter
Input capacitance
Symbol
CIN
Min
Typ
4
Max
Unit
pF
Test conditions
VIN = 0 V
5
6
7
Clock input capacitance
Input/output capacitance (D, Q, ZQ)
CCLK
CI/O
5
pF
VCLK = 0 V
VI/O = 0 V
6
pF
Notes: 1. These parameters are sampled and not 100% tested.
2. Except JTAG (TCK, TMS, TDI, TDO) pins.
AC Characteristics
(Ta = 0 to +70°C, VDD = 1.8 V ± 0.1 V)
Test Conditions
Input waveform (Rise/fall time ≤ 0.3 ns)
1.25 V
0.75 V
Test points
0.75 V
0.25 V
Output waveform
VDDQ/2
Test points
VDDQ/2
Output load condition
VDDQ/2
0.75 V
50 Ω
VREF
Zo = 50 Ω
SRAM
Q
250 Ω
ZQ
Rev.1.00 Sep 06, 2006 page 10 of 20
HM66AEB36105/18205/9405
Operating Conditions
Parameter
Input high voltage
Input low voltage
Symbol
VIH (AC)
VIL (AC)
Min
Typ
Max
Unit
V
Notes
VREF + 0.2
1, 2, 3, 4
1, 2, 3, 4
V
REF − 0.2
V
Notes: 1. All voltages referenced to VSS (GND).
2. These conditions are for AC functions only, not for AC parameter test.
3. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2
Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less
than tKHKL (min) or operate at cycle rates less than tKHKH (min).
4. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC)
b. Reach at least the target AC level.
.
c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC)
.
HM66AEB36105/HM66AEB18205
HM66AEB9405
-30
-33
-40
-50
-60
Parameter
Symbol
Unit Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Average clock
cycle time
tKHKH
3.00
3.47
3.30
4.20
4.00
5.25
5.00
6.30
6.00
7.88
ns
(K, K, C, C)
Clock phase jitter tKC var
0.20
0.20
0.20
0.20
0.20
ns
ns
ns
ns
ns
ns
3
(K, K, C, C)
Clock high time
(K, K, C, C)
Clock low time
(K, K, C, C)
Clock to clock
(K to K, C to C)
tKHKL
tKLKH
tKH/KH
t/KHKH
tKHCH
1.20
1.20
1.35
1.35
0
1.32
1.32
1.49
1.49
0
1.60
1.60
1.80
1.80
0
2.00
2.00
2.20
2.20
0
2.40
2.40
2.70
2.70
0
Clock to clock
(K to K, C to C)
Clock to data
1.30
1.45
1.80
2.30
2.80
clock
(K to C, K to C)
DLL lock time
tKC lock 1,024
tKC reset 30
tCHQV
1,024
30
1,024
30
1,024
30
1,024
30
Cycle
ns
2
7
(K, C)
K static to DLL
reset
C, C high to
output valid
0.45
0.45
0.45
0.45
0.45
0.45
0.45
0.45
0.50
0.50
ns
C, C high to
output hold
tCHQX
−0.45
−0.45
−0.45
−0.45
−0.45
−0.45
−0.45
−0.50
−0.50
ns
C, C high to echo tCHCQV
clock valid
ns
C, C high to echo tCHCQX −0.45
clock hold
ns
Rev.1.00 Sep 06, 2006 page 11 of 20
HM66AEB36105/18205/9405
HM66AEB36105/HM66AEB18205
HM66AEB9405
-30
-33
-40
-50
-60
Parameter
Symbol
Unit Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
CQ, CQ high to
tCQHQV
0.25
0.27
0.30
0.35
0.40
ns
ns
ns
ns
ns
ns
4, 7
4, 7
5
output valid
CQ, CQ high to
output hold
tCQHQX −0.25
tCHQZ
−0.27
−0.30
−0.35
−0.40
C, C high to
output high-Z
0.45
0.45
0.45
0.45
0.50
C, C high to
output low-Z
tCHQX1 −0.45
−0.45
0.40
0.40
−0.45
0.50
0.50
−0.45
0.60
0.60
−0.50
0.70
0.70
5
Address valid to
K rising edge
tAVKH
tIVKH
0.40
0.40
1
Control inputs
valid to K rising
edge
1
Data-in valid to
K, K rising edge
K rising edge to
tDVKH
tKHAX
tKHIX
0.28
0.40
0.40
0.30
0.40
0.40
0.35
0.50
0.50
0.40
0.60
0.60
0.50
0.70
0.70
ns
ns
ns
1
1
1
address hold
K rising edge to
control inputs
hold
K, K rising edge
to data-in hold
tKHDX
0.28
0.30
0.35
0.40
0.50
ns
1
Notes: 1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold
times for all latching clock edges.
2. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD
and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ±0.1 ns variation from echo
clock to data. The datasheet parameters reflect tester guardbands and test setup variations.
5. Transitions are measured ±100 mV from steady-state voltage.
6. At any given voltage and temperature tCHQZ is less than tCHQX1 and tCHQZ less than tCHQV
.
7. These parameters are sampled.
Remarks: 1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise
noted.
2. Control input signals may not be operated with pulse widths less than tKHKL (min).
3. If C, C are tied high, K, K become the references for C, C timing parameters.
4. VDDQ is +1.5 V DC.
5. Control signals are LD, R/W, BW, BW0, BW1, BW2 and BW3.
Rev.1.00 Sep 06, 2006 page 12 of 20
HM66AEB36105/18205/9405
Timing Waveforms
Read and Write Timing
NOP
1
READ
(burst of 2)
READ
WRITE
WRITE
READ
(burst of 2)
NOP
7
(burst of 2) (burst of 2) (burst of 2)
2
3
4
5
6
8
K
tKHKL tKLKH
tKHKH
tKH/KH
t/KHKH
tIVKH
tKHIX
R/
Address
Data in
A0
A1
A2
A3
A4
tDVKH tKHDX
tDVKH tKHDX
tAVKH tKHAX
D21 D22 D31 D32
Data out
Qx2
Q01 Q02 Q11 Q12
Q41 Q42
tCQHQX
tCHQX1
tCHQZ
tCHQX
tCQHQV
tCHQX
tCHQV tCHQV
CQ
tCHCQX
tCHCQV
tCHCQX
tCHCQV
tKHCH
C
tKHKL tKLKH
tKHKH
tKH/KH t/KHKH
tKHCH
Notes:
1. Q01 refers to output from address A0+0. Q02 refers to output from the next internal burst
address following A0, i.e., A0+1.
2. Outputs are disable (high-Z) one clock cycle after a NOP.
3. In this example, if address A3 = A4, then data Q41 = D31, Q42 = D32. Write data is
forwarded immediately as read results.
4. To control read and write operations, BW signals must operate at the same timing as Data in.
Rev.1.00 Sep 06, 2006 page 13 of 20
HM66AEB36105/18205/9405
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs.
TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and
may be left unconnected. But they may also be tied to VDD through a 1kΩ resistor.
TDO should be left unconnected.
Test Access Port (TAP) Pins
Symbol I/O
Pin assignments
Description
TCK
2R
Test clock input. All inputs are captured on the rising edge of TCK
and all outputs propagate from the falling edge of TCK.
TMS
TDI
10R
11R
Test mode select. This is the command input for the TAP controller
state machine.
Test data input. This is the input side of the serial registers placed
between TDI and TDO. The register placed between TDI and TDO is
determined by the state of the TAP controller state machine and the
instruction that is currently loaded in the TAP instruction.
TDO
1R
Test data output. Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note: The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for
five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP.
TAP DC Operating Characteristics
(Ta = 0 to +70°C, VDD = 1.8 V ± 0.1 V)
Parameter
Input high voltage
Symbol
VIH
Min
+1.3
−0.3
−5.0
−5.0
Max
VDD + 0.3
+0.5
Unit
V
Conditions
Input low voltage
VIL
V
Input leakage current
Output leakage current
ILI
+5.0
µA
µA
0 V ≤ VIN ≤ VDD
0 V ≤ VIN ≤ VDD,
ILO
+5.0
output disabled
IOLC = 100 µA
IOLT = 2 mA
Output low voltage
Output high voltage
VOL1
VOL2
VOH1
VOH2
0.2
0.4
V
V
V
V
1.6
1.4
|IOHC| = 100 µA
|IOHT| = 2 mA
Notes: 1. All voltages referenced to VSS (GND).
2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ +1.7 V and VDDQ ≤ +1.4 V for t ≤ 200 ms.
3. In “EXTEST” mode and “SAMPLE” mode, VDDQ is nominally 1.5 V.
4. ZQ: VIH = VDDQ
.
Rev.1.00 Sep 06, 2006 page 14 of 20
HM66AEB36105/18205/9405
TAP AC Test Condition
•
•
•
•
•
•
•
Temperature
Input timing measurement reference levels
Input pulse levels
0°C ≤ Ta ≤ +70°C
0.9 V
0 V to 1.8 V
≤ 1.0 ns
0.9 V
0.9 V
Input rise/fall time
Output timing measurement reference levels
Test load termination supply voltage (VTT)
Output load
See figures
Input waveform
1.8 V
0 V
0.9 V
Test points
0.9 V
Output waveform
0.9 V
Test points
0.9 V
Output load
VTT = 0.9 V
50 Ω
Zo = 50 Ω
TDO
20 pF
External load at test
Rev.1.00 Sep 06, 2006 page 15 of 20
HM66AEB36105/18205/9405
TAP AC Operating Characteristics
(Ta = 0 to +70°C, VDD = 1.8 V ± 0.1 V)
Parameter
Test clock cycle time
Test clock high pulse width
Test clock low pulse width
Test mode select setup
Test mode select hold
Capture setup
Symbol
tTHTH
tTHTL
tTLTH
tMVTH
tTHMX
tCS
Min
100
40
40
10
10
10
10
10
10
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
1
Capture hold
tCH
TDI valid to TCK high
TCK high to TDI invalid
TCK low to TDO unknown
TCK low to TDO valid
tDVTH
tTHDX
tTLQX
tTLQV
20
Note: 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
TAP Controller Timing Diagram
tTHTH
TCK
tMVTH
tTHTL
tTLTH
TMS
TDI
tTHMX
tDVTH
tTHDX
tTLQV
TDO
tCS
tTLQX
tCH
PI (SRAM)
Test Access Port Registers
Register name
Instruction register
Bypass register
Length
Symbol
IR [2:0]
BP
3 bits
1 bit
ID register
32 bits
109 bits
ID [31:0]
BS [109:1]
Boundary scan register
Rev.1.00 Sep 06, 2006 page 16 of 20
HM66AEB36105/18205/9405
TAP Controller Instruction Set
IR2
IR1
IR0
Instruction
EXTEST
Description
Notes
0
0
0
The EXTEST instruction allows circuitry external to the component
package to be tested. Boundary scan register cells at output balls are
used to apply test vectors, while those at input balls capture test
results. Typically, the first test vector to be applied using the EXTEST
instruction will be shifted into the boundary scan register using the
PRELOAD instruction. Thus, during the Update-IR state of EXTEST,
the output driver is turned on and the PRELOAD data is driven onto
the output balls.
1, 2, 3
0
0
0
1
1
0
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID
register when the controller is in capture-DR mode and places the ID
register between the TDI and TDO balls in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and
any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all
RAM outputs are forced to an inactive drive state (high-Z), moving the
TAP controller into the capture-DR state loads the data in the RAMs
input into the boundary scan register, and the boundary scan register
is connected between TDI and TDO when the TAP controller is moved
to the shift-DR state.
3, 4
0
1
1
0
1
0
RESERVED
The RESERVED instructions are not implemented but are reserved for
future use. Do not use these instructions.
SAMPLE
(/PRELOAD)
When the SAMPLE instruction is loaded in the instruction register,
moving the TAP controller into the capture-DR state loads the data in
the RAMs input and I/O buffers into the boundary scan register.
Because the RAM clock(s) are independent from the TAP clock (TCK)
it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e., in a metastable state).
Although allowing the TAP to SAMPLE metastable input will not harm
the device, repeatable results cannot be expected. Moving the
controller to shift-DR state then places the boundary scan register
between the TDI and TDO balls.
3
1
1
1
0
1
1
1
0
1
RESERVED
RESERVED
BYPASS
The BYPASS instruction is loaded in the instruction register when the
bypass register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the shift-DR state. This allows the
board level scan path to be shortened to facilitate testing of other
devices in the scan path.
Notes: 1. Data in output register is not guaranteed if EXTEST instruction is loaded.
2. After performing EXTEST, power-up conditions are required in order to return part to normal operation.
3. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold
time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing
the I/O ring contents into the boundary scan register.
4. Clock recovery initialization cycles are required to return from the SAMPLE-Z instruction.
ID Register
Revision number
(31:29)
Type number
(28:12)
Vendor JEDEC code
(11:1)
Start bit
(0)
Part
HM66AEB36105
HM66AEB18205
HM66AEB9405
000
000
000
00010011010000010
00010010010000010
00010000010000010
01000100011
01000100011
01000100011
1
1
1
Rev.1.00 Sep 06, 2006 page 17 of 20
HM66AEB36105/18205/9405
Boundary Scan Order
Signal names
×18
C
Signal names
×18
NC
Bit #
Ball ID
Bit #
Ball ID
×9
C
×36
C
×9
NC
CQ
SA
SA
SA
SA
SA
LD
×36
Q17
CQ
1
6R
6P
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
10B
11A
10A
9A
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1H
1J
2
C
C
C
CQ
3
6N
SA
SA
SA
SA
SA
SA
SA
Q0
D0
NC
NC
NC
NC
NC
NC
Q1
D1
NC
NC
NC
NC
NC
NC
Q2
D2
ZQ
NC
NC
NC
NC
NC
NC
Q3
D3
NC
NC
NC
NC
NC
NC
Q4
D4
NC
SA
SA
SA
SA
SA
SA
SA
Q0
D0
SA
NC
NC
4
7P
SA
SA
SA
5
7N
SA
SA
SA
6
7R
SA
SA
SA
7
8R
SA
SA
SA
8
8P
SA
LD
NC
LD
9
9R
SA
NC
BW
K
BW1
BW0
K
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
11P
10P
10N
9P
Q0
BW0
K
D0
NC
NC
Q1
D1
D9
K
K
NC
K
Q9
NC
NC
R/W
SA
SA
SA
VSS
CQ
NC
NC
NC
NC
NC
NC
NC
NC
Q5
D5
BW3
BW2
R/W
SA
10M
11N
9M
Q1
BW1
R/W
SA
D1
NC
NC
Q2
D2
D10
Q10
Q2
9N
SA
SA
11L
11M
9L
SA
NC
D2
VSS
VSS
NC
NC
Q3
D3
D11
Q11
Q3
CQ
Q9
CQ
10L
11K
10K
9J
Q18
D18
D27
Q27
Q19
D19
D28
Q28
Q20
D20
D29
Q29
Q21
D21
D30
Q30
Q22
D22
DOFF
D31
Q31
Q23
D23
D32
Q32
D9
D3
NC
NC
NC
Q4
D4
D12
Q12
Q4
NC
9K
Q10
D10
NC
10J
11J
11H
10G
9G
D4
ZQ
NC
NC
Q5
D5
ZQ
D13
Q13
Q5
NC
Q11
D11
NC
11F
11G
9F
NC
NC
NC
NC
NC
NC
Q6
D6
D5
NC
NC
NC
Q6
D6
D14
Q14
Q6
Q12
D12
NC
10F
11E
10E
10D
9E
D6
NC
NC
NC
Q7
D7
D15
Q15
Q7
Q13
D13
DOFF
NC
10C
11D
9C
DOFF
NC
NC
NC
NC
NC
NC
D7
NC
NC
Q8
D8
D16
Q16
Q8
2J
NC
9D
3K
3J
Q14
D14
NC
11B
11C
9B
D8
2K
1K
NC
D17
NC
Rev.1.00 Sep 06, 2006 page 18 of 20
HM66AEB36105/18205/9405
Signal names
×18
Signal names
Bit #
Ball ID
Bit #
Ball ID
×9
Q7
D7
NC
NC
NC
NC
NC
NC
Q8
D8
×36
Q24
D24
D33
Q33
Q25
D25
D34
Q34
Q26
D26
×9
NC
NC
SA
SA
SA
SA
SA
SA
×18
NC
NC
SA
SA
SA
SA
SA
SA
×36
D35
Q35
SA
91
92
93
94
95
96
97
98
99
100
2L
3L
Q15
101
102
103
104
105
106
107
108
109
2P
1P
3R
4R
4P
5P
5N
5R
D15
1M
1L
NC
NC
SA
3N
3M
1N
2M
3P
2N
Q16
SA
D16
SA
NC
SA
NC
SA
Q17
INTER-
NAL
INTER-
NAL
INTER-
NAL
D17
Note: In boundary scan mode,
1. Clock balls (K / K, C / C) are referenced to each other and must be at opposite logic levels for reliable
operation.
2. CQ and CQ data are synchronized to the respective C and C (except EXTEST, SAMPLE-Z).
3. If C and C tied high, CQ is generated with respect to K and CQ is generated with respect to K (except
EXTEST, SAMPLE-Z).
4. ZQ must be driven to VDDQ supply to ensure consistent results.
TAP Controller State Diagram
Test-Logic-
1
Reset
0
1
1
1
Run-Test/
Idle
Select-
DR-Scan
Select-
IR-Scan
0
0
0
1
1
Capture-DR
0
Capture-IR
0
Shift-DR
1
Shift-IR
1
0
0
0
0
1
1
Exit1-DR
0
Exit1-IR
0
Pause-DR
1
Pause-IR
1
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
0
1
0
Notes: The value adjacent to each state transition in this figure represents the signal present
at TMS at the time of a rising edge at TCK.
No matter what the original state of the controller, it will enter Test-Logic-Reset when
TMS is held high for at least five rising edges of TCK.
Rev.1.00 Sep 06, 2006 page 19 of 20
HM66AEB36105/18205/9405
Package Dimensions
HM66AEB36105/18205/9405BP (PLBG0165FB-A / Previous Code: BP-165A)
JEITA Package Code
RENESAS Code
PLBG0165FB-A
Previous Code
BP-165A
MASS[Typ.]
0.7g
P-LBGA165-15x17-1.00
D
A
B
INDEX
y1
S
S
y
S
e
R
P
N
M
L
Dimension in Millimeters
Reference
Symbol
Min
Nom
15.00
17.00
Max
15.10
17.10
K
J
D
E
14.90
16.90
H
G
F
v
w
E
D
C
B
A
A
1.34
0.27
1.40
0.32
1.00
0.50
1.46
0.37
A1
e
b
0.45
0.55
0.20
0.15
0.25
x
1
2
3
4
5
6
7
8
9
10 11
y
φ b
φ
×
M
S
A
S
B
y1
SD
SE
ZD
ZE
φ
0.07
M
Rev.1.00 Sep 06, 2006 page 20 of 20
Revision History
HM66AEB36105/HM66AEB18205
HM66AEB9405 Data Sheet
Rev.
Date
Contents of Modification
Description
Page
0.0
0.01
Jan. 17, 2003
Apr.28.2004
Initial issue
Change format issued by Renesas Technology Corp.
HM66AEB9405: Change of pin names
D0 to D1
D1 to D2
D2 to D3
D3 to D4
D4 to D5
D5 to D6
D6 to D7
D7 to D8
D8 to D0
Q0 to Q1
Q1 to Q2
Q2 to Q3
Q3 to Q4
Q4 to Q5
Q5 to Q6
Q6 to Q7
Q7 to Q8
Q8 to Q0
4
5-6
Addition of Notes on Usage
Pin Descriptions
SAn to SA
SA: Change of Descriptions
BW, BWn: Change of Descriptions
K, K: Change of Descriptions
C, C: Change of Descriptions
ZQ: Change of Descriptions
D0 to Dn: Change of Descriptions
Q0 to Qn: Change of Descriptions
VREF: Change of Descriptions
NC: Change of Descriptions
Block Diagram
Change of the figures
Truth Table
7-8
9
DA(A+0) to D(A+0)
DA(A+1) to D(A+1)
QA(A+0) to Q(A+0)
QA(A+1) to Q(A+1)
Change of Notes6
10-11 Byte Write Truth Table
0 to L
1 to H
Rev.
0.01
Date
Contents of Modification
Description
Page
12
Apr.28.2004
Absolute Maximum Ratings
VIN, VI/O, VDD, VDDQ (Notes4)
Maximum value: 2.9 V to 2.5 V
Recommended DC Operating Conditions
Deletion of Notes2
Notes3 to Notes2
Change of Notes2
12
13
Addition of Notes3
DC Characteristics (1st table)
I
I
I
DD (Max):
×9, ×18:
525/475/400/330/280 mA
to 900/840/740/620/550 mA
×36:
710/640/545/445/380 mA
to 960/900/800/670/590 mA
SB1 (Max):
×9, ×18:
255/235/200/170/150 mA
to 350/330/300/280/260 mA
×36:
265/245/210/180/160 mA
to 350/330/300/280/260 mA
DD, ISB1: Addition of Notes
Deletion of Notes3
Notes4 to Notes3
Addition of Notes4
Notes1-5 are moved to DC Characteristics (2nd table)
DC Characteristics (2nd table)
Deletion of IOH, IOL
13
Deletion of Notes5-7, 10
Notes1-4 to Notes6-9
Notes8-9 to Notes10-11
Capacitance
Change of condition
14
15
CI/O: Change of Parameter
Change of Notes2
V
IH (AC), VIL (AC): Addition of Notes4
Addition of Notes2
Notes2-3 to Notes3-4
Change of Notes3
16
17
t
t
KC reset, tCQHQV, tCQHQX: Addition of Notes7
CHQZ, tCHQX1: Change of Parameter
Remarks1 to Notes7
Change of Notes7
Remarks2-5 to Remarks1-4
Addition of Remarks5
Timing Waveforms
Change of Notes3
18
Addition of Notes4
Rev.
0.01
Date
Contents of Modification
Description
Page
20
Apr.28.2004
TAP DC Operating Characteristics
Addition of Notes4
22
TAP Controller Timing Diagram
Change of the figure
23-24 TAP Controller Instruction Set
SAMPLE(-PRELOAD) to SAMPLE(/PRELOAD)
EXTEST, SAMPLE-Z, RESERVED, SAMPLE(/PRELOAD):
Change of Description
Addition of Notes3-4
24
ID Register
Vendor JEDEC code:
00000000111 to 01000100011
25-26 Boundary Scan Order
Change of Note
28
Package Dimensions
Change of the figure of BP-165A
1.00
Sep.06.2006
Change format revised by Renesas Technology Corp.
Ordering Information to Part No. Information
Part No. Information
2
2
Type No. to Catalogue Part No.
Addition of Ordering Part No.
Addition of the Renesas package code
Package Dimensions
20
Addition of the Renesas package code
Changed to the Renesas format
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