HN29V1G91T-30 [RENESAS]
128M X 8-bit AG-AND Flash Memory; 128M ×8位AG -AND闪存
| 型号： | HN29V1G91T-30 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 128M X 8-bit AG-AND Flash Memory |
| 文件： | 总92页 (文件大小：1587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HN29V1G91T-30
128M × 8-bit AG-AND Flash Memory
REJ03C0056-0400Z
Rev. 4.00
Jul.20.2004
Description
The HN29V1G91 series achieves a write speed of 10 Mbytes/sec, which is 5 times faster than Renesas's
previous multi level cell Flash memory, using 0.13µm process technology and AG-AND (Assist Gate-
AND) type Flash memory cell using multi level cell technology provides both the most cost effective
solution and high speed programming.
Features
•
•
•
On-board single power supply: VCC = 2.7 V to 3.6 V
Operation Temperature range: Ta = 0 to +70°C
Memory organization
Memory array: (2048+64) bytes × 16384 page × 4 Bank
Page size: (2048+64) bytes
Block size: (2048+64) bytes × 2 page
Page Register: (2048+64) bytes × 4 Bank
Multi level memory cell
•
•
2bit/cell
Automatic program
Page program
Multi bank program
Cache program
2 page cache program
•
•
Automatic Erase
Block Erase
Multi Bank Block Erase
Access time
Memory array to register (1st access time): 120 µs max
Serial access: 35 ns min
Rev.4.00, Jul.20.2004, page 1 of 89
HN29V1G91T-30
•
Low power dissipation
Read ICC1 (50 ns cycle): 10 mA (typ)
Read ICC2 (35 ns cycle): 15 mA (typ)
Program ICC3 (single bank): 10 mA (typ)
Program ICC4 (Multi bank): 20 mA (typ)
Erase ICC5 (single bank): 10 mA (typ)
Erase ICC6 (Multi bank): 15 mA (typ)
Standby ISB1 (TTL): 1 mA (max)
Standby ISB2 (CMOS): 50 µA (max)
Deep Standby ISB3: 5 µA (max)
•
Program time: 600 µs (typ) (Single/Multi bank)
transfer rate: 10 MB/s (Multi bank)
•
•
Erase time: 650 µs (typ) (Single/Multi bank)
The following architecture is required for data reliability
Error correction: 3 bit error correction per 512byte are recommended.
Block replacement: When an error occurs in program page, block replacement including
corresponding page should be done. When an error occurs in erase operation, future access to this
bad block is prohibited. It is required to manage it creating a table or using another appropriate
scheme by the system (Valid blocks: Initial valid blocks for more than 98% per Bank.
Replacement blocks must be ensured more than 1.8% of valid blocks per Bank).
Wear leveling: Wear leveling is to level Program and Erase cycles in one block in order to reduce
the burden for one block and let the device last for long time. Actually, it does detect the block
which is erased and rewritten many times and replace it with less accessed block.
To secure 105 cycles as the program/erase endurance, need to control not to exceed Program and
Erase cycles to one block. You should adopt wear leveling once in 5000 Program and Erase cycles.
It is better to program it as a variable by software.
•
•
Program/Erase Endurance: 105 cycles
Package line up
TSOP: TSOP Type-I 48pin package (TFP-48DA)
Ordering Information
Type No.
Operating voltage (VCC
)
Organization
Package
HN29V1G91T-30
2.7 V to 3.6 V
×8
12.0 × 20.00 mm2
0.5 mm pitch
48-pin plastic TSOPI (TFP-48DA)
Rev.4.00, Jun.20.2004, page 2 of 89
HN29V1G91T-30
Pin Arrangement
48-pin TSOP
RES
NC
NC
NC
NC
NC
R/B
RE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
NC
PRE
VCC
VSS
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
(Top view)
Pin configuration
Pin name
I/O 1 to I/O 8
CLE
Function
Command, address, data Input/output
Command Latch Enable
Address Latch Enable
Chip Enable
ALE
CE
RE
Read Enable
WE
Write Enable
WP
Write Protect
R/B
Ready/Busy
PRE
RES
VCC
Power on Auto Read Enable
Reset
Power
VSS
Ground
NC
No Connection
Rev.4.00, Jun.20.2004, page 3 of 89
HN29V1G91T-30
Block Diagram
16
Page address buffer
Bank0
Bank Bank
Bank3
1
2
Memory array
(2048+64)
x 16384 page
Memory array
(2048+64)
x 16384 page
X-
decoder
X-
decoder
16
I/O1
to
8
8
Data
input
buffer
Data register
2048+64 byte
Data register
2048+64 byte
Multi-
plexer
I/O8
Y-Gating
Y-Gating
Y-Decoder
Y-Decoder
Input data
control
VCC
VSS
8
12
Column address
counter
Data
output buffer
R/B
CE
Read/Program/Erase
control
RE
Control
signal
buffer
WE
WP
CLE
ALE
PRE
RES
Rev.4.00, Jun.20.2004, page 4 of 89
HN29V1G91T-30
Memory map and address
Memory Map
FFFFH
FFFEH
FFFDH
1Page = (2048+64)Bytes: Program Size
1Block = (2048+64)Bytes x 2Pages: Erase Size
= (4096+128)Bytes: Erase Size
1Device = (2048+64)Bytes x 2Pages x 32768Blocks
0006H
0005H
0004H
0003H
0002H
0001H
Block 2
Block 1
Block 0
2048bytes
64bytes
64bytes
0000H
Data register
2048bytes
Bank Organization
Bank0
(8192Blocks)
(16384pages)
Bank1
(8192Blocks)
(16384pages)
Bank2
(8192Blocks)
(16384pages)
Bank3
(8192Blocks)
(16384pages)
Block 0
page 0
page 4
Block 1
page 1
page 5
Block 2
page 2
page 6
Block 3
page 3
page 7
Block 4
page 8
page 12
Block 5
page 9
page 13
Block 6
page 10
page 14
Block 7
page 11
page 15
Block 32764
page 65528
page 65532
Block 32765
page 65529
page 65533
Block 32766
page 65530
page 65534
Block 32767
page 65531
page 65535
Addressing
Symbol I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
1st Cycle
CA1
CA2
RA1
RA2
A7
L
A6
L
A5
L
A4
L
A3
A2
A1
A9
A0
A8
Column
address
2nd Cycle
3rd Cycle
4th Cycle
A11 A10
A19 A18 A17 A16 A15 A14 A13 A12
A27 A26 A25 A24 A23 A22 A21 A20
Row
address
A12, A13: Bank select
A14: Page select
A15 to A27: Block select
Rev.4.00, Jun.20.2004, page 5 of 89
HN29V1G91T-30
Pin Functions
Chip Enable: CE
CE is used for the selection of the device.
It goes to the standby mode when CE goes to ‘H’ level when the device is in the Output disable state.
When the device is in the Busy state during Program or Erase or Read operation, CE signal is ignored and
the device does not return to the standby mode even if CE goes to High.
Read Enable: RE
The RE signal controls serial data output. Data is available tREA after the falling edge of RE.
The internal address counter is also incremented by one (Address = Address + 1) on this falling edge.
Write Enable: WE
WE is the signal to latch each data in the device from the I/O port.
Data are latched in the device on the rising edge of WE.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the operation mode command into the internal register.
The command is latched into the internal register from the I/O port on the rising edge of WE when CLE is
high.
Address Latch Enable: ALE
The ALE input signal is used to control loading of the input address information or input data into the
internal address/data register.
Address is latched on the rising edge of WE with ALE high and Data is latched with ALE low.
I/O port: I/O1 to I/O8
The I/O1 to I/O8 pins are used as a port for transferring address, command and input/output data to and
from the device.
Write Protect: WP
The WP signal is used to protect the device from accidental programming or erasing. The WP low reset
internal program/erase operation. It is usually used for protecting the data with the WP low during the
power-on/off sequence when input signals are invalid.
Ready Busy: R/B
The R/B output signal indicates the status of the device operation. When it is low, it indicates that the
Program, Erase or Read operation is in process and returns to Ready state (R/B = H) after completion of
the operation.
The output buffer for this signal is an open-drain and has to be pulled up to VCC with appropriate register.
Rev.4.00, Jun.20.2004, page 6 of 89
HN29V1G91T-30
Reset: RES
The RES signal controls reset operation for device. When power on and power off, keep pin VILD level
(VSS 0.2V), and keep pin VIHD level (VCC 0.2V) during program, erase, read operation.
The transition to deep standby mode is executed when RES set VILD level during standby mode.
Power on auto Read Enable: PRE
The PRE controls auto read operation executed during power-on. The power-on auto-read is enabled when
PRE pin is tied to VCC. Please contact Renesas Technology’s sales office before using the power-on auto-
read.
Rev.4.00, Jun.20.2004, page 7 of 89
HN29V1G91T-30
Mode selection
The address input, command input, and data input/output operation of the device are controlled by RES,
WP, WE, CE, CLE, ALE, RE, PRE signals. The following shows the operation logic table.
Logic Table
Mode
RES*3
WP*3
CE
L
WE
CLE
H
ALE
L
RE
H
PRE*3
×*2
×*2
Read Mode
Command Input
H
H
×
×
Address Input
(4clock)
L
L
H
H
Write Mode
Command Input
H
H
H
H
L
L
H
L
L
H
H
×*2
×*2
Address Input
(4clock)
H
Data Input
H
H
H
H
H
H
H
H
×
L
L
L
×
L
L
L
×
×
×
×
L
L
L
×
×
×
×
H
×*2
×*2
×*2
×*2
×*2
×*2
Data Output
H
H
×
During Read (Busy)
During Program (Busy)
During Erase (Busy)
Write Protect
×
H
×
×
×
×
H
H
L
×
×
×
×
Stand-by
VSS 0.2 V
/VCC 0.2 V
H
×
VSS 0.2 V
/VCC 0.2 V
Deep Stand-by
VSS 0.2 V
VSS 0.2 V
/VCC 0.2 V
×
×
×
×
×
VSS 0.2 V
/VCC 0.2 V
Notes: 1. H: ViH, L: ViL, ×: ViH or ViL
2. PRE must be “H” fix when using Power On Auto Read and “L” fix when not using it.
3. RES, WP, PRE must be set L: ViLD, H: ViHD, ×: ViHD or ViLD
Program/Erase Characteristics
Symbol
tPROG
tCPROG
tCBSY
tDBSY
N
Min
1
Typ
0.6
0.6
3
Max
2.4
4.8
2400
4
Unit
ms
ms
µs
Notes
Program Time
Cache Program Time
Dummy Busy for Cache Program
Dummy Busy Time
µs
Number of Partial Program Cycles in a Same Page
Block Erase Time
8
cycles
ms
tBERS
tPEV
0.65
20
Page mode Erase Verify Time
Block mode Erase Verify Time
50
µs
tBEV
70
µs
Rev.4.00, Jun.20.2004, page 8 of 89
HN29V1G91T-30
Command Definition
Command Sets
1st. cycle
2nd. cycle
30h
31h
E0h
35h
10h
E0h
11h
E0h
10h
acceptable while Busy
Read
00h
Multi Bank Read
00h
Random Data output in a Page
Read for copy back
Copy Back Program
Page Data output
05h
00h
85h
06h
Multi Bank Copy Back Program
Data Recovery Read
Data Recovery Program
Reset
85h
06h
85h
FFh
Acceptable
Page Program
80h
10h
Acceptable*2
Acceptable*2
Acceptable*2
Random Data Input in a Page
Multi Bank Page Program
Cache Program
85h
80h
11h
15h
D0h
D0h
80h
Block Erase
60h
Multi Bank Block Erase
Read Status
60h−60h
70h
Acceptable
Acceptable
Acceptable
Acceptable
Read Error Status
72h
Read Multi Block Status
Read Multi Block Error Status*1
Status mode Reset
Page mode Erase Verify
Block mode Erase Verify
Read ID
71h
73h, 74h, 75h, 76h
7Fh
60h
60h
90h
00h
D2h
D3h
Device Recovery
38h
Notes: 1. Read Multi Block Error Status
73h: Bank0 Error Status, 74h: Bank1 Error Status, 75h: Bank2 Error Status, 76h: Bank3 Error
Status
2. The input of the program data can be done only in Busy state of Erase operation.
Rev.4.00, Jun.20.2004, page 9 of 89
HN29V1G91T-30
Device Operation
Page Read
It becomes Busy state with WE rising edge after writing 00h along with four address cycles and 30h and
data transfer starts from memory array to the data register. The device output the data serially from
specified column address when inputting address by the repetitive high to low transition of the RE clock
after it is Ready state.
It is possible to shorten Busy time after the 2nd page when the data of page overlapped to 4 bank
consecutively like Page 0, Page1, Page 2, Page 3 is read out (Please see 4 page read below).
The data of Page 1 to Page 3 are transferred to the data register when writing 00h and 30h specifying
column address and Page 0.
The device output the data of Page 0 serially by clocking RE after transferring it from memory array to the
data register.
The data of Page 1, Page 2, Page 3 which are transferred to the data register can be output using Page data
out command (06h/E0h) after the data of Page 0 output.
Rev.4.00, Jun.20.2004, page 10 of 89
HN29V1G91T-30
CLE
CE
WE
ALE
RE
column address M Page address N
I/O
00h
CA1
CA2
RA1
RA2
30h
M
M+1
M+2
Page address N
tR
R/B
Busy
Page N
Memory array
Data register
M
4page read
tR
(A)
(B)
R/B
pageN
column J N=0,4,8,12...
pageN
DOUT DOUT
columnK
pageN+1
I/O
00h CA1 CA2 RA1 RA2 30h
06h CA1 CA2 RA1 RA2 E0h DOUT
(3)
DOUT
(1)
(2)
R/B (A)
columnL
pageN+2
columnM pageN+3
I/O (B)
06h CA1 CA2 RA1 RA2 E0h DOUT
(4)
DOUT
06h CA1 CA2 RA1 RA2 E0h DOUT
DOUT
(5)
Bank 0
Bank 1
Bank 2
Bank 3
Page N
Page N+1
Page N+2
Page N+3
Memory array
Data register
(1)
Bank 0
Page N
Bank 1
Bank 2
Bank 3
Page N+1
Page N+2
Page N+3
Memory array
Data register
column J
column K
column L
column M
(2)
(3)
(4)
(5)
Rev.4.00, Jun.20.2004, page 11 of 89
HN29V1G91T-30
Random Data output in a Page Read
When the device output the data serially in Page read mode operation, the data from any column address in
a Page which is reading can be output by writing 05h and E0h with two column address cycles.
There is no restriction on an order of column address which can be specified and it is possible to specify
many times including same column address in the same Page address.
CLE
CE
WE
ALE
RE
Column
address L address N
Page
Column
address M
pageN
L
pageN
M M+1 M+2
I/O
00h CA1 CA2 RA1 RA2 30h
L+1 L+2
05h CA1 CA2 E0h
R/B
Page N
Memory array
Data register
L
M
Rev.4.00, Jun.20.2004, page 12 of 89
HN29V1G91T-30
Multi Bank Read
Multi Bank Read operation enables to read the data of any Page address in 4 bank. Writing 00h command
with four address cycles can be specified to maximum 4 Bank. There is no restriction on an order of a
Bank to specify.
Page address specified later becomes effective when it is specified twice in the same Bank.
The device become Ready state at rising edge of WE after writing 31h command with specifying address
and the data transfer from the memory array to the data register is started.
After it becomes Ready state, it executes specifying a bank for read and column address for starting read by
writing 06h and E0h command with four address cycles. After that the device output the data serially from
column address which is specified by clocking RE. It is possible to specify any bank for read and to read
the data which is transferred to the data register repeatedly.
tR
(A)
R/B
column J
page N
column K
page P
column L
page Q
column M
page R
column J’
page N
column K’
page P
(B)
DOUT
00h Address 00h Address 00h Address 00h Address 31h
06h Address E0h DOUT
DOUT
06h Address E0h DOUT
I/O
Bank2
Bank0
Bank1
Bank0
Bank1
Bank3
(1)
(2)
(3)
(A)
R/B
column L’
page Q
column M’
page R
06h Address E0h DOUT
DOUT
06h Address E0h DOUT
DOUT
I/O(B)
Bank2
Bank3
(4)
(5)
Bank 0
Page N
Bank 1
Page P
Bank 2
Page Q
Bank 3
Page R
Memory array
Data register
(1)
Bank 0
Page N
Bank 1
Page P
Bank 2
Page Q
Bank 3
Page R
Memory array
Data register
column J’
column K’
column L’
column M’
(2)
(3)
(4)
(5)
Note: 1. (2) (3) (4) (5): repeatable
Rev.4.00, Jun.20.2004, page 13 of 89
HN29V1G91T-30
Multi Bank Read Random Data output
The data can be read out setting column address freely on the way to the read operation of Page address
data in each Bank in Multi Bank Read operation. It is possible to read out the data by writing 05h and E0h
command with two column address cycles. There is no restriction to specify any column address and it is
possible to specify it including same one in the same page address many times.
tR
(A)
R/B
column J
page N
column K
page P
column L
page Q
column M
page R
column J’
page N
column J’’
(B)
DOUT
00h Address 00h Address 00h Address 00h Address 31h
06h Address E0h DOUT
DOUT
05h Address E0h DOUT
I/O
(1)
(2)
R/B
(C)
(D)
(A)
column K’
page P
column L’
page Q
column K’’
column L’’
I/O
(B) 06h Address E0h DOUT
DOUT
05h Address E0h DOUT
DOUT
06h Address E0h DOUT
DOUT
05h Address E0h DOUT
DOUT
(3)
(4)
R/B
(C)
column M’
page R
column M’’
I/O
(D) 06h Address E0h DOUT
DOUT
05h Address E0h DOUT
DOUT
(5)
Bank 0
Bank 1
Page P
Bank 2
Page Q
Bank 3
Page R
Page N
Memory array
Data register
(1)
Bank 0
Page N
Bank 1
Page P
Bank 2
Bank 3
Page R
Memory array
Data register
Page Q
column J’
column K’
column L
’
column M’
(2)column J’’
(3)
(4)
(5)
column K’’
column L’’
column M’’
Note: 1. (2) (3) (4) (5): repeatable
Rev.4.00, Jun.20.2004, page 14 of 89
HN29V1G91T-30
Page Program
Page program operation enables to write the data into one Page address. The data is stored into the data
register after writing 80h command with four address input (Column address, Page address) and data input.
It is also stored serially from column address which is input and then automatic program operation starts
after writing 10h command (Program command). Program operation must be executed to a Page address
which the data is erased. A number of additional program in the same Page address is maximum 8 times.
Rev.4.00, Jun.20.2004, page 15 of 89
HN29V1G91T-30
Page Program Random Data input in a Page
This operation enables to input the program data in the Page address randomly writing 85h command with
two column address input on the way to the program operation in the Page program mode.
It can input the data by specifying a column address in the same page which you want to program the data
using this mode.
After completion of the data input, program it to the specified column address is executed automatically by
writing 10h command (Program start command). Program operation must be executed to a Page address
which the data is erased.
A number of additional program in the same Page address is maximum 8 times.
The data of 1 byte or more need to be input when it is in random data input.
CLE
CE
WE
ALE
RE
Column
Page
Column
address L address N
address M
I/O
80h CA1 CA2 RA1 RA2
DIN DIN
DIN
85h CA1 CA2 DIN DIN
DIN
10h
70h status
tPROG
R/B
Page N
Memory array
Program
Data register
L
M
Rev.4.00, Jun.20.2004, page 16 of 89
HN29V1G91T-30
Multi Bank Page Program
It is possible to program the data to any one page address in each bank simultaneously since this device
adopts 4 bank structure. The bank to be programmed the data is chosen from 1 bank to maximum 4 bank.
Address and data for next bank can be input consecutively by writing 11h command (dummy command)
after writing 80h command with column and page address, data as well as usual page program.
Program operation to several banks specified automatically are executed simultaneously by writing 10h
command (program start command) after data input to the maximum 4 bank completes.
tDBSY
tDBSY
R/B
(A)
(B)
column J
page N
column K
page P
I/O
80h CA1 CA2 RA1 RA2
DIN
DIN 11h
80h CA1 CA2 RA1 RA2
DIN
Bank1
DIN 11h
(2)
(1)
Bank0
R/B
tDBSY
tPROG
(A)
column L
page Q
column M
page R
I/O
(B)
status
out
80h CA1 CA2 RA1 RA2
DIN
DIN 11h
80h CA1 CA2 RA1 RA2
DIN
DIN 10h
71h
Bank2
(4)
Bank3
(3)
Bank 0
Page N
Bank 1
Page P
Bank 2
Page Q
Bank 3
Page R
Memory array
Data register
Program
Program
(5)
(5)
(5)
(5)
Program
Program
column J
column K
column L
column M
(1)
(2)
(3)
(4)
Rev.4.00, Jun.20.2004, page 17 of 89
HN29V1G91T-30
Multi Bank Page Program Random Data Input in a Page
This mode enables to input program data specifying an address in a page which the data is programmed
when it is in Multi Bank Page Program operation. The data can be input serially by writing 85h command
with column address to on the way to the data input to the page address to be programmed as well as
random data input in page mode. After the data input, program and address/data input to next bank is
executed by writing 11h command (dummy command) and then 80h command as well as Multi Bank Page
Program.
Program operation to several banks specified automatically is executed simultaneously by writing 10h
command (program start command) after the completion of data input to the final bank.
Address of the random data can be set in every page for program freely.
tDBSY
(A)
(B)
R/B
page N
80h CA1 CA2 RA1 RA2
column J
column J’
D
DIN
85h CA1 CA2
DIN
DIN 11h
I/O
IN
(1)
Bank0
tDBSY
(A)
(C)
(D)
R/B
page P
80h CA1 CA2 RA1 RA2
column K
column K’
(B)
D
DIN
85h CA1 CA2
DIN
DIN 11h
I/O
IN
(2)
Bank1
tDBSY
(C)
(E)
(F)
R/B
column L’
column L
page Q
(D)
80h CA1 CA2 RA1 RA2
D
DIN
85h CA1 CA2
DIN
DIN 11h
I/O
IN
(3)
Bank2
tPROG
(E)
R/B
page R
column M’
column M
status
out
(F)
80h CA1 CA2 RA1 RA2
D
DIN
85h CA1 CA2
DIN
DIN 10h
71h
I/O
IN
(5)
(4)
Bank3
Bank 2
Page Q
Bank 3
Bank 0
Page N
Bank 1
Page P
Page R
(5)
Memory array
Data register
Program
Program
(5)
Program
(5)
(5)
Program
column L
column L’
column M
column M’
column J
column J’
column K
column K’
(1)
(2)
(3)
(4)
Rev.4.00, Jun.20.2004, page 18 of 89
HN29V1G91T-30
Cache Program
Cache program operation enables to use the data register of the bank which do not program as the cache
register.
The program data for next page address is transferred to Flash memory from external data buffer by using
the cache register while programming the primary data.
Setup for program starts after writing 15h command following 80h command and program address/data
transfer.
After that the device is in the Busy state. The data register of the bank which do not program is cleared
when program operation inside the device starts and then it is ready to receive the data of next page
address.
In this case next page address must be different page address of the bank with one which programs just
before.
It is prohibited to program the data to page address in same bank consecutively using cache program.
Next page address for program should specify one in different bank.
The data of next page address can be transferred to Flash memory by writing 80h command as well as the
data transfer of the1st page address and then 15h command (program dummy command) input is required
after program address/data input. It becomes Busy state until the program operation to the 1st page address
completes and the data of data register is cleared. If the program operation to the 1st page address does not
complete, it becomes Busy state until the data of data register except for one of the bank which programs
next.
70h command is issued to find out the status in cache program operation after Ready/Busy becomes Ready.
The True Ready/Busy status (I/O5) in cache program becomes busy when CPU is active and shows that the
internal program operation is in the process. The True Ready/Busy status (I/O6) should be verified to find
out the program completion if 15h command is used for the last programming. Reset operation is required
by writing FFh when program operation completes using 15h command and moves to the other operation
except for cache program. Reset operation is not required if 10h command (program start command) is
used for the last programming.
tCBSY
tCBSY
tCBSY
(A)
(B)
R/B
Address,
Data
Address,
Data
Address,
Data
3rd page
15h
80h
(3)
15h
I/O
80h
(1)
70h
Status
70h
(4)
Status
80h
15h
2nd page
1st page
(2)
(5)
tCBSY
tCPROG
tCBSY
R/B (A)
Address,
Data
Address,
Data
Address,
Data
15h
80h
15h
I/O (B) 80h
70h
Status
70h
Status
80h
10h
70h
Status
(M+1) th page
M th page
(M-1) th page
(7)
(8)
Bank 0
Page N
Bank 1
Bank 2
Bank 3
Page Q
Page P
(4)
Page R
(8)
Memory Array
Program
Program (6)
(2)
Program
Program
Data Register
(1)
(3)
(5)
(7)
Rev.4.00, Jun.20.2004, page 19 of 89
HN29V1G91T-30
2page Cache Program
2 page cache program operation is available using both Multi Bank Program and Cache Program operation.
It enables to input the program data for the address of next bank consecutively by writing 11h command
(dummy command) following 80h command and program address/data input. Setup for program starts by
writing 15h command after data input and then the device is in the Busy state (tCBSY). The data registers of
two banks which do not program are cleared when program operation inside the device starts and then it is
ready to receive the data of next two page address.
In this case next two page address must be different page address of the bank with ones which programs
just before.
Rev.4.00, Jun.20.2004, page 20 of 89
HN29V1G91T-30
Copy Back Program
Copy Back Program operation enables to copy the data to different page address of same bank without
taking it to external data register. The data transfer to the data register is started to copy memory array data
of 1 page address writing 35h command following 00h command and address input with 4 cycles. Then
copy of the data is started by writing 10h command following 85h command and address with 4 cycles for
post-copy. Address for post-copy must be chosen page address which has erased (FFh).
CLE
CE
WE
ALE
RE
Column
Page
Column
Page
address J address M
address K address N
I/O
00h CA1 CA2 RA1 RA2 35h
85h CA1 CA2 RA1 RA2 10h
70h
status
tPROG
R/B
(1)
(2)
Bank 0
Bank 1
Bank 2
Bank 3
Page M
(1)
Memory array
Data register
Bank 0
Bank 1
Bank 2
Bank 3
Page N
Program
Memory array
Data register
(2)
Note: 1. Post copy address must be specified one in same bank.
Rev.4.00, Jun.20.2004, page 21 of 89
HN29V1G91T-30
Copy Back Program with Random Data Input In a Page
Source copy data which has transferred to the data register can be updated when copy back program
operation is executed.
Memory array data which has taken out to the data register is updated to the input data after storing source
copy data to the data register and inputting the data following 85h command and 4 address input with 4
cycles. 1 byte data or more must be input when random data input is executed. Program to post-copy page
address is executed by writing 10h command after data input.
Address for post-copy must be chosen page address which has erased (FFh).
CLE
CE
WE
ALE
RE
Column
Page
Column
Page
Column
address J address M
address K address N
address L
I/O
00h CA1 CA2 RA1 RA2 35h 85h CA1 CA2 RA1 RA2 DIN
DIN 85h CA1 CA2 DIN
DIN 10h
70h status
(2)
R/B
(1)
(3)
Bank 0
Bank 1
Bank 2
Bank 3
Page M
(1)
Memory array
Data register
Bank 0
Bank 1
Bank 2
Bank 3
Memory array
Data register
(2)
column L
DIN
column K
DIN
Bank 0
Bank 1
Bank 2
Bank 3
Page N
Memory array
Data register
Program
(3)
Note: 1. Post copy address must be specified one in same bank.
Rev.4.00, Jun.20.2004, page 22 of 89
HN29V1G91T-30
Copy Back Program with Data Output
When copy back program operation is executed, it is possible to confirm the source copy data outputting
one which has transferred to the data register to external. It is possible to output the source copy data after
storing it to the data register and inputting E0h command following 06h command and address input with 4
cycles. Program to post-copy page address is executed by writing 10h command following 85h command
and post copy address input with 4 cycles after data output. Address for post-copy must be chosen page
address which has erased (FFh). Copy data can be updated after post copy address input with 4 cycles and
the data input.
R/B
column J page M
column J’ page M
column K page N
status
70h
out
00h CA1 CA2 RA1 RA2 35h
06h CA1 CA2 RA1 RA2 E0h DOUT DOUT 85h CA1 CA2 RA1 RA2 10h
I/O
(1)
(2)
(3)
Bank 0
Bank 1
Bank 1
Bank 2
Bank 2
Bank 3
Bank 3
Page M
(1)
Memory array
Data register
Bank 0
Memory array
Data register
column J’
DOUT
(2)
Bank 0
Page N
Bank 1
Bank 2
Bank 3
Memory array
Data register
Program
(3)
Note: 1. Post copy address must be specified one in same bank.
Rev.4.00, Jun.20.2004, page 23 of 89
HN29V1G91T-30
Copy Back Program with Data Output and Random Data Input in a Page
(A)
(B)
R/B
column J page M
00h CA1 CA2 RA1 RA2 35h
(1)
column J’ page M
column K page N
06h CA1 CA2 RA1 RA2 E0h DOUT DOUT 85h CA1 CA2 RA1 RA2 DIN
DIN
I/O
(2)
(3)
(A)
(B)
R/B
column L
status
70h
out
I/O
85h CA1 CA2 DIN
(4)
DIN 10h
(5)
Bank 0
Bank 1 to 3
Bank 0
Bank 1 to 3
Page M
(1)
Memory array
Memory array
Data register
Data register
DIN
DIN
column K
(3)
column L
(4)
Bank 0
Bank 0
Bank 1 to 3
Bank 1 to 3
Page N
Memory array
Data register
Memory array
Data register
Program
(5)
column J’
(2)
DOUT
Note: 1. Post copy address must be specified one in same bank.
Rev.4.00, Jun.20.2004, page 24 of 89
HN29V1G91T-30
Multi Bank Copy Back Program
Multi Bank Copy Back Program enables to execute copy back program to a multiple bank simultaneously.
The data is transferred to the data register from memory array simultaneously by writing 35h command
after specifying post copy address consecutively. Data read and update can be executed as well as copy
back program.
(A)
R/B
page N
page P
page Q
page R
00h CA1 CA2 RA1 RA2
00h CA1 CA2 RA1 RA2
00h CA1 CA2 RA1 RA2
00h CA1 CA2 RA1 RA2
35h
(B)
I/O
(1)
Bank0
Bank1
Bank2
Bank3
R/B (A)
page N’
85h CA2 CA1 RA1 RA2 11h
page P’
85h CA1 CA2 RA1 RA2 11h
page Q’
85h CA1 CA2 RA1 RA2 11h
page R’
85h CA1 CA2 RA1 RA2 10h
status
out
I/O (B)
71h
(2)
Bank 0
Bank 1
Page P
Bank 2
Page Q
Bank 3
Page R
Page N
(1)
Memory array
Data register
(1)
(1)
(1)
Bank 0
Page N’
(2)
Bank 1
Bank 2
Page Q’
Bank 3
Page R’
Program
Page P’
(2)
Memory array
Data register
(2)
Program
Program
Program
(2)
Rev.4.00, Jun.20.2004, page 25 of 89
HN29V1G91T-30
Data Recovery Read
Data recovery read enables to output the data itself which is transferred from external after program
completion.
It is possible to read out the data which is programmed by writing E0h command following 06h command
and read address input with 4 cycles. It is also possible to read out the data of any column address in same
page address by writing E0h command following 05h command and column address input with 2 cycles on
the way to outputting the data by clocking RE.
R/B
column L Page M
column N
10h
06h CA1 CA2 RA1 RA2 E0h DOUT
DOUT
05h CA1 CA1 E0h DOUT
DOUT
I/O
Page M
(1)
(2)
(3)
Page M
Program
(1)
Memory array
Data register
Memory array
Data register
column L
Dout
column N
Dout
(2)
(3)
Rev.4.00, Jun.20.2004, page 26 of 89
HN29V1G91T-30
Data Recovery Program
Data recovery program enables to re-program the program data itself which is transferred from external to
different page address in same bank. Program to newly specified page address is executed by writing 10h
command following 85h command and address for re-programming with 4 cycles as well as copy back
program. Same page address cannot be chosen during this operation.
It is possible to update the re-program data by inputting the data after specifying address for re-
programming.
Address for re-programming must be chosen page address which has erased (FFh).
t
t
PROG
PROG
R/B
column K
Page N
status
out
10h
85h CA1 CA2 RA1 RA2
10h
70h
I/O
Page M
(2)
(1)
Page N
(2)
Memory array
Data register
Page M
Program
(1)
Memory array
Data register
Program
Note: 1. Page M and Page N are different page address.
t
t
PROG
PROG
R/B
column K page N
column L
status
out
10h
85h CA1 CA2 RA1 RA2
DIN
DIN
85h CA1 CA2 DIN
DIN 10h
70h
I/O
(2)
(3)
(4)
(1)
Page N
(4)
Memory array
Data register
Page M
Program
(1)
Memory array
Data register
Memory array
Data register
Program
Din
column K
(2)
Din
column L
(3)
Note: 1. Page M and Page N are different page address.
It is possible to combine erasing the data of the block with re-programming, as shown below, in the data
recovery program operation.
Rev.4.00, Jun.20.2004, page 27 of 89
HN29V1G91T-30
To program, update the data next, then erase, and then re-programming.
R/B
t
PROG
Status
Check
80h
CA × 2 RA × 2 Data
10h
85h
CA × 2 RA × 2 Data
85h
CA × 2 Data
I/O
Program1
1
*1 Program 1 data update specify a page program
2
R/B
t
t
BERS
PROG
Status
Check
Program
Status
I/O
60h
3
RA × 2 D0h
Erase
85h
CA × 2 RA × 2
10h
Program2 Start
70h
Specify the address for
re-programming (same as *1)
Specify a page in the same bank
same as RA in setting 1.
Program2
4
1
2
3
4
Page M
Page N, N+4
Erase
Program1
Program2
col.K col.L
60h−RA2−D0h
data update
80h−CA1−RA1−Data−10h
85h−CA2−RA2−10h
85h−CA2−RA2−Data−85h−CA3−Data
RA1 = PageM
RA2 = PageN
CA2 = col.K
CA3 = col.L
To program, erase next, then update the data, and then re-programming.
R/B
t
t
BERS
PROG
Status
out
Status
out
80h
CA × 2 RA × 2 Data
10h
70h
60h
RA × 2
D0h
70h
I/O
Erase
Program1 *1
1
2
Within the same bank
as the page specified in *1
R/B
t
PROG
Status
I/O
85h
CA × 2 RA × 2 Data
85h
CA × 2 Data
10h
Program2 Start
4
70h
out
Program
3
Specify the address for re-programming
(in the same bank as *1)
1
2
3
4
Page M
Page N
Program1
Program2
10h
Erase
col.K col.L
data update
60h−RA2−D0h
80h−CA1−RA1−Data−10h
85h−CA2−RA2−Data−85h−CA3−Data
RA2 = PageN
RA1 = PageM
CA2 = col.K
CA3 = col.L
Rev.4.00, Jun.20.2004, page 28 of 89
HN29V1G91T-30
Program Data Input in Erase Busy
Program Data input in Erase Busy enables to program the data of any page address during busy status in
erase operation.
It is possible to program the data in both block erase mode and multi bank block erase mode if they are in
busy state.
There is no restriction between page address for programming and block for erase.
It needs 1µs wait time after the erase status becomes busy to write 80h command for program address and
data input.
It can confirm the status by writing 70h or 71h command after program data input.
The input data is possible to input in both single bank and multi bank mode and corresponds to the data
input mode specifying column address in same page address. It needs to keep 4µs or more from writing
11h command to writing 80h command when the data to a multiple bank is programmed. 10h command
(program start command) must be issued after completion of erase operation.
Program data input in single bank
Note: 1. Status command available
Program data input with random data mode in single bank mode
Note: 1. Status command available
Rev.4.00, Jun.20.2004, page 29 of 89
HN29V1G91T-30
Program data input in multi bank program mode (In case of completing data input during busy
status)
Note: 1. Status command available
Program data input in multi bank program mode (In case of not completing data input during busy
status)
Note: 1. Status command available
The correspondence when the erase error occurred in Program Data Input in Erase Busy mode.
In the Program Data Input in Erase Busy mode, after an erase error occurred in one block at a two-blocks
simultaneous erase operation, a certain operation is needed in a particular case. In case of an erase
operation of one block in the same bank as the error-occurred block, the reset command FFh is needed just
before, as shown in Figure 1.
Otherwise, an illegal two-blocks erase operation will be executed, because the address data of two pages to
program remains.
After the one-block erase operation succeed, it is possible to program by specifying the address to program
again with the command 85h, because the data to be programmed stored in the buffer is maintained.
Rev.4.00, Jun.20.2004, page 30 of 89
HN29V1G91T-30
Program Data Input in Erase Busy (recommend pattern when error occurred) Multi Bank Mode
R/B
t
BERS
Erase
Status
RA × 2
Block0 (Bank0),
RA × 2
CA × 2 RA × 2
CA × 2 RA × 2
60h
60h
D0h
80h
Data
11h
80h
Data
70h
I/O
*2 Specify a page program
1
*1 Specify a page program
Page0 (Bank0)
2
Page1 (Bank1)
Error only Block0
(Bank0)
Erase Block1 (Bank1)
1
1
t
DBSY
R/B
t
t
PROG
BERS
Erase
Status
I/O
RA × 2
CA × 2 RA × 2
CA × 2 RA × 2
60h
4
D0h
70h
85h
11h
85h
10h
FFh
Specify the address (same as *1, *2)
again for programming
Pass
5
Reset
address
3
Block2 in Bank0 erase execute
5
infornation
1
2
3
4
5
Bank0
Block0
Bank1
Bank0
Block2
Bank1
Bank0
Bank1
Block1
Block1
Block1
FFh
Block0
erase error
command
Address
reset
Block2
Erase
Program
Program
Erase
Erase
Data0
Data1
Data0
Data1
Data0
Data1
80h–CA0–RA0
–(Data0)–11h
80h–CA0–RA1
–(Data1)
60h–RA2–D0h
(erase only block2)
85h–CA0–RA2 85h–CA0–RA1
–11h –10h
It is not necessary to reset by command FFh, when transmit the writing data in erase block and 1 page in
same bank, and execute writing during erasing 1 block data, or erasing error occurs and erasing another
block in same bank. But in this case, as shown in following figure, it is necessary to specify the address for
re-programming, after erasing another block address.
Write address specifying it by command 85h at the address for re-programming in the same bank, when
writing it as shown in following figure.
Program Data Input in Erase Busy (recommend pattern when error occurred) Single Bank Mode
R/B
t
t
BERS
BERS
Erase
Status
60h
RA × 2 D0h
80h
CA × 2 RA × 2 Data
70h
60h
RA × 2 D0h
I/O
*1 Specify a page program
Another address in Same Bank
(same as *1) erase execute input
error
R/B
t
PROG
Status
Check
Program
Status
70h
85h
CA × 2 RA × 2
10h
70h
I/O
Specify the address (same as *1)
for re-programming
Pass
Rev.4.00, Jun.20.2004, page 31 of 89
HN29V1G91T-30
Block Erase
Erase operation for one block which is consisted of 2 page can be executed. One block is consisted of
pageN and page(N+4)
(Ex: page0 and page4, page1 and page5).
Input page address (A14 = VIL) in lower side, when erase block address input.
Multi Block Erase
Erase operation for one block in maximum 4 bank is executed simultaneously. Any block in a bank can be
chosen. Input page address (A14 = VIL) in lower side, when erase block address input.
Page mode Erase Verify
Whether any one page address is erased or not is verified in this mode. Verification starts internally inside
the device after writing D2h command after 60h command and row address input. It can be verified
whether the page address is erased or not after by writing 70h command (status read command) after it
becomes ready.
Block mode Erase Verify
Whether any one block is erased or not is verified in this mode. Verification starts internally inside the
device after writing D3h command after 60h command and row address input. It can be verified whether
the block is erased or not after by writing 70h command (status read command) after it becomes ready.
Multi Bank Page mode Erase Verify
Page mode erase verify for each page in maximum 4bank is executed. It can be verified whether page
address in each bank is erased or not by writing 71h command (status read command) after it becomes
ready.
Multi Bank Block mode Erase Verify
Block mode erase verify for each block in maximum 4bank is executed. It can be verified whether the
block in each bank is erased or not by writing 71h command (status read command) after it becomes ready.
Read ID
ID code can be read out by inputting the address (00h) after writing 90h command.
Manufacturer code (07h) and Device code (01h) can be read out serially by clocking RE.
Rev.4.00, Jun.20.2004, page 32 of 89
HN29V1G91T-30
Power on Auto Read
The data of the lowest page address can be read out serially without command and address input after
power is on.
Power on auto read mode is activated when VCC reaches about 2.7V. It is enabled only when PRE pin is
tied to VCC.
PRE pin must be connected to VCC when using power on auto read and VSS when not using it.
After power on auto read is executed, reset operation is required by reading out 1 page (2112 byte) data or
writing FFh command.
Note: Please contact Renesas Technology’s sales office before using this mode.
Rev.4.00, Jun.20.2004, page 33 of 89
HN29V1G91T-30
Status Read at Read mode
The content of status register can be read out writing 70h command (status read command) and by clocking
RE in read operation. The data of memory array cannot be read out even by clocking RE since status read
mode is set after the device becomes ready. 7Fh command needs to be written in case of releasing status
read mode in read operation.
The data of memory array can be read out without address input in this operation.
Operation status of status register
Operation status can be output by status read.
Command
70h
Output
Single bank operation status
71h
Multi bank operation status
72h
Single bank operation error status
Multi bank operation bank0 error status
Multi bank operation bank1 error status
Multi bank operation bank2 error status
Multi bank operation bank3 error status
73h
74h
75h
76h
Rev.4.00, Jun.20.2004, page 34 of 89
HN29V1G91T-30
Status Register check flow (single bank operation)
Start
70h Write
read status register
NO
I/O7=1
or
R/B=1
YES
NO
I/O1=0
YES
72h Write
read errorstatus register
NO
I/O6=1
YES
Fail
Fail
Read ECC check
Not 1 bit error
ECC possible
1 bit error
Program/erase completed
70h command status in single bank operation
status
Program/Erase
Write protect
Ready/Busy
Ready/Busy
Not Used
Cache Program
Write protect
Ready/Busy
True Ready/Busy*1
Not Used
Output
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
Protect: 0 Not Protect: 1
Ready: 1 Busy: 0
Ready: 1 Busy: 0
0
Not Used
Not Used
0
Not Used
Not Used
0
Not Used
Pass/Fail (N-1)
Pass/Fail (N)
0 / Pass: 0 Fail: 1 (cache program)
Pass: 0 Fail: 1
Pass/Fail
Note: 1. True Ready/Busy shows Ready/Busy status of CPU
(R/B output status is same as I/O7).
Rev.4.00, Jun.20.2004, page 35 of 89
HN29V1G91T-30
72h command status in single bank operation
status
Output
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
Write protect
Ready/Busy
Program/Erase ECC check
Erase check
Program check
Not Used
Protect: 0 Not Protect: 1
Ready: 1 Busy: 0
Ecc available: 1 Ecc Not available: 0
Pass: 0 Fail: 1
Pass: 0 Fail: 1
0
Not Used
0
Pass/Fail
Pass: 0 Fail: 1
Status Register check flow (Multi bank program/erase)
Start
71h Write
read status register
NO
I/O7=1
R/B=1
or
YES
I/O1=0
YES
NO
Error bank check
73-76h Write
read errorstatus register *1
NO
Fail
Fail
I/O6=1
YES
Note:1.
Read ECC check
73h:Bank0 error status
74h:Bank1 error status
75h:Bank2 error status
76h:Bank3 error status
Not 1 bit error
NO
ECC possible
1 bit error
Error bank check end
YES
Program/erase completed
Rev.4.00, Jun.20.2004, page 36 of 89
HN29V1G91T-30
71h Command Status in Multi Bank Operation
status
Output
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
Write protect
Protect: 0 Not Protect: 1
Ready: 1 Busy: 0
Ready: 1 Busy: 0
Pass: 0 Fail: 1
Pass: 0 Fail: 1
Pass: 0 Fail: 1
Pass: 0 Fail: 1
Pass: 0 Fail: 1
Ready/Busy
Ready/Busy
Bank3 Pass/Fail
Bank2 Pass/Fail
Bank1 Pass/Fail
Bank0 Pass/Fail
All Pass/Fail
73h, 74h, 75h, 76h Command Status in Multi Bank Operation / Cache program / 2page cache
program
status
Output
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
Write protect
Ready/Busy
Program/Erase ECC check
Erase check
Program check
Not Used
Protect: 0 Not Protect: 1
Ready: 1 Busy: 0
Ecc available: 1 Ecc Not available: 0
Pass: 0 Fail: 1
Pass: 0 Fail: 1
0 (Don't care)
Not Used
0 (Don't care)
Pass/Fail
Pass: 0 Fail: 1
Rev.4.00, Jun.20.2004, page 37 of 89
HN29V1G91T-30
Status Register check flow (Cache program operation)
Start
70h Write
read status register
NO
I/O7=1
or
R/B=1
YES
YES
Cache program
pass
Program command
10h or 15h
I/O1=0 & I/O2=0
NO
10h
(Last program)
15h
NO
I/O2=0
70h Write
read status register
YES
NO
I/O6=1
YES
Next cache program
71h Write
read status register
I/O2-5
check
73-76h Write
read errorstatus register
NO
I/O6=1
YES
ECC may be possible
ECC impossible
Error bank
check end
NO
YES
FFh Write
cache mode clear
NO
ECC may be possible
YES
Read ECC check
Next bank
Cache program error so
substitute operation
NO
ECC possible
YES
NO
Error bank operate end
YES
Cache program end
Rev.4.00, Jun.20.2004, page 38 of 89
HN29V1G91T-30
Status Register (Cache program operation)
The status is output by writing 70h command in cache program / 2 page cache program operation.
I/O1, 2 which shows pass/fail and I/O6, 7 which shows Ready/Busy is output OR data of 2 page address
which programs simultaneously. In other words, if either 2 page address is Busy status, I/O6 or I/O7
outputs “0”. If either 2 page address fails, I/O1 or I/O2 outputs “1”.
It verifies the status writing 70h command in cache program operation and verification of detail error code
which page address fails in program is executed by writing 73h-76h command which output error content
corresponding to bank address.
It can also verify the status writing 70h in 2 page cache program operation and if either 2 page address
which programs simultaneously fails with program error, it outputs fail status. We recommend verifying
page address writing 71h command.
If error occurs in (N-1) page address, error management of (N-1) page (taking the data to replacement page
address) address needs to be executed after program completion of N page address.
70h command status in Cache program / 2page cache program operation
status
Output
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
Write protect
Ready/Busy
True ready/Busy*1
Not Used
Protect: 0 Not Protect: 1
Ready: 1 Busy: 0
Ready: 1 Busy: 0
0
Not Used
0
Not Used
0
Pass/Fail (N-1)
Pass/Fail (N)
Pass: 0 Fail: 1
Pass: 0 Fail: 1
Note: 1. True Ready/Busy shows Ready/Busy status of CPU.
71h command status in 2page cache program operation
status
Output
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
Write protect
Protect: 0 Not Protect: 1
Ready: 1 Busy: 0
Ready: 1 Busy: 0
Pass: 0 Fail: 1
Pass: 0 Fail: 1
Pass: 0 Fail: 1
Pass: 0 Fail: 1
Pass: 0 Fail: 1
Ready/Busy
Ready/Busy
Bank3 Pass/Fail (N or N-1)
Bank2 Pass/Fail (N or N-1)
Bank1 Pass/Fail (N or N-1)
Bank0 Pass/Fail (N or N-1)
Pass/Fail (N or N-1)
Rev.4.00, Jun.20.2004, page 39 of 89
HN29V1G91T-30
73h, 74h, 75h, 76h command status in Cache program / 2page cache program operation
status
Output
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
Write protect
Protect: 0 Not Protect: 1
Ready: 1 Busy: 0
Ecc available: 1 Ecc Not available: 0
Pass: 0 Fail: 1
Pass: 0 Fail: 1
0
Ready/Busy
Program/Erase ECC check (N or N-1)
Erase check (N or N-1)
Program check (N or N-1)
Not Used
Pass/Fail (N-1)
Pass: 0 Fail: 1
Pass: 0 Fail: 1
Pass/Fail (N)
Rev.4.00, Jun.20.2004, page 40 of 89
HN29V1G91T-30
Reset operation
This device can enter standby mode interrupting each operation mode by writing FFh command (reset
command) during each operation. Page address data during program operation, block data during erase
operation are not guaranteed after completing reset operation.
Reset operation in the Cache program (R/B = Ready, True R/B = Busy)
I/O
80h
15h
FFh
R/B
t
RSTP
Reset operation in the Cache program (R/B = Ready, True R/B = Busy)
I/O
80h
15h
R/B
RES
t
RSTP
t
min
RSTP
Reset operation in the Erase Verify
D2h/D3h
I/O
60h
FFh
R/B
t
RSTEV
Reset operation in the Erase Verify
D2h/D3h
I/O
60h
R/B
RES
t
RSTEV
t
min
RSTEV
Rev.4.00, Jun.20.2004, page 41 of 89
HN29V1G91T-30
Reset operation in the Program
I/O 80h/85h
10h/15h
FFh
00h
R/B
Program busy
Program start
tRSTP
tRSTE
tRSTR
Reset operation in the Erase
I/O
60h
D0h
FFh
00h
R/B
Erase busy
Erase start
Reset operation in the Read
I/O
00h
30h/31h/35h
FFh
00h
R/B
Read busy
Read start
This device can enter deep standby mode interrupting each operation mode by making RES pin low during
each operation.
Page address data during program operation, block data during erase operation are not guaranteed after
completing reset operation.
Reset operation in the Program
I/O 80h/85h
10h/15h
R/B
Program busy
Program start
tRSTP
RES
1
*
tRSTP min
Note: 1. Power on sequence.
Rev.4.00, Jun.20.2004, page 42 of 89
HN29V1G91T-30
Reset operation in the Erase
60h
D0h
I/O
R/B
Erase busy
Erase start
tRSTE
1
RES
*
tRSTE min
Note: 1. Power on sequence.
Reset operation in the Read
00h
30h/31h/35h
I/O
R/B
Read busy
Read start
1
tRSTR
*
RES
tRSTR min
Note: 1. Power on sequence.
Rev.4.00, Jun.20.2004, page 43 of 89
HN29V1G91T-30
Usage for WP
WP at the low level prohibits the erase operation and the program operation. When use WP, use it as
follows.
Program operation
WE
I/O
80h/85h
10h/15h
WP
R/B
tWWS
tWWH
Prohibition of the Program operation
WE
I/O
80h/85h
10h/15h
WP
R/B
tWWS
tWWH
Rev.4.00, Jun.20.2004, page 44 of 89
HN29V1G91T-30
Erase operation
WE
I/O
60h
D0h/D2h/D3h
WP
R/B
tWWS
tWWH
Prohibition of the Erase operation
WE
I/O
60h
D0h/D2h/D3h
WP
R/B
tWWS
tWWH
Rev.4.00, Jun.20.2004, page 45 of 89
HN29V1G91T-30
Status Transition
PRE=L
V
CC
Deep Standby
(RES=L)
Power Off
PRE=H
Power On &
Power On
Power On Read
Reset Operation
Power On Read
2nd Access State
Operation
End
Reset
Operation
RES
=H→L
Any Operation
State
Deep Standby
RE
FFH or
2Kbyte Read
D
out
Status Register Read
70H to 76H
Status Read
State
Any State
RE
Status
Output
7Fh
ID Read
90H
RE
RE
ID Read Setup
Manufacture Code
Device Code
Any Command Input
ID Read Operation End
Read Address Setup
CA1
CA2
RA1
RA2
00H
Address
CA1
Setup
CA2
Setup
RA1
Setup
Input Setup
FFH
Memory Read Access Operation
30H, 31H
1st Access
End
2nd Access
State
SRAM Read Access
1st Access
RE
FFH
D
out
WE Input (Not Status Command)
2nd Access State End
Copy Back Program Operation1 (Read)
Standby
(RES=H,
CE=H)
CE
1st Access
End
35H
2nd Access
State
SRAM Read Access
1st Access
Output
disable
(CE=L)
RE
FFH
D
out
WE Input (Not Status Command)
2nd Access State End
Random Output Setup
CA1
CA2
CA2
RA1
CA2
Setup
RA2
RA1
Setup
06H
Address
Input Setup
CA1
Setup
FFH
Random Output Setup2
CA1
05H
Address
CA1
Input Setup
Setup
FFH
Random Output Operation
E0H
WE Input
2nd Access State End
2nd Access
State2
SRAM Read Access
RE
D
out
Deplete Recovery Operation
38H
Deplete
Recovery
FFH
Operation End
: BUSY Status
Rev.4.00, Jun.20.2004, page 46 of 89
HN29V1G91T-30
Erase Address Setup
Erase Verify Address Setup
RA1
60H
RA2
Address
RA1
Input Setup
Setup
FFH
Erase Operation
Erase
D0H
(Program Data
input available)
FFH
Operation End
Erase Verify Operation
D2H
Erase Verify
D3H
FFH
Operation End
Program Address Setup
80H
RA2
CE
CA1
CA2
RA1
RA1
80H
Address
CA1
CA2
Standby
(RES=H,
CE=H)
Input Setup
Setup
Setup
Setup
Output
disable
(CE=L)
FFH
Random Data Input Setup
85H
CA1
CA2
D
is need
85H
Address
Input Setup
CA1
Setup
in
at lowest 1Cycle
FFH
Dummy
Busy
11H
RA2/CA2
Setup
Data Input
State
Copy Back Program Operation2 (Program)
Data Recovery Program Setup
85H
RA2
CA1
CA2
RA1
RA1
Address
85H
CA1
CA2
Input Setup
Setup
Setup
Setup
FFH
Program Operation
10H
FFH
Program
Program
FFH
Operation End
Cache Program Operation
15H
FFH
Cache Program Standby
True Busy State
Operation End
WE
D
in
: BUSY Status
Rev.4.00, Jun.20.2004, page 47 of 89
HN29V1G91T-30
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
V
Notes
VCC voltage
−0.6 to +4.6
0
1
VSS voltage
VSS
V
All input and output voltage
Operating temperature range
Storage temperature range
Vin, Vout
Topr
−0.6 to +4.6
0 to +70
−25 to +85
V
1, 2
3
°C
°C
Tstg
Notes: 1. Relative to VSS
.
2. Vin/Vout = −2.0 V for pulse width with 20ns or less.
3. Device Storage temperature before programming.
Capacitance
Parameter
Symbol
Cin
Min
Typ
Max Unit
Test conditions
Input capacitance
Output capacitance
6
pF
pF
Vin = 0 V, Ta = +25°C, f = 1 MHz
Cout
10
Vout = 0 V, Ta = +25°C, f = 1
MHz
Valid Block
Parameter
Symbol
NVB0
Min
Typ
Max
Unit
Valid Block Number
Bank0
Bank1
Bank2
Bank3
8029
8029
8029
8029
8192
8192
8192
8192
blocks
blocks
blocks
blocks
NVB1
NVB2
NVB3
Spare Block
Parameter
Symbol
NSB0
Min
145
145
145
145
Typ
Max
Unit
Spare Block Number
Bank0
Bank1
Bank2
Bank3
blocks
blocks
blocks
blocks
NSB1
NSB2
NSB3
Rev.4.00, Jun.20.2004, page 48 of 89
HN29V1G91T-30
DC Characteristics
(VCC = 2.7 V to 3.6 V, Ta = 0 to +70°C)
Parameter
Symbol Min
Typ Max
3.3 3.6
10 20
15 30
10 20
20 30
10 20
15 30
Unit Test conditions
Operating VCC voltage
Operating VCC current
(Read)
VCC
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
ISB1
2.7
V
mA tRC = 50 ns, CE = ViL, Iout = 0 mA
mA tRC = 35 ns, CE = ViL, Iout = 0 mA
mA Single Bank Operation
mA Multi Bank Operation
mA Single Bank Operation
mA Multi Bank Operation
Operating VCC current
(Program)
Operating VCC current
(Erase)
Standby current (TTL)
1
mA CE = ViH
WP = VSS 0.2 V / VCC 0.2 V
PRE = VSS 0.2 V / VCC 0.2 V
RES = VCC 0.2 V
Standby current (CMOS)
ISB2
10 50
µA CE = VCC − 0.2 V,
WP = VSS 0.2 V / VCC 0.2 V
PRE = VSS 0.2 V / VCC 0.2 V
RES = VCC 0.2 V
Deep Standby current (CMOS) ISB3
5
µA RES = VSS 0.2 V,
WP = VSS 0.2 V / VCC 0.2 V
PRE = VSS 0.2 V/ VCC 0.2 V
Input Leakage Current
Output Leakage Current
Input voltage
ILi
10
10
µA Vin = 0 to 3.6 V
µA Vin = 0 to 3.6 V
ILo
ViH
ViL
ViHD
2.0
−0.3
VCC + 0.3 V
0.8
VCC + 0.2 V
V
Input voltage
(RES, WP, PRE)
VCC
0.2
−
ViLD
VoH
VOL
−0.2
2.4
8
+0.2
V
V
V
Output High voltage Level
Output Low voltage Level
Output Low Current (R/B)
IOH = −400 µA
0.4
IOL = 2.1 mA
IOL(R/B) 5
mA VOL = 0.4 V
Rev.4.00, Jun.20.2004, page 49 of 89
HN29V1G91T-30
AC Characteristics
(VCC = 2.7 V to 3.6 V, Ta = 0 to +70°C)
Test Conditions
•
•
•
•
Input pulse levels: 0.4 to 2.4 V
Input rise and fall time: 3 ns
Input and output timing levels: 1.5 V / 1.5 V
Output load: 1TTL GATE and 50 pF (3.0 V 10%)
1TTL GATE and 100 pF (3.3 V 10%)
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
CLE Setup Time
tCLS
tCLH
tCS
0
CLE Hold Time
9
CE Setup Time
CE Hold Time
WE Pulse Width
ALE Setup Time
0
tCH
6
tWP
15
0
1
tALS
tALH
tDS
ALE Hold Time
6
Data Setup Time
9
Data Hold Time
tDH
9
Write cycle Time
tWC
33
12
5
WE High Hole Time
CE High to WE low setup time
WE High to CE low hold time
CE High to RE low setup time
RE High to CE low hold time
tWH
tCHWS
tWHCH
tCHRS
tRHCH
5
5
5
Note: 1. If tCS is set less than 5 ns, tWP must be minimum 20 ns. Otherwise, tWP is minimum 15 ns.
Rev.4.00, Jun.20.2004, page 50 of 89
HN29V1G91T-30
AC Timing Characteristics for Operation
Parameter
Symbol Min
Typ
Max
120
Unit Note
Data Transfer from Cell to Register
ALE to RE Delay (ID Read)
ALE to RE Delay (Read cycle)
CLE to RE Delay (Read cycle)
Ready to RE Low
tR
20
30
6
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAR1
tAR2
tCLR
tRR
20
20
35
10
0
RE Pulse Width
WE High to Busy
tRP
tWB
100
Read cycle time
tRC
RE Access Time
CE Access Time
tREA
tCEA
tRHZ
tCHZ
tREH
tIR
20
25
RE High to Output Hi-Z
CE High to Output Hi-Z
RE High Hold Time
Output Hi-Z to RE Low
WE High to RE Low
20
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
1
1
20
10
0
tWHR
tRSTR
tRSTP
tRSTE
tRSTEV
tRSTDR
tPON
tVRS
tVRDY
tBSY
tWWS
tWWH
tCSD
50
100
15
15
100
Device Resetting Time
Read
20
Program
70
Erase
400
30
Erase Verify
Device recovery
350
200
Power on busy Time
VCC Setup time to Reset
VCC to Ready
100
100
Reset to Busy
WP setup time to WE High
WP hold time to WE High
CE setup time to Deep standby
Note: 1. The time until it becomes Hi-Z depends on the earliest signal which CE and RE go to high.
Rev.4.00, Jun.20.2004, page 51 of 89
HN29V1G91T-30
Timing Waveform
Command Latch Cycle
Address Latch Cycle
Rev.4.00, Jun.20.2004, page 52 of 89
HN29V1G91T-30
Input Data Latch Cycle
Serial Access Cycle after Read (CLE = L, WE = H, ALE = L)
Note: 1. The time until it becomes Hi-Z depends on the earliest signal which CE and RE go to high.
Rev.4.00, Jun.20.2004, page 53 of 89
HN29V1G91T-30
Invalid input cycle
CE
tWHCH
tCHWS
ALE
CLE
WE
I/O1 to
I/O8
DIN
(Invalid)
VIH or VIL
Invalid output cycle
CE
tRHCH
tCHRS
ALE
CLE
RE
I/O1 to
I/O8
VIH or VIL
Rev.4.00, Jun.20.2004, page 54 of 89
HN29V1G91T-30
Status Read Cycle
Note: 1. 70h: Single Bank operation Status
72h: Single Bank operation Error Status
71h: Multi Bank operation Status
73h: Multi Bank operation / Bank0 Error Status
74h: Multi Bank operation / Bank1 Error Status
75h: Multi Bank operation / Bank2 Error Status
76h: Multi Bank operation / Bank3 Error Status
Rev.4.00, Jun.20.2004, page 55 of 89
HN29V1G91T-30
Read Operation
Rev.4.00, Jun.20.2004, page 56 of 89
HN29V1G91T-30
Read Operation (Intercepted by CE)
tCLR
CLE
CE
tWC
WE
tWB
tCHZ
tAR2
ALE
tR
tRC
RE
tRR
I/Ox
00h
CA1
CA2
RA1
RA2
30h
DOUTN
DOUTN+1
DOUTN+2
Column address Row address
N
R/B
Busy
Rev.4.00, Jun.20.2004, page 57 of 89
HN29V1G91T-30
Random Data Output in a Page
Note: 1. The head column address can be specified over and over.
Rev.4.00, Jun.20.2004, page 58 of 89
HN29V1G91T-30
Multi Bank Read
Notes: 1. A maximum 4 bank from Bank0 to Bank3 can be repeated.
2. Read out specified bank.
3. It is repeated over and over within the same page setup.
Rev.4.00, Jun.20.2004, page 59 of 89
HN29V1G91T-30
Page program Operation
Rev.4.00, Jun.20.2004, page 60 of 89
HN29V1G91T-30
Page Program Operation with Random Data Input
Note: 1. It is repeated over and over within the same page setup.
Rev.4.00, Jun.20.2004, page 61 of 89
HN29V1G91T-30
Multi Bank Program (1/2)
Note: 1. A maximum 4 bank from Bank0 to Bank3 can be repeated.
Rev.4.00, Jun.20.2004, page 62 of 89
HN29V1G91T-30
Multi Bank Program (2/2)
Rev.4.00, Jun.20.2004, page 63 of 89
HN29V1G91T-30
Multi Bank Program Operation with Random Data Input (1/2)
Note: 1. Maximum three times repeatable.
Rev.4.00, Jun.20.2004, page 64 of 89
HN29V1G91T-30
Multi Bank Program Operation with Random Data Input (2/2)
Note: 1. Maximum three times repeatable.
Rev.4.00, Jun.20.2004, page 65 of 89
HN29V1G91T-30
Cache Program
Notes: 1. There is no limitation in the number of Page address which can specify consecutively.
2. Don’t specify a Page address inside the same bank consecutively.
Rev.4.00, Jun.20.2004, page 66 of 89
HN29V1G91T-30
2 Page Cache Program (1/2)
Note: 1. Don’t specify a Page address inside the same bank consecutively.
Rev.4.00, Jun.20.2004, page 67 of 89
HN29V1G91T-30
2 Page Cache Program (2/2)
Rev.4.00, Jun.20.2004, page 68 of 89
HN29V1G91T-30
Copy Back Program Operation
Rev.4.00, Jun.20.2004, page 69 of 89
HN29V1G91T-30
Copy Back Program with Data Output (1/2)
Rev.4.00, Jun.20.2004, page 70 of 89
HN29V1G91T-30
Copy Back Program with Data Output (2/2)
Note: 1. Updating copy data
Rev.4.00, Jun.20.2004, page 71 of 89
HN29V1G91T-30
Multi Bank Copy Back Program (1/3)
Notes: 1. Specifying the address of a source of copy.
2. Specifying the address of a source of copy.
3. A maximum 4 bank can be specified.
4. Read out the data of a source of copy.
Rev.4.00, Jun.20.2004, page 72 of 89
HN29V1G91T-30
Multi Bank Copy Back Program (2/3)
Note: 1. Updating a source data which did Copy Back Read.
Specifying Page address for post-copy.
Rev.4.00, Jun.20.2004, page 73 of 89
HN29V1G91T-30
Multi Bank Copy Back Program (3/3)
Note: 1. Updating a source data which did Copy Back Read.
Specifying Page address for post-copy.
Rev.4.00, Jun.20.2004, page 74 of 89
HN29V1G91T-30
Program Data Input in Erase busy
Rev.4.00, Jun.20.2004, page 75 of 89
HN29V1G91T-30
Block Erase Operation
Rev.4.00, Jun.20.2004, page 76 of 89
HN29V1G91T-30
Multi Bank Block Erase
Note: 1. Possible to specify maximum 4 Bank from Bank 0 to Bank3.
Rev.4.00, Jun.20.2004, page 77 of 89
HN29V1G91T-30
Page mode Erase Verify
Block mode Erase Verify
Rev.4.00, Jun.20.2004, page 78 of 89
HN29V1G91T-30
Multi Bank Page mode Erase verify
Note: 1. Possible to specify maximum 4 Bank from Bank 0 to Bank3.
Rev.4.00, Jun.20.2004, page 79 of 89
HN29V1G91T-30
Multi Bank Block mode Erase verify
Note: 1. Possible to specify maximum 4 Bank from Bank 0 to Bank3.
Rev.4.00, Jun.20.2004, page 80 of 89
HN29V1G91T-30
Read ID Operation
Rev.4.00, Jun.20.2004, page 81 of 89
HN29V1G91T-30
Power on Auto Read
VCC = 2.7 V
VCC
tCEA
CE
CLE
ALE
tVRS
WE
WP
tVRS
PRE
RES
tVRDY
tBSY tPON+tR
R/B
tRR
tREA
RE
I/O
Rev.4.00, Jun.20.2004, page 82 of 89
HN29V1G91T-30
Power on and off sequence
2.7 V
2.7 V
VCC
don t
care
don t
care
CE, WE, RE
tVRS
WP
CLE, ALE
PRE
tVRS
tBSY
RES
tVRDY
operation
don t
care
tPON
invalid
R/B
Rev.4.00, Jun.20.2004, page 83 of 89
HN29V1G91T-30
Deep Standby Mode
Standby state
Deep standby state
Power on state
Standby state
CE
tCSD
100 ns min
RES
R/B
tBSY
tPON
Operation state
Deep standby state
Power on state
Standby state
CE
tVRS
tRST min
RES
tBSY
tPON
tRST
R/B
Rev.4.00, Jun.20.2004, page 84 of 89
HN29V1G91T-30
Notes on usage
1. Prohibition of undefined command input
The commands listed in the command definition can only be used in this device. It is prohibited to issue a
command that is not defined in the list. If an undefined command is issued, the data held in the device may
be lost.
Only the commands defined can be issued, in only defined timings. Otherwise, illegal operations may
occur.
2. Limitation of command input in the busy state
In the busy state, following two commands are acceptable. Do not issue any other command except below
two commands.
•
•
Status read 70h, 71h, 72h, 73h, 74h, 75h, 76h
Read command FFh
3. Commands limitation after commands (80h, 85h) are input at the first cycle of a program
After commands (80h, 85h) are input at the first cycle of a program, only the second cycle of the program
commands (10h, 11h, 15h) and reset command (FFh) can be used. After a command 80h or 85h is input,
the commands are prohibit.
4. R/B (Ready/busy) pin handing
R/B is an open-drain output pin, and it should be pulled up to VCC with a resistance (more than 2kΩ).
5. Notes on RE signal
If the RE clock is sent before the address is input, the internal read operation may start unintentionally.
Be sure to send the RE clock after the address is input.
If the RE clock is input after the data of the last address is read during the read operation, invalid data is
output.
6. Notes on Address taking
This product takes the address data by four cycles, and when five cycles or more are input, the address data
since the fifth cycle becomes invalid.
7. Deep standby mode
During command waiting or standby state, when RES pin goes to low, the device transfers to deep standby
state.
When RES goes to high, the device returns form the deep standby state.
During command execution, going RES low stops command operation. If RES goes to low during
Rev.4.00, Jun.20.2004, page 85 of 89
HN29V1G91T-30
erase/program/read operation, the command operation is forced to terminate and the applied page data is
not guaranteed.
8. Notes on the power supply down
Please do not turn off a power supply in erase busy operation.
It is required to take the following measures on system side for expected power down.
When the power down is recognized to have occurred during erase busy operation, device recovery mode
after the power on. The data in other blocks are protected, though the data in the applied block is invalid,
by doing this.
Busy
tDRC
Busy
tDRC
R/B
I/O
00h CA1 CA2 RA1 RA2 38h
00h CA1 CA2 RA3 RA4 38h
Address input
Notes: 1. Please input any address for CA1 and CA2. Input an arbitrary address to CA1 and CA2.
2. The address input is necessary for RA1 and RA2 and RA4. Input 00h respectively.
For RA3, input 04h.
3. Busy time (tDRC) is as follows. When the data protect operation is unnecessary, end at the typ
time in normal operation. When the data protect operation is executed, the time of 100ms or
less is needed.
4. This protect operation is pause to input FF command or RES = L. In case of this pause, the
protect operation is not guaranteed.
typ
max
tDRC
890µs
100ms
R/B
00h CA1 CA2 RA1 RA2 38h
FFh
I/O
t
RSTDR
=350µs max
R/B
00h CA1 CA2 RA1 RA2 38h
I/O
t
RSTDR
=350µs max
RES
350µs min
Rev.4.00, Jun.20.2004, page 86 of 89
HN29V1G91T-30
9. Unusable Block
Initially, the HN29V1G91T includes unusable blocks. The usable blocks must be distinguished from the
usable blocks bye the system as follows.
1. Confirm the blocks which cannot be used after mounting on the system. The following data is written
on each page of the blocks which can be used. One block is composed of two pages, and following
data is written in both pages commonly (Refer to “The Unusable Blocks Indication Flow”).
Initial Data of Usable Pages
Column address 0h to 81Fh 820h
Data FFh 1Ch
821h
822h
823h
824h
825h
826h to 83Fh
71h
C7h
1Ch
71h
C7h
FFh
2. Do not Program and Erase to the partial invalid blocks by the system.
Start
k = 0
m = 0
n = 0
Page number = (8k + m + n)
NO
NO
1
Check data *
YES
n = n + 4
2
Bad block*
1
Check data *
YES
m = m + 1
NO
m = 4
YES
k = k + 1
NO
k = 8192
YES
END
Notes: 1. Refer to table "Initial data of usable pages".
2. Bad pages are installed in system.
The Unusable Blocks Indication Flow
Rev.4.00, Jun.20.2004, page 87 of 89
HN29V1G91T-30
10.Measures for don’t care in timing waveforms for Program Data Input in Erase Busy
The timing waveforms in any mode is specified “Don’t care”, during CE = H other control signals become
“Don’t care”. When CE = H, specify ALE and CLE = H, WE and RE = H.
11.Status read during read mode (data output)
Input the status mode reset command (7Fh), when the device returns to the read mode, after the status read
is executed the status read command (70h), during the busy status in the read mode.
12.Status read during read mode (data output)
The memory data cannot be output only by the RE clock, after the transition from the status read mode to
the read mode by the 7Fh, when the device is set to the status read mode during the data output, in the read
mode.
In this case, 06h command, column address, page address and E0h command must be input to the read
operation.
13.Status read in Multibank program mode
When execute status read during a dummy busy period after input command 11h in multibank program,
judge only Ready/Busy.
Rev.4.00, Jun.20.2004, page 88 of 89
HN29V1G91T-30
Package Dimensions
HN29V1G91T-30 (TFP-48DA)
As of January, 2003
12.00
12.40 Max
Unit: mm
25
48
1
24
0.50
*0.22 0.08
0.80
M
0.08
0.20 0.0ꢀ
20.00 0.20
0.45 Max
0˚ – 8˚
0.50 0.10
0.10
Package Code
JEDEC
JEITA
TFP-48DA
Conforms
Conforms
0.52 g
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
Rev.4.00, Jun.20.2004, page 89 of 89
Revision History
HN29V1G91T-30 Data Sheet
Rev. Date
Contents of Modification
Page Description
0.01 Jun. 19, 2003
0.02 Oct. 06, 2003
Initial issue
2
7
9
Add the explanation to the block replacement
Add the note for Power on auto Read Enable using
Add the Device Recovery
28
31
Add the two figures
Add the correspondence when the erase error occurred in Program Data
input in Erase Busy mode
48
49
50
51
88
Change degree of Storage Temperature range
Change IOL (R/B) Min 8 to 5
Add to the AC character, tCHWS, tWHCH, tCHRS, tRHCH
Add to the AC character, tWWS, tWWH, tCSD
Add the four items to the Notes on usage, No10 to 13
0.03 Nov. 28, 2003
2
Change of the description of transfer rate
2
Change of Operating voltage
3
Change of the figure of Pin Arrangement
6
Change of the description of Chip Enable
10
13
17
18
Change of the description of Page Read
Change of the figure of Multi Bank Read
Change of the figure of Multi Bank Page Program
Change of the figure of Multi Bank Page Program Random Data Input in
a Page
21
22
Change of the figure of Copy Back Program
Change of the figure of Copy Back Program with Random Data Input in
a Page
26
28
Change of the figure of Data Recovery Read
Change of the figure of To program, erase next, then update the data,
and then re-programming.
31
Change of the figure of Program Data input in Erase Busy (recommend
pattern when error occurred) Multi Bank Mode
Change of 70h command status in single bank operation
Change of 71h command status in 2page cache program operation
Change of 73h, 74h, 75h, 76h command status in Cache program/2page
cache program operation
35
39
40
41
Change of the figure of Reset operation in the Cache program (R/B =
Ready, True R/B = Busy)
41
42
43
43
49
49
50
51
57
63
84
85
Change of the figure of Reset operation in the Erase Verify
Change of the figure of Reset operation in the Program
Change of the figure of Reset operation in the Erase
Change of the figure of Reset operation in the Read
ISB1, ISB2, ISB3: Change of Test conditions
IOL(R/B) Typ: 10 mA to 8 mA
tWP: Addition of Note1
t
VRS, tBSY: Change of Unit
Change of the figure of Read Operation (Intercepted by CE)
Change of the figure of Multi Bank Program (2/2)
Change of the figure of Deep Standby Mode
Notes on usage: Change of 1., 2.
Rev. Date
Contents of Modification
Page Description
1.00 Dec. 08, 2003
2
48
86
Deletion of Preliminary
Change of the description of Wear leveling
Tstg: 0°C/+70°C to −25°C/+125°C
Notes on usage: Change of 8.
2.00 Dec. 19, 2003
3.00 Jun. 03, 2004
VCC: 2.7 V/3.6 V to 3.0 V/3.6 V
Tstg: −25°C/+125°C to −25°C/+85°C
48
VCC: 3.0 V/3.6 V to 2.7 V/3.6 V
1, 51 tR Max (1st access time): 100µs to120µs
8
Program/Erase Characteristics
tPROG Max: 1ms to 2.4ms
t
CPROG Max: 2ms to 4.8 ms
tCBSY Max: 1000µs to 2400µs
tBERS Max: 2.4ms to 20ms
86
Notes on usage: Change of 8. Notes: 2., 4.
Change of description
“The address input is necessary for RA1 and RA2. Input 00h
respectively.” to “The address input is necessary for RA1 and RA2 and
RA4. Input 00h respectively.”
“For RA3 and RA4, input 04h respectively.” to “For RA3, input 04h.”
“Before confirmation of this command, the protect operation is not
guaranteed.” to “In case of this pause, the protect operation is not
guaranteed.”
4.00 Jul. 20, 2004
51
AC Characteristics
tVRS Min: 20µs to 100µs
tVRDY Max: 20µs to 100µs
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
http://www.renesas.com
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501
Renesas Technology Europe Limited.
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom
Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900
Renesas Technology Europe GmbH
Dornacher Str. 3, D-85622 Feldkirchen, Germany
Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11
Renesas Technology Hong Kong Ltd.
7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2375-6836
Renesas Technology Taiwan Co., Ltd.
FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .1.0
相关型号：
HN29V256A0BBP-30
16MX16 FLASH 2.7V PROM, 35ns, PBGA95, 10 X 11.50 MM, 0.80 MM PITCH, LEAD FREE, CSP-95
RENESAS
HN29V256A1BBP-30
32MX8 FLASH 2.7V PROM, 35ns, PBGA95, 10 X 11.50 MM, 0.80 MM PITCH, LEAD FREE, CSP-95
RENESAS
HN29V2G74WT-30
128MX8 FLASH 3V PROM, 25ns, PDSO48, 12 X 17 MM, 0.5 MM PITCH, LEAD FREE, PLASTIC, WSOP-48
RENESAS
©2020 ICPDF网 联系我们和版权申明