HN58V256AT-12 [RENESAS]
256k EEPROM (32-kword × 8-bit) Ready/Busy and RES function (HN58V257A); 256K EEPROM （ 32千字× 8位）就绪/忙和RES功能（ HN58V257A ）
| 型号： | HN58V256AT-12 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 256k EEPROM (32-kword × 8-bit) Ready/Busy and RES function (HN58V257A) |
| 文件： | 总25页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HN58V256A Series
HN58V257A Series
256k EEPROM (32-kword × 8-bit)
Ready/Busy and RES function (HN58V257A)
REJ03C0147-0500Z
(Previous ADE-203-357D (Z) Rev.4.0)
Rev. 5.00
Nov. 17. 2003
Description
Renesas Technology's HN58V256A and HN58V257A are electrically erasable and programmable ROMs
organized as 32768-word × 8-bit. They have realized high speed, low power consumption and high reliability
by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also
have a 64-byte page programming function to make their write operations faster.
Features
•
•
•
Single 3 V supply: 2.7 to 5.5 V
Access time: 120 ns max
Power dissipation:
Active: 20 mW/MHz, (typ)
Standby: 110 µW (max)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
On-chip latches: address, data, CE, OE, WE
Automatic byte write: 10 ms max
Automatic page write (64 bytes): 10 ms max
Ready/Busy (only the HN58V257A series)
Data polling and Toggle bit
Data protection circuit on power on/off
Conforms to JEDEC byte-wide standard
Reliable CMOS with MNOS cell technology
105 erase/write cycles (in page mode)
10 years data retention
Software data protection
Write protection by RES pin (only the HN58V257A series)
Industrial versions (Temperature range: −20 to 85°C and −40 to 85°C) are also available.
There are free also lead free products.
Rev.5.00, Nov. 17.2003, page 1 of 22
HN58V256A Series, HN58V257A Series
Ordering Information
Type No.
Access time
120 ns
Package
HN58V256AFP-12
HN58V256AT-12
HN58V257AT-12
HN58V256AFP-12E
400 mil 28-pin plastic SOP (FP-28D)
28-pin plastic TSOP (TFP-28DB)
32-pin plastic TSOP (TFP-32DA)
120 ns
120 ns
120 ns
400 mil 28-pin plastic SOP (FP-28DV)
Lead Free
HN58V256AT-12E
HN58V257AT-12E
120 ns
120 ns
28-pin plastic TSOP (TFP-28DBV)
Lead Free
32-pin plastic TSOP (TFP-32DAV)
Lead Free
Pin Arrangement
HN58V256AFP Series
HN58V256AT Series
A2
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
A3
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A1
A0
13
12
11
10
9
A4
A5
2
I/O0
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
I/O7
A6
3
A13
A8
A7
A12
A14
VCC
A6
4
8
A5
5
A9
7
6
A4
6
A11
5
A13
A8
A3
7
4
3
A2
8
A10
A9
2
A11
A1
9
1
A10
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
(Top view)
I/O0
I/O1
I/O2
VSS
HN58V257AT Series
A2
A1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
A3
A4
A0
A5
NC
A6
(Top view)
I/O0
I/O1
I/O2
VSS
A7
A12
A14
RDY/
VCC
I/O3
I/O4
I/O5
I/O6
I/O7
NC
8
7
6
5
A13
A8
4
3
A9
2
A11
1
A10
(Top view)
Rev.5.00, Nov. 17.2003, page 2 of 22
HN58V256A Series, HN58V257A Series
Pin Description
Pin name
A0 to A14
I/O0 to I/O7
OE
CE
WE
Function
Address input
Data input/output
Output enable
Chip enable
Write enable
Power supply
Ground
VCC
VSS
RDY/Busy*1
RES*1
NC
Ready busy
Reset
No connection
Note: 1. This function is supported by only the HN58V257A series.
Block Diagram
Note: 1. This function is supported by only the HN58V257A series.
1
to
I/O0
I/O7
RDY/
*
VCC
High voltage generator
VSS
1
*
I/O buffer
and
input latch
Control logic and timing
1
*
A0
to
Y gating
Y decoder
A5
Address
buffer and
latch
X decoder
Memory array
Data latch
A6
to
A14
Rev.5.00, Nov. 17.2003, page 3 of 22
HN58V256A Series, HN58V257A Series
Operation Table
Operation
Read
CE
VIL
VIH
VIL
VIL
×
OE
VIL
×*2
VIH
VIH
×
WE
VIH
×
RES*3
VH*1
×
RDY/Busy*3
High-Z
I/O
Dout
High-Z
Din
Standby
Write
High-Z
VIL
VIH
VIH
×
VH
High-Z to VOL
High-Z
Deselect
Write inhibit
VH
High-Z
×
×
VIL
VIL
×
×
Data polling
Program reset
VIL
×
VIH
×
VH
VOL
Data out (I/O7)
High-Z
VIL
High-Z
Notes: 1. Refer to the recommended DC operating condition.
2. ×: Don’t care
3. This function is supported by only the HN58V267A series.
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
V
Supply voltage relative to VSS
Input voltage relative to VSS
Operating temperature range*2
Storage temperature range
−0.6 to +7.0
−0.5*1 to +7.0*3
0 to +70
Vin
V
Topr
Tstg
°C
°C
−55 to +125
Notes: 1. Vin min = −3.0 V for pulse width ≤ 50 ns
2. Including electrical characteristics and data retention
3. Should not exceed VCC + 1.0 V.
Recommended DC Operating Conditions
Parameter
Symbol
VCC
Min
Typ
3.0
0
Max
Unit
V
Supply voltage
2.7
5.5
VSS
0
0
V
Input voltage
VIL
−0.3*1
1.9*2
0.6
V
VIH
VH*4
VCC + 0.3*3
VCC + 1.0
+70
V
VCC −0.5
V
Operating temperature
Topr
0
°C
Notes: 1. VIL min: −1.0 V for pulse width ≤ 50 ns.
2. VIH min for VCC = 3.6 to 5.5 V is 2.4 V.
3. VIH max: VCC + 1.0 V for pulse width ≤ 50 ns.
4. This function is supported by only the HN58V257A series.
Rev.5.00, Nov. 17.2003, page 4 of 22
HN58V256A Series, HN58V257A Series
DC Characteristics (Ta = 0 to +70°C, VCC = 2.7 to 5.5 V)
Parameter
Symbol Min
Typ
Max
2*1
2
Unit Test conditions
Input leakage current
ILI
µA
µA
µA
mA
mA
VCC = 5.5 V, Vin = 5.5 V
Output leakage current ILO
VCC = 5.5 V, Vout = 5.5/0.4 V
CE = VCC
CE = VIH
Iout = 0 mA, Duty = 100%,
Cycle = 1 µs, VCC = 3.6 V
Standby VCC current
ICC1
ICC2
ICC3
20
1
Operating VCC current
8
12
12
30
0.4
mA
mA
mA
Iout = 0 mA, Duty = 100%,
Cycle = 1 ns, VCC = 5.5 V
Iout = 0 mA, Duty = 100%,
Cycle = 120 µs, VCC = 3.6 V
Iout = 0 mA, Duty = 100%,
Cycle = 120 ns, VCC = 5.5 V
Output low voltage
Output high voltage
VOL
VOH
V
V
IOL = 2.1 mA
VCC × 0.8
IOH = −400 µA
Note: 1. ILI on RES = 100 µA max (only the HN58V257A series)
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter
Symbol
Cin
Min
Typ
Max
6
Unit Test conditions
Input capacitance*1
Output capacitance*1
pF
pF
Vin = 0 V
Cout
12
Vout = 0 V
Note: 1. This parameter is periodically sampled and not 100% tested.
Rev.5.00, Nov. 17.2003, page 5 of 22
HN58V256A Series, HN58V257A Series
AC Characteristics (Ta = 0 to +70°C, VCC = 2.7 to 5.5 V)
Test Conditions
•
•
•
•
•
Input pulse levels:
0.4 V to 2.4 V (VCC ≤ 3.6V), 0.4V to 3.0 V (VCC > 3.6 V), 0 V to VCC (RES pin*2)
Input rise and fall time: ≤ 5 ns
Input timing reference levels: 0.8, 1.8 V
Output load: 1TTL Gate +100 pF
Output reference levels: 1.5 V, 1.5 V
Read Cycle
HN58V256A/HN58V257A
-12
Parameter
Symbol Min
tACC
tCE
Max
120
120
60
Unit
ns
Test conditions
Address to output delay
CE to output delay
OE to output delay
Address to output hold
CE = OE = VIL, WE = VIH
OE = VIL, WE = VIH
CE = VIL, WE = VIH
CE = OE = VIL, WE = VIH
CE = VIL, WE = VIH
CE = OE = VIL, WE = VIH
CE = OE = VIL, WE = VIH
ns
tOE
tOH
10
0
ns
ns
OE (CE) high to output float*1 tDF
0
40
ns
RES low to output float*1, 2
RES to output delay*2
tDFR
0
350
600
ns
tRR
0
ns
Rev.5.00, Nov. 17.2003, page 6 of 22
HN58V256A Series, HN58V257A Series
Write Cycle
Parameter
Symbol Min*3 Typ
Max
Unit Test conditions
Address setup time
tAS
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ms
ns
ns
µs
µs
Address hold time
tAH
50
0
CE to write setup time (WE controlled)
CE hold time (WE controlled)
WE to write setup time (CE controlled)
WE hold time (CE controlled)
OE to write setup time
OE hold time
tCS
tCH
tWS
tWH
tOES
tOEH
tDS
0
0
0
0
0
Data setup time
70
0
Data hold time
tDH
tWP
tCW
tDL
—
WE pulse width (WE controlled)
CE pulse width (CE controlled)
Data latch time
200
200
100
0.3
100
Byte load cycle
tBLC
tBL
tWC
tDB
tDW
tRP
30
Byte load window
Write cycle time
10*4
Time to device busy
120
0*5
100
1
Write start time
Reset protect time*2
Reset high time*2, 6
tRES
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are
no longer driven.
2. This function is supported by only the HN58V257A series.
3. Use this device in longer cycle than this value.
4. tWC must be longer than this value unless polling techniques or RDY/Busy (only the HN58V257A
series) are used. This device automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy (only the
HN58V257A series) are used.
6. This parameter is sampled and not 100% tested.
7. A6 through A14 are page addresses and these addresses are latched at the first falling edge of
WE.
8. A6 through A14 are page addresses and these addresses are latched at the first falling edge of
CE.
9. See AC read characteristics.
Rev.5.00, Nov. 17.2003, page 7 of 22
HN58V256A Series, HN58V257A Series
Timing Waveforms
Read Timing Waveform
Address
tACC
tOH
tCE
tDF
tOE
High
Data Out
Data out valid
tRR
tDFR
2
*
Rev.5.00, Nov. 17.2003, page 8 of 22
HN58V256A Series, HN58V257A Series
Byte Write Timing Waveform (1) (WE Controlled)
tWC
Address
tCS tAH
tCH
tAS
tBL
tWP
tOES
tOEH
tDS
tDH
Din
tDW
High-Z
tDB
High-Z
2
RDY/
*
tRP
tRES
2
*
VCC
Rev.5.00, Nov. 17.2003, page 9 of 22
HN58V256A Series, HN58V257A Series
Byte Write Timing Waveform (2) (CE Controlled)
Address
tWC
tWS
tAH
tBL
tCW
tAS
tWH
tOES
tOEH
tDH
tDS
Din
tDW
High-Z
tDB
High-Z
2
RDY/
*
tRP
tRES
2
*
VCC
Rev.5.00, Nov. 17.2003, page 10 of 22
HN58V256A Series, HN58V257A Series
Page Write Timing Waveform (1) (WE Controlled)
Address*7
A0 to A14
tAH
tAS
tBL
tWP
tDL
tBLC
tWC
tCS
tCH
tOEH
tOES
tDH
tDS
Din
tDW
tDB
2
High-Z
tRP
High-Z
RDY/
*
2
*
tRES
VCC
Rev.5.00, Nov. 17.2003, page 11 of 22
HN58V256A Series, HN58V257A Series
Page Write Timing Waveform (2) (CE Controlled)
Address*8
A0 to A14
tAH
tAS
tBL
tCW
tDL
tBLC
tWC
tWS
tWH
tOEH
tOES
tDH
tDS
Din
tDW
tDB
2
High-Z
High-Z
RDY/
*
tRP
2
*
tRES
VCC
Rev.5.00, Nov. 17.2003, page 12 of 22
HN58V256A Series, HN58V257A Series
Data Polling Timing Waveform
Address
An
An
An
*9
tCE
tOES
tOEH
*9
tOE
tDW
Din X
Dout X
Dout
I/O7
tWC
Rev.5.00, Nov. 17.2003, page 13 of 22
HN58V256A Series, HN58V257A Series
Toggle bit
This device provide another function to determine the internal programming cycle. If the EEPROM is set to
read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each read.
When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible
for next read or program.
Toggle bit Waveform
Notes: 1. I/O6 beginning state is “1”.
2. I/O6 ending state will vary.
3. See AC read characteristics.
4. Any address location can be used, but the address must be fixed.
Next mode
*4
Address
*3
t
CE
*3
t
OE
t
t
OES
OEH
*1
*2
*2
Din
Dout
Dout
Dout
Dout
I/O6
t
DW
t
WC
Rev.5.00, Nov. 17.2003, page 14 of 22
HN58V256A Series, HN58V257A Series
Software Data Protection Timing Waveform (1) (in protection mode)
VCC
tBLC
tWC
Address
Data
5555
AA
5555 Write address
A0 Write data
2AAA
55
Software Data Protection Timing Waveform (2) (in non-protection mode)
VCC
Normal active
mode
tWC
Address
Data
5555 2AAA 5555 5555 2AAA 5555
AA 55 80 AA 55 20
Rev.5.00, Nov. 17.2003, page 15 of 22
HN58V256A Series, HN58V257A Series
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle.
Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE. When
CE or WE is high for 100 µs after data input, the EEPROM enters write mode automatically and the input
data are written into the EEPROM.
Data Polling
Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read mode
during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the EEPROM is
performing a write operation.
RDY/Busy Signal (only the HN58V257A series)
RDY/Busy signal also allows the status of the EEPROM to be determined. The RDY/Busy signal has high
impedance except in write cycle and is lowered to VOL after the first write signal. At the end of a write cycle,
the RDY/Busy signal changes state to high impedance.
RES Signal (only the HN58V257A series)
When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping
RES low when VCC is switched. RES should be high during read and programming because it doesn't provide
a latch function.
VCC
Read inhibit
Read inhibit
Program inhibit
Program inhibit
Rev.5.00, Nov. 17.2003, page 16 of 22
HN58V256A Series, HN58V257A Series
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising
edge of WE or CE.
Write/Erase Endurance and Data Retention Time
The endurance is 105 cycles in case of the page programming and 104 cycles in case of the byte programming
(1% cumulative failure rate). The data retention time is more than 10 years when a device is page-
programmed less than 104 cycles.
Data Protection
To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20 ns
or less.
1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to
programming mode by mistake. Be careful not to allow noise of a width of more than 20 ns on the
control pins.
V
IH
0 V
V
IH
0 V
20 ns max
Rev.5.00, Nov. 17.2003, page 17 of 22
HN58V256A Series, HN58V257A Series
2. Data Protection at VCC On/Off
When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act
as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional
programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable
state.
Note: The EPROM should be kept in unprogrammable state during VCC on/off by using CPU RESET signal.
VCC
CPU
RESET
*
*
Unprogrammable
Unprogrammable
2.1 Protection by CE, OE, WE
To realize the unprogrammable state, the input level of control pins must be held as shown in the
table below.
CE
OE
WE
VCC
×
×
×
VSS
×
×
×
VCC
×: Don’t care.
VCC: Pull-up to VCC level.
VSS: Pull-down to VSS level.
2.2 Protection by RES (only the HN58V257A series)
The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the
EEPROM’s RES pin. RES should be kept VSS level during VCC on/off.
The EEPROM breaks off programming operation when RES becomes low, programming
operation doesn’t finish correctly in case that RES falls low during programming operation. RES
should be kept high for 10 ms after the last data input.
VCC
Program inhibit
Program inhibit
or
10 ms min
1 µs min
100 µs min
Rev.5.00, Nov. 17.2003, page 18 of 22
HN58V256A Series, HN58V257A Series
3. Software data protection
To prevent unintentional programming, this device has the software data protection (SDP) mode. The
SDP is enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3
bytes code is input. To program data in the SDP enable mode, 3 bytes code must be input before write
data.
Address
Data
5555
AA
↓
↓
2AAA
↓
55
↓
5555
↓
A0
↓
Write address Write data } Normal data input
The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP
disable cycle, data can not be written.
Address
Data
5555
↓
AA
↓
2AAA
↓
55
↓
5555
↓
5555
↓
2AAA
↓
5555
80
↓
AA
↓
55
↓
20
The software data protection is not enabled at the shipment.
Note: There are some differences between Renesas Technology’s and other company’s for enable/disable
sequence of software data protection. If there are any questions , please contact with Renesas
Technology’s sales offices.
Rev.5.00, Nov. 17.2003, page 19 of 22
HN58V256A Series, HN58V257A Series
Package Dimensions
HN58V256AFP Series (FP-28D, FP-28DV)
Unit: mm
18.3
18.8 Max
15
28
1
14
11.8 ± 0.3
1.7
1.12 Max
0˚ – 8˚
1.27
1.0 ± 0.2
0.15
*0.40 ± 0.08
0.20
M
0.38 ± 0.06
Package Code
FP-28D, FP-28DV
JEDEC
JEITA
Conforms
—
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
0.7 g
Rev.5.00, Nov. 17.2003, page 20 of 22
HN58V256A Series, HN58V257A Series
Package Dimensions (cont.)
HN58V256AT Series (TFP-28DB, TFP-28DBV)
Unit: mm
8.00
8.20 Max
15
28
1
14
0.55
*0.22 ± 0.08
0.20 ± 0.06
0.10
M
0.80
13.40 ± 0.30
0.45 Max
0˚ – 5˚
0.50 ± 0.10
0.10
Package Code
JEDEC
JEITA
TFP-28DB, TFP-28DBV
—
—
*Dimension including the plating thickness
Base material dimension
Mass (reference value) 0.23 g
Rev.5.00, Nov. 17.2003, page 21 of 22
HN58V256A Series, HN58V257A Series
Package Dimensions (cont.)
HN58V257AT Series (TFP-32DA, TFP-32DAV)
Unit: mm
8.00
8.20 Max
17
32
1
16
0.50
*0.22 ± 0.08
0.20 ± 0.06
0.08
M
0.80
14.00 ± 0.20
0.45 Max
0˚ – 5˚
0.50 ± 0.10
0.10
TFP-32DA, TFP-32DAV
Conforms
Conforms
Package Code
JEDEC
JEITA
*Dimension including the plating thickness
Base material dimension
0.26 g
Mass (reference value)
Rev.5.00, Nov. 17.2003, page 22 of 22
Revision History
HN58V256A/HN58V257A Series Data Sheet
Rev. Date
Contents of Modification
Page Description
0.0
0.1
Mar. 15. 1995
Aug. 7. 1995
Initial issue
Determination of package type:
HN58V256AT series (TFP-28DB)
Deletion of HN58V256AP series (DP-28)
Deletion of HN58V256AFPI-12/15
Deletion of HN58V256AT-12SR/15SR
Deletion of HN58V257AT-12SR/15SR
Absolute Maximum Rating
4
4
Deletion of Device Group
Deletion of Operating temperature range
− 20 to + 85°C and − 40 to +85°C
Recommended DC Operating Conditions
Deletion of Device Group
Deletion of Operating temperature range
−20/ /85°C and −40/ /85°C
Deletion of note 4
Change order of notes
1.0
Apr. 12. 1995
Change of format
2
Operating Information
Deletion of HN58V256A-15 and HN58V257A-15
Deletion of note 1
Deletion of Compatible type No.
Deletion of Operating temperature range
Pin Description
Addition of note 1
Block Diagram
3
3
Addition of note 1
Mode Selection
Addition of note 3
4
4
Absolute Maximum Ratings
Addition of note 4
Recommended DC operating Condition
VIH (min) 2.4 V to 1.9 V
Addition of note 4
5
6
DC Characteristics
ICC3 (max): 8/12/20/30 mA to 8/12/15/30 mA
AC Characteristics
Test condition: Input pulse levels: 0 V to 3.0 V to
0.4 V to 2.4 V(VCC ≤ 3.6 V), 0.4 V to 3.0 V(VCC > 3.6V)
Addition of note 2
Read Timing Waveform: Addition of note 1
Write Cycle: tDS (min): 50 ns to 70 ns
Addition of note 4, 5
Byte Write Timing Waveform (1) and (2): Addition of note 1
Page Write Timing Waveform (1) and (2): Addition of note 2
Revision Record (cont.)
Rev. Date
Contents of Modification
Page Description
1.0
Apr. 12. 1995
6
Timing Waveforms
Data Polling Timing Waveform: Addition of note 1
Toggle bit Waveform: Addition of note 4
Functional Description
16
16
Data Protection 2-(2) Addition of figure
2.0
3.0
4.0
Mar. 4. 1997
Functional Description
Data protection 3: Addition of note
May. 20. 1997 16
Functional Description
Data protection 3: Change of Description
Oct. 24. 1997
8
Timing Waveforms
Read Timing Waveform: Correct error
5.00 Nov. 17. 2003
Change format issued by Renesas Technology Corp.
Ordering Information
2
Addition of HN58V256AFP-12E, HN58V256AT-12E, HN58V257AT-12E
20-22 Package Dimensions
FP-28D to FP-28D, FP-28DV
TFP-28DB to TFP-28DB, TFP-28DBV
TFP-32DA to TFP-32DA, TFP-32DAV
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
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