HN58X24256FPIAGE [RENESAS]
IC,SERIAL EEPROM,32KX8,CMOS,SOP,8PIN,PLASTIC;
| 型号： | HN58X24256FPIAGE |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,SERIAL EEPROM,32KX8,CMOS,SOP,8PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总22页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Cautions
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Remember to give due consideration to safety when making your circuit designs, with appropriate
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contained therein.
HN58X24128FPIAG
HN58X24256FPIAG
Two-wire serial interface
128k EEPROM (16-kword × 8-bit)
256k EEPROM (32-kword × 8-bit)
ADE-203-1266A (Z)
Rev. 1.0
Apr. 20, 2001
Description
HN58X24xxxFPIAG series are two-wire serial interface EEPROM (Electrically Erasable and
Programmable ROM). They realize high speed, low power consumption and a high level of reliability by
employing advanced MNOS memory technology and CMOS process and low voltage circuitry technology.
They also have a 64-byte page programming function to make their write operation faster.
Features
•
•
•
•
Single supply: 1.8 V to 5.5 V
Two-wire serial interface (I2CTM serial bus*1)
Clock frequency: 400 kHz
Power dissipation:
Standby: 3 µA (max)
Active (Read): 1 mA (max)
Active (Write): 5 mA (max)
•
•
•
•
Automatic page write: 64-byte/page
Write cycle time: 10 ms (2.7 V to 5.5 V)/15 ms (1.8 V to 2.7 V)
Endurance: 105 Cycles (Page write mode)
Data retention: 10 Years
HN58X24128FPIAG/HN58X24256FPIAG
•
•
•
Small size packages: SOP-8pin
Shipping tape and reel: 2,500 IC/reel
Temperature range: –40 to +85°C
Note: 1. I2C is a trademark of Philips Corporation.
Ordering Information
Type No.
Internal organization Operating voltage Frequency Package
HN58X24128FPIAG 128k bit
1.8 V to 5.5 V
400 kHz
150 mil 8-pin plastic SOP
(FP-8DB)
(16384 × 8-bit)
HN58X24256FPIAG 256k bit
(32768 × 8-bit)
Pin Arrangement
8-pin SOP
1
A0
A1
8
VCC
WP
2
3
4
7
6
5
A2
SCL
SDA
VSS
(Top view)
Pin Description
Pin name
A0 to A2
SCL
Function
Device address
Serial clock input
Serial data input/output
Write protect
SDA
WP
VCC
Power supply
Ground
VSS
NC
No connection
2
HN58X24128FPIAG/HN58X24256FPIAG
Block Diagram
High voltage generator
Memory array
VCC
VSS
WP
A0, A1, A2
SCL
Control
logic
Y-select & Sense amp.
Serial-parallel converter
SDA
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
V
Supply voltage relative to VSS
Input voltage relative to VSS
Operating temperature range*1
Storage temperature range
–0.6 to +7.0
–0.5*2 to +7.0*3
–40 to +85
–65 to +125
Vin
V
Topr
Tstg
˚C
˚C
Notes: 1. Including electrical characteristics and data retention.
2. Vin (min): –3.0 V for pulse width ≤ 50 ns.
3. Should not exceed VCC + 1.0 V.
DC Operating Conditions
Parameter
Symbol
VCC
Min
Typ
—
0
Max
Unit
V
Supply voltage
1.8
5.5
VSS
0
0
V
Input high voltage
Input low voltage
VIH
VCC × 0.7
–0.3*1
–40
—
—
—
VCC + 1.0
VCC × 0.3
85
V
VIL
V
Operating temperature
Topr
˚C
Notes: 1. VIL (min): –1.0 V for pulse width ≤ 50 ns.
3
HN58X24128FPIAG/HN58X24256FPIAG
DC Characteristics (Ta = –40 to +85˚C, VCC = 1.8 V to 5.5 V)
Parameter
Symbol Min
Typ
—
Max
2.0
2.0
3.0
1.0
5.0
0.4
Unit
µA
µA
µA
mA
mA
V
Test conditions
Input leakage current
Output leakage current
Standby VCC current
Read VCC current
Write VCC current
Output low voltage
ILI
—
—
—
—
—
—
VCC = 5.5 V, Vin = 0 to 5.5 V
VCC = 5.5 V, Vout = 0 to 5.5 V
Vin = VSS or VCC
ILO
—
ISB
1.0
—
ICC1
ICC2
VOL2
VCC = 5.5 V, Read at 400 kHz
VCC = 5.5 V, Write at 400 kHz
VCC = 4.5 to 5.5 V, IOL = 1.6 mA
—
—
V
V
CC = 2.7 to 4.5 V, IOL = 0.8 mA
CC = 1.8 to 2.7 V, IOL = 0.4 mA
VOL1
—
—
0.2
V
VCC = 1.8 to 2.7 V, IOL = 0.2 mA
Capacitance (Ta = 25˚C, f = 1 MHz)
Test
Parameter
Input capacitance (A0 to A2, SCL, WP) Cin*1
Output capacitance (SDA)
CI/O*1
Symbol Min
Typ
Max
6.0
Unit
pF
conditions
—
—
—
—
Vin = 0 V
6.0
pF
Vout = 0 V
Note: 1. This parameter is sampled and not 100% tested.
4
HN58X24128FPIAG/HN58X24256FPIAG
AC Characteristics (Ta = –40 to +85˚C, VCC = 1.8 to 5.5 V)
Test Conditions
•
Input pules levels:
VIL = 0.2 × VCC
VIH = 0.8 × VCC
•
•
•
Input rise and fall time: ≤ 20 ns
Input and output timing reference levels: 0.5 × VCC
Output load: TTL Gate + 100 pF
Parameter
Symbol Min
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
400
—
Unit
kHz
ns
Notes
Clock frequency
Clock pulse width low
Clock pulse width high
Noise suppression time
Access time
fSCL
tLOW
tHIGH
tI
—
1200
600
—
—
ns
50
ns
1
tAA
100
1200
600
600
0
900
—
ns
Bus free time for next mode
Start hold time
tBUF
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
ns
—
ns
Start setup time
—
ns
Data in hold time
Data in setup time
Input rise time
—
ns
100
—
—
ns
300
300
—
ns
1
1
Input fall time
tF
—
ns
Stop setup time
tSU.STO
tDH
600
50
ns
Data out hold time
—
ns
Write cycle time
VCC = 2.7 V to 5.5 V
VCC = 1.8 V to 2.7 V
tWC
—
10
ms
ms
2
2
tWC
—
15
Notes: 1. This parameter is sampled and not 100% tested.
2. tWC is the time from a stop condition to the end of internally controlled write cycle.
5
HN58X24128FPIAG/HN58X24256FPIAG
Timing Waveforms
Bus Timing
1/fSCL
tR
tF
tLOW
tHIGH
SCL
tSU.STA
tHD.DAT
tSU.DAT
tHD.STA
tSU.STO
SDA
(in)
tBUF
tAA
tDH
SDA
(out)
Write Cycle Timing
Stop condition
Start condition
SCL
SDA
D0 in
tWC
(Internally controlled)
Write data
(Address (n))
ACK
6
HN58X24128FPIAG/HN58X24256FPIAG
Pin Function
Serial Clock (SCL)
The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge
clock data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is
400 kHz.
Serial Input/Output Data (SDA)
The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that
pin is open-drain driven structure. Use proper resistor value for your system by considering VOL, IOL and
the SDA pin capacitance. Except for a start condition and a stop condition which will be discussed later,
the SDA transition needs to be completed during SCL low period.
Data Validity (SDA data change timing waveform)
SCL
SDA
Data
Data
change
change
Note:
High-to-low and low-to-high change of SDA should be done during SCL low periods.
7
HN58X24128FPIAG/HN58X24256FPIAG
Device Address (A0, A1, A2)
Eight devices can be wired for one common data bus line as maximum. Device address pins are used to
distinguish each device and device address pins should be connected to VCC or VSS. When device address
code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one
device can be activated.
Pin Connections for A0 to A2
Pin connection
Max connect
Memory size number
A2
A1
A0
Note
128k bit
256k bit
8
8
VCC/VSS*1 VCC/VSS VCC/VSS
VCC/VSS VCC/VSS VCC/VSS
Note: 1. “VCC/VSS” means that device address pin should be connected to VCC or VSS.
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in
the following table. When the WP is low, write operation for all memory arrays are allowed. The read
operation is always activated irrespective of the WP pin status. WP should be fixed high or low during
operations since WP does not provide a latch function.
Write Protect Area
Write protect area
WP pin status 128k bit
256k bit
VIH
VIL
Upper 1/8 (16k bit)
Normal read/write operation
Upper 1/8 (32k bit)
8
HN58X24128FPIAG/HN58X24256FPIAG
Functional Description
Start Condition
A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation.
(See start condition and stop condition)
Stop Condition
A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts
after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the
write data inputs and place the device in a internally-timed write cycle to the memories. After the
internally-timed write cycle which is specified as tWC, the device enters a standby mode. (See write cycle
timing)
Start Condition and Stop Condition
SCL
SDA
(in)
Start condition
Stop condition
9
HN58X24128FPIAG/HN58X24256FPIAG
Acknowledge
All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero
to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter
keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation,
EEPROM sends a zero to acknowledge after receiving every 8-bit words. In the read operation, EEPROM
sends a zero to acknowledge after receiving the device address word. After sending read data, the
EEPROM waits acknowledgment by keeping bus open. If the EEPROM receives zero as an acknowledge,
it sends read data of next address. If the EEPROM receives acknowledgment "1" (no acknowledgment)
and a following stop condition, it stops the read operation and enters a stand-by mode. If the EEPROM
receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus open without sending
read data.
Acknowledge Timing Waveform
1
2
8
9
SCL
SDA IN
Acknowledge
out
SDA OUT
10
HN58X24128FPIAG/HN58X24256FPIAG
Device Addressing
The EEPROM device requires an 8-bit device address word following a start condition to enable the chip
for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address
code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to
distinguish device type and this EEPROM uses “1010” fixed code. The device address word is followed by
the 3-bit device address code in the order of A2, A1, A0. The device address code selects one device out of
all devices which are connected to the bus. This means that the device is selected if the inputted 3-bit
device address code is equal to the corresponding hard-wired A2-A0 pin status. The eighth bit of the
device address word is the read/write(R/W) bit. A write operation is initiated if this bit is low and a read
operation is initiated if this bit is high. Upon a compare of the device address word, the EEPROM enters
the read or write operation after outputting the zero as an acknowledge. The EEPROM turns to a stand-by
state if the device code is not “1010” or device address code doesn’t coincide with status of the correspond
hard-wired device address pins A0 to A2.
Device Address Word
Device address word (8-bit)
Device code (fixed)
Device address code
A2 A1
R/W code*1
128k, 256k
1
0
1
0
A0
R/W
Note: 1. R/W=“1” is read and R/W = “0” is write.
11
HN58X24128FPIAG/HN58X24256FPIAG
Write Operations
Byte Write:
A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends
acknowledgment "0" at the ninth clock cycle. After these, the 128kbit and 256kbit EEPROMs receive 2
sequence 8-bit memory address words. Upon receipt of this memory address, the EEPROM outputs
acknowledgment "0" and receives a following 8-bit write data. After receipt of write data, the EEPROM
outputs acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters an
internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle.
The EEPROM returns to a standby mode after completion of the write cycle.
Byte Write Operation
Device
address
1st Memory
address (n)
2nd Memory
address (n)
Write data (n)
W
1 0 1 0
128k to 256k
Start
ACK
R/W
ACK
ACK
Stop
Notes: 1. Don't care bits for 128k and 256k.
2. Don't care bit for 128k.
12
HN58X24128FPIAG/HN58X24256FPIAG
Page Write:
The EEPROM is capable of the page write operation which allows any number of bytes up to 64 bytes to
be written in a single write cycle. The page write is the same sequence as the byte write except for
inputting the more write data. The page write is initiated by a start condition, device address word,
memory address(n) and write data (Dn) with every ninth bit acknowledgment. The EEPROM enters the
page write operation if the EEPROM receives more write data (Dn+1) instead of receiving a stop condition.
The a0 to a5 address bits are automatically incremented upon receiving write data (Dn+1). The EEPROM
can continue to receive write data up to 64 bytes. If the a0 to a5 address bits reaches the last address of the
page, the a0 to a5 address bits will roll over to the first address of the same page and previous write data
will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and enters
internally-timed write cycle.
Page Write Operation
Device
address
1st Memory
address (n)
2nd Memory
address (n)
Write data (n)
ACK
Write data (n+m)
128k to
256k
W
1 0 1 0
ACK
R/W
ACK
ACK
ACK
Stop
Start
Notes: 1. Don't care bits for 128k and 256k.
2. Don't care bit for 128k.
13
HN58X24128FPIAG/HN58X24256FPIAG
Acknowledge Polling:
Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not.
This features is initiated by the stop condition after inputting write data. This requires the 8-bit device
address word following the start condition during a internally-timed write cycle. Acknowledge polling
will operate R/W code = “0”. Acknowledgment “1” (no acknowledgment) shows the EEPROM is in a
internally-timed write cycle and acknowledgment “0” shows that the internally-timed write cycle has
completed. See Write Cycle Polling using ACK.
Write Cycle Polling Using ACK
Send
write command
Send
stop condition
to initiate write cycle
Send
start condition
Send
device address word
with R/W = 0
No
No
ACK
returned
Yes
Next operation is
addressing the memory
Yes
Send
Send
Send
memory address
start condition
stop condition
Send
stop condition
Proceed random address
read operation
Proceed write operation
14
HN58X24128FPIAG/HN58X24256FPIAG
Read Operation
There are three read operations: current address read, random read, and sequential read. Read operations
are initiated the same way as write operations with the exception of R/W = “1”.
Current Address Read:
The internal address counter maintains the last address accessed during the last read or write operation,
with incremented by one. Current address read accesses the address kept by the internal address counter.
After receiving a start condition and the device address word (R/W is “1”), the EEPROM outputs the 8-bit
current address data from the most significant bit following acknowledgment “0” If the EEPROM receives
acknowledgment “1” (no acknowledgment) and a following stop condition, the EEPROM stops the read
operation and is turned to a standby state. In case the EEPROM have accessed the last address of the last
page at previous read operation, the current address will roll over and returns to zero address. In case the
EEPROM have accessed the last address of the page at previous write operation, the current address will
roll over within page addressing and returns to the first address in the same page. The current address is
valid while power is on. The current address after power on will be indefinite. The random read operation
described below is necessary to define the memory address.
Current Address Read Operation
Device
address
Read data (n+1)
ACK No ACK
128k to 256k
Start
1 0 1 0
R
Stop
R/W
15
HN58X24128FPIAG/HN58X24256FPIAG
Random Read:
This is a read operation with defined read address. A random read requires a dummy write to set read
address. The EEPROM receives a start condition, device address word (R/W=0) and memory address 2 ×
8-bit sequentially. The EEPROM outputs acknowledgment “0” after receiving memory address then enters
a current address read with receiving a start condition. The EEPROM outputs the read data of the address
which was defined in the dummy write operation. After receiving acknowledgment “1”(no
acknowledgment) and a following stop condition, the EEPROM stops the random read operation and
returns to a standby state.
Random Read Operation
Device
address
1st Memory
address (n)
2nd Memory
address (n)
Device
address
Read data (n)
No ACK
@@@
# # #
128k to
256k
W
R
1 0 1 0
1 0 1 0
R/W
ACK
ACK
R/W
ACK
Start
ACK
Start
Stop
Dummy write
Currect address read
Notes: 1. Don't care bits for 128k and 256k.
2. Don't care bit for 128k.
3. 2nd device address code (#) should be same as 1st (@).
16
HN58X24128FPIAG/HN58X24256FPIAG
Sequential Read:
Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives
acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are
coming out. This operation can be continued as long as the EEPROM receives acknowledgment “0”. The
address will roll over and returns address zero if it reaches the last address of the last page. The sequential
read can be continued after roll over. The sequential read is terminated if the EEPROM receives
acknowledgment “1” (no acknowledgment) and a following stop condition.
Sequential Read Operation
Device
address
Read data (n) Read data (n+1) Read data (n+2) Read data (n+m)
128k to
256k
R
1 0 1 0
ACK
ACK
R/W
ACK
ACK
No ACK
Stop
Start
17
HN58X24128FPIAG/HN58X24256FPIAG
Notes
Data Protection at VCC On/Off
When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc)
may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional
programming, this EEPROM have a power on reset function. Be careful of the notices described below in
order for the power on reset function to operate correctly.
•
SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition
during VCC on/off may cause the trigger for the unintentional programming.
•
•
VCC should be turned off after the EEPROM is placed in a standby state.
VCC should be turned on from the ground level(VSS) in order for the EEPROM not to enter the
unintentional programming mode.
•
VCC turn on speed should be longer than 10 us.
Write/Erase Endurance and Data Retention Time
The endurance is 105 cycles in case of page programming and 104 cycles in case of byte programming (1%
cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed
less than 104 cycles.
Noise Suppression Time
This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than
50 ns. Be careful not to allow noise of width more than 50 ns.
18
HN58X24128FPIAG/HN58X24256FPIAG
Package Dimensions
HN58X24128FPIAG/HN58X24256FPIAG (FP-8DB)
Unit: mm
4.89
5.15 Max
5
8
1
4
6.02 ± 0.18
0.69 Max
1.06
0° – 8°
+ 0.289
1.27
0.60
– 0.194
+0.063
*0.42
–0.064
0.40 ± 0.06
0.10
M
0.25
Hitachi Code
JEDEC
FP-8DB
—
EIAJ
—
0.08 g
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
19
HN58X24128FPIAG/HN58X24256FPIAG
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
Europe
Asia
: http://semiconductor.hitachi.com/
: http://www.hitachi-eu.com/hel/ecg
: http://sicapac.hitachi-asia.com
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive Whitebrook Park
Hitachi Europe Ltd.
Electronic Components Group
Hitachi Asia Ltd.
Hitachi Tower
16 Collyer Quay #20-00
Singapore 049318
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower
San Jose,CA 95134
Lower Cookham Road
World Finance Centre,
Tel: <1> (408) 433-1990 Maidenhead
Fax: <1>(408) 433-0223 Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Tel : <65>-538-6533/538-8577
Fax : <65>-538-6933/538-3877
URL : http://www.hitachi.com.sg
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel : <852>-(2)-735-9218
Fax : <852>-(2)-730-0281
URL : http://semiconductor.hitachi.com.hk
Fax: <44> (1628) 585200
Hitachi Asia Ltd.
(Taipei Branch Office)
4/F, No. 167, Tun Hwa North Road
Hung-Kuo Building
Hitachi Europe GmbH
Electronic Components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Taipei (105), Taiwan
Tel : <886>-(2)-2718-3666
Fax : <886>-(2)-2718-8180
Telex : 23222 HAS-TP
URL : http://www.hitachi.com.tw
Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.
Colophon 4.0
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