HS-4424BEH [RENESAS]
Radiation Hardened Dual, Non-Inverting Power MOSFET Drivers;
| 型号： | HS-4424BEH |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Radiation Hardened Dual, Non-Inverting Power MOSFET Drivers |
| 文件： | 总16页 (文件大小：528K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
Dual, Noninverting Power MOSFET Radiation Hardened
Drivers
HS-4424DRH
Features
The radiation hardened HS-4424 family are noninverting, dual,
monolithic high-speed MOSFET drivers designed to convert low
voltage control input signals into higher voltage, high current
outputs. The HS-4424DRH is fully tested across the 8V to 18V
operating range.
• Electrically screened to DLA SMD# 5962-99560
• QML qualified per MIL-PRF-38535 requirements
• Latch-up immune
• Radiation environment
- High dose rate (50-300rad(Si)/s). . . . . . . . . . . 300krad(Si)
The inputs of these devices can be directly driven by the
HS-1825ARH PWM device or by our ACS/ACTS and HCS/HCTS
type logic devices. The fast rise times and high current outputs
allow very quick control of high gate capacitance power
MOSFETs in high frequency applications.
• IPEAK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2A (min)
• Matched rise and fall times (CL = 4300pF). . . . . . . 75ns (max)
• Low voltage lockout feature . . . . . . . . . . . . . . . . . . . . . . . . <8V
• Wide supply voltage range . . . . . . . . . . . . . . . . . . . . 8V to 18V
The high current outputs minimize power losses in MOSFETs by
rapidly charging and discharging the gate capacitance. The
output stage incorporates a low voltage lockout circuit that
puts the outputs into a three-state mode when the supply
voltage is below its Undervoltage Lockout (UVLO) threshold
voltage.
• Propagation delay . . . . . . . . . . . . . . . . . . . . . . . . .250ns (max)
• Consistent delay times with VCC changes
• Low power consumption
- 40mW with inputs high
- 20mW with inputs low
Constructed with Intersil’s dielectrically isolated Rad Hard
Silicon Gate (RSG) BiCMOS process, these devices are immune
to single event latch-up and have been specifically designed to
provide highly reliable performance in harsh radiation
environments.
• Low equivalent input capacitance . . . . . . . . . . . . . 3.2pF (typ)
• ESD protected. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kV
Applications
• Switching power supplies
• DC/DC converters
TABLE 1. HS4424 PRODUCT FAMILY SPECIFIC UVLO Vth
PART NUMBER
UVLO (V)
<10
HS-4424RH
HS-4424EH
• Motor controllers
HS4424BRH
HS4424BEH
<7.5
<8
HS4424DRH
7.7
+8V TO +18V
VCC
UVLO_f
7.6
UVLO_r
7.5
OUT A
IN A
PWM
7.4
7.3
7.2
CONTROLLER
IN B
OUT B
HS-1825ARH
HS-4424DRH
GND
-55
25
125
TEMPERATURE (°C)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. UNDERVOLTAGE LOCKOUT vs TEMPERATURE
July 1, 2015
FN8747.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
HS-4424DRH
Pin Configuration
HS-4424DRH
(16 LD FLATPACK)
TOP VIEW
NC
IN A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
OUT A
OUT A
VCC
NC
GND A
GND B
NC
VCC
OUT B
OUT B
NC
IN B
NC
Pin Descriptions
PIN NUMBER
PIN NAME
EQUIVALENT ESD CIRCUIT
DESCRIPTION
1, 3, 6, 8, 9, 16
NC
NA
Circuit 2
NA
No Internal Connection
Driver A Input
2
4
IN A
GND A
GND B
IN B
Ground Reference A
Ground Reference B
Driver B Input
5
NA
7
Circuit 2
NA
10, 11
12, 13
14, 15
OUT B
VCC
Driver B Output
Circuit 1
NA
Positive power supply
Driver A Output
OUT A
VCC
VCC
2kΩ
IN
GND
GND
FIGURE 3. CIRCUIT 1
FIGURE 4. CIRCUIT 2
FN8747.1
July 1, 2015
Submit Document Feedback
2
HS-4424DRH
Functional Block Diagram
VCC
OUT A
CONTROL
LOGIC
LEVEL
IN A
SHIFTER
AND
UVLO
OUT A
1k
GND A
VCC
OUT B
CONTROL
LEVEL
SHIFTER
LOGIC
IN B
AND
UVLO
OUT B
1k
GND B
FIGURE 5. BLOCK DIAGRAM
Ordering Information
ORDERING
SMD NUMBER
(Note 2)
PART NUMBER
(Note 1)
TEMPERATURE RANGE
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
(°C)
5962F9956006V9A
HS0-4424DRH/SAMPLE
5962F9956005VXC
HS9-4424DRH/PROTO
NOTES:
HS0-4424DRH-Q
-55 to +125
-55 to +125
-55 to +125
-55 to +125
DIE
HS0-4424DRH/SAMPLE
HS9-4424DRH-Q
DIE SAMPLE
16 Ld Flatpack
16 Ld Flatpack
K16.A
K16.A
HS9-4424DRH/PROTO
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table must be used when ordering.
FN8747.1
July 1, 2015
Submit Document Feedback
3
HS-4424DRH
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to VCC
Output Short-circuit Duration (1 output at a time). . . . . . . . . . . . Indefinite
ESD Rating
Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 5kV
Machine Model (Tested per MIL-PRF-883 3015.7) . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V
Thermal Resistance (Typical)
16 Ld Flatpack Package (Notes 3, 4). . . . .
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+175°C
Maximum Lead Temperature (Soldering 10 secs) . . . . . . . . . . . . . .+265°C
JA (°C/W)
34
JC (°C/W)
5
Recommended Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 18V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
4. For JC, the “case temp” location is the center of the package underside.
Electrical Specifications
V
= 8V, 12V, 18V, T = +25°C, unless otherwise noted. Boldface limits apply across the operating tem-
CC A
perature range, -55°C to +125°C; over radiation total ionizing dose.
MIN
MAX
PARAMETER
VSUPPLY
DESCRIPTION
Supply Voltage Range
TEST CONDITIONS
(Note 5)
TYP
(Note 5)
UNIT
V
8
18
3.5
4
ICCSB LOW
18V Bias Current
18V Bias Current
8V Bias Current
VS = 18V, Inputs = 0V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
VS = 18V, Inputs = 0V
VS = 18V, Inputs = 0V, Post Radiation
VS, Inputs = 18V
4
ICCSB HIGH
ICCSB LOW
ICCSB HIGH
IIL_18
3.5
4
VS, Inputs = 18V
VS, Inputs = 18V, Post Radiation
VS = 8V, Inputs = 0V
4
3.5
4
VS = 8V, Inputs = 0V
VS = 8V, Inputs = 0V, Post Radiation
VS, Inputs = 8V
4
8V Bias Current
3.5
4
VS, Inputs = 8V
VS, Inputs = 8V, Post Radiation
VS = 18V, Inputs = 0V
VS = 18V, Inputs = 0V
VS = 18V, Inputs = 0V, Post Radiation
VS, Inputs = 18V
4
Input Current Low
Input Current High
Input Current Low
Input Current High
-5
0.08
0.08
0.08
0.08
5
-10
-10
-5
10
10
5
µA
µA
IIH_18
µA
VS, Inputs = 18V
-10
-10
-5
10
10
5
µA
VS, Inputs = 18V, Post Radiation
VS = 8V, Inputs = 0V
µA
IIL_8
µA
VS = 8V, Inputs = 0V
-10
-10
-5
10
10
5
µA
VS = 8V, Inputs = 0V, Post Radiation
VS, Inputs = 8V
µA
IIH_8
µA
VS, Inputs = 8V
-10
-10
10
10
µA
VS, Inputs = 8V, Post Radiation
µA
FN8747.1
July 1, 2015
Submit Document Feedback
4
HS-4424DRH
Electrical Specifications
V
= 8V, 12V, 18V, T = +25°C, unless otherwise noted. Boldface limits apply across the operating tem-
A
CC
perature range, -55°C to +125°C; over radiation total ionizing dose. (Continued)
MIN
MAX
PARAMETER
VOH
DESCRIPTION
Output Voltage High
TEST CONDITIONS
V = 8V, IOUT = 5mA
(Note 5)
TYP
(Note 5)
UNIT
V
VS - 0.75
VS - 0.45
S
VS - 0.9
V
VOL
VOH
VOL
Output Voltage Low
Output Voltage High
Output Voltage Low
Output Voltage High
Output Voltage Low
Output Voltage High
Output Voltage Low
Output Voltage High
Output Voltage Low
Output Voltage High
Output Voltage Low
Input Voltage High Threshold
Input Voltage Low Threshold
V = 8V, IOUT = 5mA
0.45
VS - 0.75
0.75
0.8
V
S
0.8
V
V = 8V, IOUT = 50mA
VS - 0.95
V
S
VS - 1.1
V
V = 8V, IOUT = 50mA
0.95
V
S
1.1
V
VOH
V = 12V, IOUT = 5mA
VS - 0.75
VS - 0.45
0.45
V
S
VS - 0.75
V
VOL
V = 12V, IOUT = 5mA
0.8
V
S
0.8
V
VOH
V = 12V, IOUT = 50mA
VS - 0.95
VS - 0.75
0.75
V
S
VS - 1.1
V
VOL
V = 12V, IOUT = 50mA
0.95
V
S
1.1
V
VOH
V = 18V, IOUT = 5mA
VS - 0.75
VS - 0.45
0.45
V
S
VS - 0.75
V
VOL
V = 18V, IOUT = 5mA
0.8
V
S
0.8
V
VOH
V = 18V, IOUT = 50mA
VS - 0.95
VS - 0.75
0.75
V
S
VS - 1.1
V
VOL
V = 18V, IOUT = 50mA
S
0.95
V
1.1
V
VIH_18
VS = 18V
VS = 18V
3
V
3.1
V
VIL_18
0.8
V
0.8
V
VIHYS_18
VIH_12
Input Voltage Threshold Hysteresis
Input Voltage High Threshold
VS = 18V
VS = 12V
100
3
mV
V
3.1
V
VIL_12
Input Voltage Low Threshold
VS = 12V
0.8
V
0.8
V
VHYS_12
VIH_8
Input Voltage Threshold Hysteresis
Input Voltage High Threshold
VS = 12V
VS = 8V
100
3
mV
V
3.1
V
VIL_8
Input Voltage Low Threshold
VS = 8V
VS = 8V
0.8
V
0.8
V
VHYS_8
Input Voltage Threshold Hysteresis
Rising Undervoltage Lockout
100
7.2
mV
V
UVLO_r
7.5
7.8
6.9
7.95
V
FN8747.1
July 1, 2015
Submit Document Feedback
5
HS-4424DRH
Electrical Specifications
V
= 8V, 12V, 18V, T = +25°C, unless otherwise noted. Boldface limits apply across the operating tem-
A
CC
perature range, -55°C to +125°C; over radiation total ionizing dose. (Continued)
MIN
MAX
PARAMETER
UVLO_f
DESCRIPTION
TEST CONDITIONS
(Note 5)
TYP
(Note 5)
UNIT
V
Falling Undervoltage Lockout
7.1
7.45
7.75
6.8
7.9
V
HYS_UVLO
Min_PW
Undervoltage Lockout Hysteresis
Minimum Input Pulse Width
UVLO_r - UVLO_f
23
24
mV
mV
ns
100
TRANSIENT RESPONSE
tr, tf, Rise Time 10% to 90% of VOUT
VS = 18V, CL = 4300pF
75
95
95
75
95
95
75
95
95
75
95
95
75
95
95
75
95
95
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VS = 18V, CL = 4300pF
VS = 18V, CL = 4300pF, Post Radiation
VS = 18V, CL = 4300pF
Fall Time 90% to 10% of VOUT
Rise Time 10% to 90% of VOUT
Fall Time 90% to 10% of VOUT
Rise Time 10% to 90% of VOUT
Fall Time 90% to 10% of VOUT
VS = 18V, CL = 4300pF
VS = 18V, CL = 4300pF, Post Radiation
VS = 12V, CL = 4300pF
VS = 12V, CL = 4300pF
VS = 12V, CL = 4300pF, Post Radiation
VS = 12V, CL = 4300pF
VS = 12V, CL = 4300pF
VS = 12V, CL = 4300pF, Post Radiation
VS = 8V, CL = 4300pF
VS = 8V, CL = 4300pF
VS = 8V, CL = 4300pF, Post Radiation
VS = 8V, CL = 4300pF
VS = 8V, CL = 4300pF
VS = 8V, CL = 4300pF, Post Radiation
FN8747.1
July 1, 2015
Submit Document Feedback
6
HS-4424DRH
Electrical Specifications
V
= 8V, 12V, 18V, T = +25°C, unless otherwise noted. Boldface limits apply across the operating tem-
A
CC
perature range, -55°C to +125°C; over radiation total ionizing dose. (Continued)
MIN
MAX
PARAMETER
tPHL, tPLH
DESCRIPTION
TEST CONDITIONS
(Note 5)
TYP
(Note 5)
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
,
50% of Rising Input to 10% of Rising Output VS = 18V, CL = 4300pF
VS = 18V, CL = 4300pF
200
300
300
200
300
300
250
350
350
250
350
350
300
400
400
300
400
400
VS = 18V, CL = 4300pF, Post Radiation
50% of Falling Input to 90% of Falling Output VS = 18V, CL = 4300pF
VS = 18V, CL = 4300pF
VS = 18V, CL = 4300pF, Post Radiation
50% of Rising Input to 10% of Rising Output VS = 12V, CL = 4300pF
VS = 12V, CL = 4300pF
VS = 12V, CL = 4300pF, Post Radiation
50% of Falling Input to 90% of Falling Output VS = 12V, CL = 4300pF
VS = 12V, CL = 4300pF
VS = 12V, CL = 4300pF, Post Radiation
50% of Rising Input to 10% of Rising Output VS = 8V, CL = 4300pF
VS = 8V, CL = 4300pF
VS = 8V, CL = 4300pF, Post Radiation
50% of Falling Input to 90% of Falling Output VS = 8V, CL = 4300pF
VS = 8V, CL = 4300pF
VS = 8V, CL = 4300pF, Post Radiation
NOTE:
5. Compliance to datasheet limits is assured by one or more methods; production test, characterization and/or design.
FN8747.1
July 1, 2015
Submit Document Feedback
7
HS-4424DRH
Typical Performance Curves Unless otherwise specified, V = 8V, 12V, 18V, C = 4300pF, T = +25°C.
S
L
A
200
150
100
50
3.0
2.5
2.0
1.5
1.0
0.5
0
ICCSBH_18
ICCSBH_8
ICCSBL_18
ICCSBL_8
18V_BIAS
8V_BIAS
0
1k
10k
100k
1M
-55
25
125
FREQUENCY (Hz)
TEMPERATURE (°C)
FIGURE 6. SUPPLY CURRENT vs DUAL SWITCHING AT FREQUENCY
FIGURE 5. SUPPLY CURRENT vs TEMPERATURE
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.95
VOH_18_50
0.90
VOH_8_5
VOH_18_5
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
VOH_8_50
VOL_8_5
VOL_8_50
VOL_18_50
VOL_18_5
-55
25
125
-55
25
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 7. OUTPUT VOLTAGE vs TEMPERATURE (5mA)
FIGURE 8. OUTPUT VOLTAGE vs TEMPERATURE (50mA)
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
2.8
V
+125
OH
18V V
IH
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
V
+85
OH
12V V
IH
V
+25
8V V
OH
IH
V
-55
OH
12V V
IL
V
+125
OL
8V V
IL
V
+25
90
18V V
OL
IL
V
+85
OL
V
-55
OL
0
3
6
9
30
60
199
349
498
-55
25
TEMPERATURE (°C)
125
OUTPUT CURRENT (mA)
FIGURE 9. OUTPUT VOLTAGE vs OUTPUT CURRENT
FIGURE 10. INPUT VOLTAGE THRESHOLD vs TEMPERATURE AND
BIAS VOLTAGE
FN8747.1
July 1, 2015
Submit Document Feedback
8
HS-4424DRH
Typical Performance Curves Unless otherwise specified, V = 8V, 12V, 18V, C = 4300pF, T = +25°C. (Continued)
S
L
A
0.5
300
250
200
150
100
50
0.0
TPHL_8
TPHL_12
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
TPHL_18
IIH_18
IIH_8
TPLH_8
IIL_8
TPLH_18
IIL_18
TPLH_12
0
-55
25
TEMPERATURE (°C)
125
-55
25
TEMPERATURE (°C)
125
FIGURE 11. INPUT CURRENT vs TEMPERATURE AND BIAS VOLTAGE
FIGURE 12. PROPAGATION DELAY vs TEMPERATURE
70
TR_12
65
60
55
50
45
40
35
TR_18
OUTPUT 2V/DIV
TF_12
TF_8
TF_18
125
INPUT 5V/DIV
TR_8
-55
25
TEMPERATURE (°C)
1µs/DIV
FIGURE 13. RISE/FALL TIME vs TEMPERATURE
FIGURE 14. 1MHz AT 8V BIAS
OUTPUT 5V/DIV
INPUT 5V/DIV
OUTPUT 2V/DIV
INPUT 5V/DIV
1µs/DIV
100ns/DIV
FIGURE 15. 1MHz AT 18V BIAS
FIGURE 16. 8V RISING/FALLING PROPAGATION TIME
FN8747.1
July 1, 2015
Submit Document Feedback
9
HS-4424DRH
Typical Performance Curves Unless otherwise specified, V = 8V, 12V, 18V, C = 4300pF, T = +25°C. (Continued)
S
L
A
OUTPUT 2V/DIV
OUTPUT 5V/DIV
INPUT 5V/DIV
INPUT 5V/DIV
100ns/DIV
100ns/DIV
FIGURE 17. 12V RISING/FALLING PROPAGATION TIME
FIGURE 18. 18V RISING/FALLING PROPAGATION TIME
18V BIAS
12V BIAS
18V BIAS
12V BIAS
8V BIAS
8V BIAS
20ns/DIV
20ns/DIV
FIGURE 19. RISE TIME
FIGURE 20. FALL TIME
1000
100
10
1
°
MAX TEMP = 100 C
0.1
0.01
0
1
2
3
4
5
6
7
VCC (V)
FIGURE 21. UVLO OUTPUT HIGH Z vs VCC
FIGURE 22. 18V, 1MHz OPERATING IR TEMP
FN8747.1
July 1, 2015
Submit Document Feedback
10
HS-4424DRH
Post High, Low Dose Rate Radiation Characteristics Unless otherwise specified,
VS = 12V, TA = +25°C. This data is typical mean test data post 300kRAD (Si) radiation exposure at a high dose exposure rate of 50 to 300rad(Si)/s and
post 50kRAD (Si) radiation exposure at a high dose exposure rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to high
dose rate radiation. These are not limits nor are they guaranteed.
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.5
0
I
HIGH
CCSB
I
B
IH
I
A
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
IH
I
B
IL
I
LOW
CCSB
I
A
IL
0
300
0
300
krad(Si)
krad(Si)
FIGURE 23. 18V SUPPLY CURRENT vs HDR RADIATION
FIGURE 24. 18V INPUT CURRENT vs HDR RADIATION
205
11.50
11.49
11.48
11.47
11.46
11.45
11.44
11.43
11.42
11.41
11.40
0.360
0.355
0.350
0.345
0.340
0.335
0.330
0.325
0.320
0.315
0.310
200
195
190
185
180
175
170
165
t
A
PHL
t
A
PLH
V
B
OL
V
A
OL
t
B
PHL
t
B
PLH
V
B
OH
V
A
OH
0
300
300
0
krad(Si)
krad(Si)
FIGURE 25. OUTPUT VOLTAGE vs HDR RADIATION
FIGURE 26. PROPAGATION DELAY vs HDR RADIATION
65.0
t B
64.5
64.0
63.5
63.0
62.5
62.0
f
t B
r
t A
f
t A
r
0
300
krad(Si)
FIGURE 27. RISE/FALL TIME vs HDR RADIATION
FN8747.1
July 1, 2015
Submit Document Feedback
11
HS-4424DRH
Post High, Low Dose Rate Radiation Characteristics Unless otherwise specified,
VS = 12V, TA = +25°C. This data is typical mean test data post 300kRAD (Si) radiation exposure at a high dose exposure rate of 50 to 300rad(Si)/s and
post 50kRAD (Si) radiation exposure at a high dose exposure rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to high
dose rate radiation. These are not limits nor are they guaranteed. (Continued)
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.2
0
I
B
I
HIGH
IH
I A
IH
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
CCSB
I
LOW
CCSB
I
B
IL
I
A
IL
0
50
0
50
krad(Si)
krad(Si)
FIGURE 28. 18V SUPPLY CURRENT vs LDR RADIATION
FIGURE 29. 18V INPUT CURRENT vs LDR RADIATION
11.50
0.302
170
168
166
164
162
160
158
156
154
11.49
11.48
11.47
11.46
11.45
11.44
11.43
11.42
11.41
11.40
0.300
0.298
0.296
0.294
0.292
0.290
0.288
0.286
0.284
0.282
t
A
PHL
t
A
PLH
V
A
OL
V
A
OH
t
B
PLH
V
B
OH
V
B
t
B
OL
PHL
0
50
0
50
krad(Si)
krad(Si)
FIGURE 30. OUTPUT VOLTAGE vs LDR RADIATION
FIGURE 31. PROPAGATION DELAY vs LDR RADIATION
58
56
54
52
50
48
46
44
42
t A
r
t B
r
t B
f
t A
f
40
0
50
krad(Si)
FIGURE 32. RISE/FALL TIME vs LDR RADIATION
FN8747.1
July 1, 2015
Submit Document Feedback
12
HS-4424DRH
Power Dissipation and Junction Temperature
It is possible to exceed the +150°C maximum recommended
junction temperature under certain load and power supply
conditions.
Applications Information
Functional Description
The HS-4424DRH MOSFET driver is designed for easy
implementation with a PWM controller, such as the HS1825ARH,
as the input control signal driver. The HS-4424DRH consists of
two independent drivers sharing bias voltage and ground
connections at the die level.
Calculate power dissipation using Equation 1;
2
(EQ. 1)
Pd = V I + 2 C V f
Where
Undervoltage Lockout and Operating Voltage
Range
Pd = Power dissipation
V = Supply voltage
I = Operating supply current
C = Load capacitance
f = Operating frequency
The HS-4424DRH has a guaranteed UVLO of <8V across the
operating temperature range. All devices are recommended to
operate up to and are characterized and tested at a bias of 18V.
The UVLO feature ensures that the internal MOSFET drivers have
sufficient gate drive to operate in their saturated mode. When in
a UVLO condition the HS-4424DRH output is put into a high
impedance tri-stated mode.
Calculate junction temperature TJ using Equation 2:
(EQ. 2)
T
= Pd Theta JC + T
C
J
Characterization and testing occurs (as appropriate) at 8V, 12V
and 18V and across the -55°C to +125°C operating temperature
range.
Where
TJ = Junction temperature
Pd = Power dissipation
Theta JC = Junction-to-case thermal resistance
TC = Case temperature
Input Characteristics
The HS-4424DRH input is designed to be used with low voltage
level signals (<1V for a low input level and >3V for a high input
level) and also be capable of accepting input voltages up to the
VCC level.
PCB Layout Guidelines
Use a ground plane in the PCB design, connect GND A and GND B
pins directly to the ground plane in the same area, preferably
close to the IC. Reference all input circuitry including IN A and IN
B to a common node and reference all output circuitry including
all OUT A and OUT B pins to a common node.
Output Buffer
The HS-4424DRH output buffer is designed to drive >2A of peak
output current into high capacitance loads and can be paralleled
to increase the output current capability.
Bypass each VCC pin to the ground plane with a 0.047µF ceramic
chip capacitor in parallel with a 4.7µF low ESR solid tantalum
capacitor.
The output buffer uses a final drive stage comprised of a PNP
lower and NPN upper complimentary pair of transistors for the
high output current drive. To enhance the pull-up and pull-down
of this bipolar pair, they are each paralleled with MOS devices to
do so.
Clamp both OUT pins to VCC, each with a single diode. The
1n5819 (1A, 40V) Schottky diode is recommended.
FN8747.1
July 1, 2015
Submit Document Feedback
13
HS-4424DRH
Assembly Related Information
Die Characteristics
SUBSTRATE POTENTIAL
Die Dimensions
Floating (DI)
4890µm x 3370µm (193 mils x 133 mils)
Thickness: 483µm ±25.4µm (19mils ±1mil)
LID POTENTIAL
Floating
Interface Materials
GLASSIVATION
Additional Information
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0kÅ ±1.0kÅ
WORST CASE CURRENT DENSITY
< 2 x 105 A/cm2
TOP METALLIZATION
TRANSISTOR COUNT
Type: AlSiCu
Thickness: 16.0kÅ ±2kÅ
125
Weight of Packaged Device
BACKSIDE FINISH
0. 591 grams (typical)
Silicon
PROCESS
Lid Characteristics
Radiation Hardened Silicon Gate (DI)
Finish: Gold
Case isolation to any lead: 20 x 109Ω (minimum)
Metallization Mask Layout
GND (5)
GND (4)
IN A (2)
IN B (7)
OUT B (10)
OUT B (11)
OUT A (15)
OUT A (14)
V
(12)
V
(13)
CC
CC
FN8747.1
July 1, 2015
Submit Document Feedback
14
HS-4424DRH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
FN8747.1
CHANGE
Junly 1, 2015
Abs Max ratings on page 4 - removed abs max input current and related text on page 13.
ESD Ratings - changed Machine Model from: 1kV to: 200V and Charged Device Model from: 4kV to: 750V
Changed over temp limits for UVLO Rising from: MIN/MAX 7.0/7.9 to: 6.9/7.95 and Falling MIN/MAX from:
6.9/7.85 to: 6.8/7.9.
Changed over temp 8V, 5mA VOH limit MIN from VS - 0.75 to VS - 0.9.
Initial Release
June 8, 2015
FN8747.0
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8747.1
July 1, 2015
Submit Document Feedback
15
HS-4424DRH
Package Outline Drawing
K16.A
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 2, 1/10
0.015 (0.38)
PIN NO. 1
1
2
0.008 (0.20) ID OPTIONAL
0.050 (1.27 BSC)
PIN NO. 1
ID AREA
0.440 (11.18)
MAX
0.005 (0.13)
MIN
4
0.022 (0.56)
0.015 (0.38)
TOP VIEW
0.115 (2.92)
0.009 (0.23)
0.004 (0.10)
0.045 (1.14)
0.026 (0.66)
0.045 (1.14)
6
0.285 (7.24)
0.245 (6.22)
-D-
-H-
-C-
0.370 (9.40)
0.250 (6.35)
0.13 (3.30)
MIN
0.03 (0.76) MIN
SEATING AND
BASE PLANE
LEAD FINISH
SIDE VIEW
NOTES:
Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
1.
0.006 (0.15)
0.004 (0.10)
LEAD FINISH
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
0.009 (0.23)
0.004 (0.10)
BASE
METAL
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
0.019 (0.48)
0.015 (0.38)
4. Measure dimension at all four corners.
0.0015 (0.04)
MAX
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
0.022 (0.56)
0.015 (0.38)
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
3
SECTION A-A
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Controlling dimension: INCH.
FN8747.1
July 1, 2015
Submit Document Feedback
16
相关型号：
HS-46508100B
133MHz FSB Socket 370 Embedded Engine Board with CRT/Panel, Audio, four LAN & TV-Out
BOSER
HS-465082559
133MHz FSB Socket 370 Embedded Engine Board with CRT/Panel, Audio, four LAN & TV-Out
BOSER
©2020 ICPDF网 联系我们和版权申明