首页 |元器件品牌

HS0-26CLV31RH/SAMPLE [RENESAS]

LINE RECEIVER;
HS0-26CLV31RH/SAMPLE
型号： HS0-26CLV31RH/SAMPLE
厂家： RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述：

LINE RECEIVER

接口集成电路
文件： 总3页 (文件大小：293K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
Radiation Hardened 3.3V Quad Differential Line  
Drivers  
HS-26CLV31RH, HS-26CLV31EH  
Features  
The Intersil HS-26CLV31RH, HS-26CLV31EH are radiation  
hardened 3.3V quad differential line drivers designed for  
digital data transmission over balanced lines, in low voltage,  
RS-422 protocol applications. CMOS processing assures low  
power consumption, high speed, and reliable operation in the  
most severe radiation environments.  
• Electrically screened to SMD # 5962-96663  
• QML qualified per MIL-PRF-38535 requirements  
• 1.2 micron radiation hardened CMOS  
- Total dose . . . . . . . . . . . . . . . . . . . . . . . . 300 krad (Si) (max)  
2
- Single event upset LET . . . . . . . . . . . . . 100MeV/mg/cm )  
- Single event latch-up immune  
The HS-26CLV31RH, HS-26CLV31EH accept CMOS level inputs  
and converts them to differential outputs. Enable pins allow  
several devices to be connected to the same data source and  
addressed independently. These devices have unique outputs that  
become high impedance when the driver is disabled or  
powered-down, maintaining signal integrity in multi-driver  
applications.  
• Extremely low stand-by current . . . . . . . . . . . . . 100µA (max)  
• Operating supply range . . . . . . . . . . . . . . . . . . . . . 3.0V to 3.6V  
• CMOS level inputs . . . . . . .V > (0.7) (V ); V < (0.3) (V  
)
IH DD IL DD  
• Differential outputs . . . . . . . . . . . . . . . V > 1.8V; V < 0.5V  
OH OL  
• High impedance outputs when disabled or powered down  
• Low output impedance . . . . . . . . . . . . . . . . . . . . . .10Ω or less  
• Full -55°C to +125°C military temperature range  
• Pb-Free (RoHS Compliant)  
Specifications for Rad Hard QML devices are controlled by the  
Defense Logistics Agency Land and Maritime (DLA). The SMD  
numbers listed here must be used when ordering.  
Detailed Electrical Specifications for these devices are  
contained in SMD 5962-96663. A “hot-link” is also provided on  
our homepage for downloading.  
Applications  
• Line transmitter for MIL-STD-1553 serial data bus  
Ordering Information  
ORDERING NUMBER  
(Note 1)  
INTERNAL  
MKT. NUMBER  
PART  
MARKING  
TEMP. RANGE  
(°C)  
PACKAGE  
(RoHS Compliant)  
PKG.  
DWG. #  
5962F9666302QEC  
5962F9666302QXC  
5962F9666302VEC  
5962F9666302VXC  
5962F9666302V9A  
HS1-26CLV31RH/PROTO  
HS9-26CLV31RH/PROTO  
5962F9666304VEC  
5962F9666304VXC  
5962F9666304V9A  
HS0-26CLV31RH/SAMPLE  
5962F9666302VYC  
HS9G-26CLV31RH/PROTO  
NOTES:  
HS1-26CLV31RH-8  
Q 5962F96 66302QEC  
Q 5962F96 66302QXC  
Q 5962F96 66302VEC  
Q 5962F96 66302VXC  
-55 to +125 16 Ld SBDIP  
-55 to +125 16 Ld FLATPACK  
-55 to +125 16 Ld SBDIP  
-55 to +125 16 Ld FLATPACK  
-55 to +125 Die  
D16.3  
HS9-26CLV31RH-8  
K16.A  
D16.3  
K16.A  
HS1-26CLV31RH-Q  
HS9-26CLV31RH-Q  
HS0-26CLV31RH-Q  
HS1-26CLV31RH/PROTO  
HS9-26CLV31RH/PROTO  
HS1-26CLV31EH-Q  
HS1-26CLV31RH/PROTO  
HS9-26CLV31RH/PROTO  
Q 5962F96 66304VEC  
Q 5962F96 66304VXC  
-55 to +125 16 Ld SBDIP  
-55 to +125 16 Ld FLATPACK  
-55 to +125 16 Ld SBDIP  
-55 to +125 16 Ld FLATPACK  
-55 to +125 Die  
D16.3  
K16.A  
D16.3  
K16.A  
HS9-26CLV31EH-Q  
HS0-26CLV31EH-Q  
HS0-26CLV31RH/SAMPLE  
HS9G-26CLV31RH-Q (Note 2)  
-55 to +125 Die  
Q 5962F96 66302VYC  
-55 to +125 16 Ld FLATPACK  
-55 to +125 16 Ld FLATPACK  
K16.A  
K16.A  
HS9G-26CLV31RH/PROTO (Note 2) HS9G-26CLV31RH/PROTO  
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both  
SnPb and Pb-free soldering operations.  
2. The lid of these packages are connected to the ground pin of the device.  
May 23, 2013  
FN4898.4  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2000, 2008, 2009, 2012, 2013. All Rights Reserved  
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.  
1
All other trademarks mentioned are the property of their respective owners.  
HS-26CLV31RH, HS-26CLV31EH  
Pin Configurations  
HS1-26CLV31RH, HS1-26CLV31EH  
HS9-26CLV31RH, HS9-26CLV31EH  
(16 LD SBDIP)  
CDIP2-T16  
TOP VIEW  
(16 LD FLATPACK)  
CDFP4-F16  
TOP VIEW  
AIN  
AO  
1
2
3
4
5
6
7
8
16 VDD  
15 DIN  
14 DO  
AIN  
AO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VDD  
DIN  
AO  
DO  
AO  
ENABLE  
BO  
DO  
ENABLE  
BO  
13 DO  
ENABLE  
CO  
12 ENABLE  
11 CO  
BO  
BO  
BIN  
CO  
10 CO  
BIN  
GND  
CIN  
9
CIN  
GND  
Logic Diagram  
ENABLE ENABLE  
DIN  
CIN  
BIN  
AIN  
DO DO  
CO CO  
BO BO  
AO AO  
For additional products, see www.intersil.com/product_tree  
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted  
in the quality certifications found at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time  
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be  
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third  
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN4898.4  
May 23, 2013  
2
HS-26CLV31RH, HS-26CLV31EH  
Die Characteristics  
DIE DIMENSIONS:  
Substrate:  
96.5 mil x 195 mils x 21 mils  
(2450 x 4950)  
AVLSI1RA  
Backside Finish:  
INTERFACE MATERIALS:  
Glassivation:  
Silicon  
ASSEMBLY RELATED INFORMATION:  
Substrate Potential (Powered Up):  
Type: PSG (Phosphorus Silicon Glass)  
Thickness: 8kÅ ±1kÅ  
V
DD  
Metallization:  
ADDITIONAL INFORMATION:  
Worst Case Current Density:  
Bottom: Mo/TiW  
Thickness: 5800Å ±1kÅ  
Top: AlSiCu (Top)  
5
2
<2.0 x 10 A/cm  
Thickness: 10kÅ ±1kÅ  
Bond Pad Size:  
110µm x 100µm  
Metallization Mask Layout  
HS-26CLV31RH, HS-26CLV31EH  
TABLE 1. HS-26CLV31RH, HS-26CLV31EH PAD COORDINATES  
RELATIVE TO PIN 1  
PIN  
PAD  
NUMBER  
NAME  
X COORDINATES Y COORDINATES  
1
2
AIN  
A0  
0
0
0
-570.7  
-1483.5  
-2124.8  
-2873.5  
-3786.3  
-4357  
-4357  
-4357  
-4357  
-3786.3  
-2873.5  
-2124.8  
-1483.5  
-570.7  
0
AO (2)  
(14) DO  
3
A0  
0
4
ENABLE  
B0  
0
5
0
6
B0  
0
AO (3)  
(13) DO  
7
BIN  
0
8
GND  
GND  
CIN  
852.4  
1062.4  
1912.8  
1912.8  
1912.8  
1912.8  
1912.8  
1912.8  
1912.8  
1062.4  
852.4  
8
ENABLE (4)  
(12) ENABLE  
9
10  
11  
12  
13  
14  
15  
16  
16  
C0  
C0  
ENABLE  
D0  
(11) CO  
BO (5)  
D0  
DIN  
VIN  
0
BO (6)  
(10) CO  
VIN  
0
NOTE: Dimensions in microns  
FN4898.4  
May 23, 2013  
3

相关型号：

HS0-26CLV32EH-Q

 Line Receiver
RENESAS

HS0-26CLV32RH-Q

 Radiation Hardened 3.3V Quad Differential Line Receiver
INTERSIL

HS0-26CLV32RH/SAMPLE

 Line Receiver
RENESAS

HS0-26CT31RH-Q

 Radiation Hardened Quad Differential Line Driver
INTERSIL

HS0-26CT32RH-Q

 Radiation Hardened Quad Differential Line Receiver
INTERSIL

HS0-302AEH-Q

 DPST
RENESAS

HS0-302AEH/SAMPLE

 DPST
RENESAS

HS0-302EH-Q

 Radiation Hardened CMOS Dual DPST Analog Switch
INTERSIL

HS0-302RH-Q

 DUAL 2-CHANNEL, DBL POLE SGL THROW SWITCH, UUC, DIE
RENESAS

HS0-302RH/SAMPLE

 DPST
RENESAS

HS0-303AEH-Q

 Radiation Hardened CMOS Dual SPDT Analog Switch
INTERSIL

HS0-303AEH-Q

 SGL POLE DOUBLE THROW SWITCH
RENESAS
©2020 ICPDF网 联系我们和版权申明