ICL3221EIV [RENESAS]
LINE TRANSCEIVER, PDSO16, PLASTIC, MO-153AB, TSSOP-16;
| 型号： | ICL3221EIV |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | LINE TRANSCEIVER, PDSO16, PLASTIC, MO-153AB, TSSOP-16 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总35页 (文件大小：1633K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
±15kV ESD Protected, +3V to +5.5V, 1µA, 250kbps, RS-232 Transmitters/Receivers
FN4910
Rev 23.00
Sep 24, 2018
The ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E,
and ICL3243E are 3.0V to 5.5V powered RS-232
transmitters/receivers which meet ElA/TIA-232 and
Features
• ESD protection for RS-232 I/O pins to ±15kV
(IEC61000)
V.28/V.24 specifications, even at V = 3.0V.
CC
• Drop-in replacements for the MAX3221E,
MAX3222E, MAX3223E, MAX3232E, MAX3241E,
MAX3243E, and SP3243E
Additionally, they provide ±15kV ESD protection
(IEC61000-4-2 Air Gap and Human Body Model) on
transmitter outputs and receiver inputs (RS-232 pins).
Targeted applications are notebook and laptop
computers in which the low operational power
• The ICL3221E is a low-power, pin-compatible
upgrade for the 5V MAX221E
consumption and even lower standby power
• The ICL3222E is a low-power, pin-compatible
upgrade for the 5V MAX242E and SP312E
consumption is critical. Efficient on-chip charge pumps,
coupled with manual and automatic power-down
functions (except for the ICL3232E), reduce the
standby supply current to a 1µA trickle. Small footprint
packaging and the use of small, low value capacitors
ensure board space savings. Data rates greater than
250kbps are ensured at worst case load conditions.
This family is fully compatible with 3.3V-only systems,
mixed 3.3V and 5.0V systems, and 5.0V-only systems.
• The ICL3232E is a low-power upgrade for the
HIN232E, ICL232, and pin-compatible competitor
devices
• RS-232 compatible with V
CC
= 2.7V
• Meets EIA/TIA-232 and V.28/V.24 specifications at 3V
• Latch-up free
• On-chip voltage converters require only four
The ICL324XE are 3-driver, 5-receiver devices that
provide a complete serial port suitable for laptop or
notebook computers. Both devices also include
noninverting always-active receivers for “wake-up”
capability.
external 0.1µF capacitors at V
= 3.3V
CC
• Manual and automatic power-down features
• Guaranteed mouse driveability (ICL324xE only)
• Receiver hysteresis for improved noise immunity
• Guaranteed minimum data rate: 250kbps
• Wide power supply range: single +3V to +5.5V
• Low supply current in power-down state: 1µA
• Pb-free available (RoHS compliant)
The ICL3221E, ICL3223E, and ICL3243E feature an
automatic power-down function that powers down the
on-chip power supply and driver circuits. Power-down
occurs when an attached peripheral device is shut off
or the RS-232 cable is removed, conserving system
power automatically without changes to the hardware
or operating system. These devices power up again
when a valid RS-232 voltage is applied to any receiver
input.
Applications
• Any system requiring RS-232 communication ports
- Battery powered, hand-held, and portable
equipment
- Laptop computers and notebooks
- Modems, printers, and other peripherals
- Digital cameras
Table 1 summarizes the features of the devices
represented by this datasheet, and AN9863
summarizes the features of each device in the
ICL32xxE 3V family.
- Cellular/mobile phones
Related Literature
For a full list of documents, visit our website:
• ICL3221E, ICL3222E, ICL3223E, ICL3232E,
ICL3241E, and ICL3243E product information
pages
FN4910 Rev 23.00
Sep 24, 2018
Page 1 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
TABLE 1. SUMMARY OF FEATURES
NUMBER OF
MONITOR
NUMBER NUMBER RECEIVERS
DATA
RATE
(kbps) FUNCTION?
RECEIVER
ENABLE
AUTOMATIC
POWER-DOWN
FUNCTION?
PART
NUMBER
READY
MANUAL
OF Tx
OF Rx
(R
)
OUTPUT? POWER-DOWN?
OUTB
ICL3221E
ICL3222E
ICL3223E
ICL3232E
ICL3241E
ICL3243E
1
2
2
2
3
3
1
2
2
2
5
5
0
250
250
250
250
250
250
Yes
Yes
Yes
No
No
No
No
No
No
No
Yes
Yes
Yes
No
Yes
No
0
0
0
2
1
Yes
No
Yes
No
Yes
Yes
No
Yes
FN4910 Rev 23.00
Sep 24, 2018
Page 2 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Contents
Typical Operating Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Charge-Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Low Power Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin-Compatible Replacements for 5V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-Down Functionality (Except ICL3232E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Software Controlled (Manual) Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Automatic Power-Down (ICL3221E, ICL3223E, and ICL3243E Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Receiver ENABLE Control (ICL3221E, ICL3222E, ICL3223E, and ICL3241E Only) . . . . . . . . . . . . . . . . . . . 18
Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operation Down to 2.7V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Transmitter Outputs when Exiting Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Mouse Driveability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
High Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Interconnection with 3V and 5V Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
±15kV ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Human Body Model (HBM) Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
IEC61000-4-2 Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Die Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
FN4910 Rev 23.00
Sep 24, 2018
Page 3 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Operating Circuits
ICL3221E
C
(OPTIONAL CONNECTION, NOTE)
3
+3.3V
+
0.1µF
15
2
+
4
C
0.1µF
3
C1+
1
V
CC
C
0.1µF
3
+
V+
V-
C1-
5
C
0.1µF
2
C2+
+
7
C
4
0.1µF
6
C2-
+
T
1
11
9
13
T1
T1
OUT
IN
TTL/CMOS
RS-232
LOGIC LEVELS
8
LEVELS
R1
R1
IN
OUT
5kΩ
R
1
1
EN
16
10
V
CC
FORCEOFF
INVALID
12
TO POWER
CONTROL LOGIC
FORCEON
GND
14
NOTE: THE NEGATIVE TERMINAL OF C3 CAN BE CONNECTED TO EITHER VCC OR GND
ICL3222E
C
(OPTIONAL CONNECTION, NOTE)
3
+3.3V
C
+
0.1µF
17
2
3
C1+
1
V
CC
+
+
C
0.1µF
3
+
+
V+
V-
0.1µF
4
5
C1-
C
0.1µF
2
C2+
7
C
4
0.1µF
6
C2-
T
T
1
2
12
15
8
T1
T2
T1
T2
IN
IN
OUT
OUT
11
13
TTL/CMOS
RS-232
LOGIC LEVELS
14
9
LEVELS
R1
R1
R2
OUT
IN
IN
5kΩ
R
1
10
1
R2
OUT
5kΩ
R
2
EN
18
V
CC
SHDN
GND
16
NOTE: THE NEGATIVE TERMINAL OF C3 CAN BE CONNECTED TO EITHER VCC OR GND
FN4910 Rev 23.00
Sep 24, 2018
Page 4 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Operating Circuits(Continued)
ICL3223E
+3.3V
+
0.1µF
19
2
+
4
C
0.1µF
C1+
1
V
3
CC
C
0.1µF
3
+
V+
V-
C1-
5
C
0.1µF
2
C2+
+
7
C
4
0.1µF
6
C2-
+
T
T
1
2
13
17
8
T1
T2
T1
T2
IN
IN
OUT
OUT
12
15
TTL/CMOS
RS-232
LOGIC LEVELS
16
9
LEVELS
R1
R2
R1
R2
OUT
OUT
IN
IN
5kΩ
5kΩ
R
1
10
1
R
2
EN
20
11
V
FORCEOFF
INVALID
CC
14
TO POWER
CONTROL LOGIC
FORCEON
GND
18
ICL3232E
+3.3V
C
C
(OPTIONAL CONNECTION, NOTE)
+
3
0.1µF
16
1
C
0.1µF
C1+
1
V
2
6
CC
+
+
3
+
V+
V-
3
4
0.1µF
C1-
C
0.1µF
2
C2+
C
4
5
C2-
0.1µF
+
T
T
1
2
11
14
T1
T2
T1
IN
OUT
OUT
7
10
12
T2
IN
TTL/CMOS
LOGIC LEVELS
RS-232
13
LEVELS
R1
R1
OUT
IN
R
5kΩ
5kΩ
1
9
8
R2
R2
OUT
IN
R
2
GND
15
NOTE: THE NEGATIVE TERMINAL OF C3 CAN
BE CONNECTED TO EITHER VCC OR GND
FN4910 Rev 23.00
Sep 24, 2018
Page 5 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Operating Circuits(Continued)
ICL3241E
ICL3243E
+3.3V
+
+3.3V
0.1µF
28
+
26
0.1µF
26
27
C
0.1µF
C1+
1
V
CC
C
3
0.1µF
27
3
28
+
24
C
0.1µF
+
3
+
C
0.1µF
+
V+
V-
C1+
V
CC
1
V+
V-
24
C1-
1
2
C1-
C
0.1µF
2
C2+
1
+
3
9
C
2
0.1µF
C
4
C2+
C
4
0.1µF
+
C2-
0.1µF
2
+
+
C2-
T
T
T
1
2
3
T
T
T
1
2
3
14
9
14
T1
IN
T1
IN
T1
OUT
T1
OUT
13
10
11
10
11
RS-232
LEVELS
13
12
T2
T3
IN
IN
RS-232
LEVELS
T2
T3
IN
IN
T2
T3
OUT
OUT
T2
T3
OUT
OUT
12
21
R1
R2
OUTB
OUTB
20
19
20
19
R2
OUTB
4
5
4
5
R1
TTL/CMOS
LOGIC
LEVELS
OUT
R1
R1
R2
OUT
IN
R1
R2
IN
IN
R
5kΩ
5kΩ
1
R
TTL/CMOS
LOGIC
LEVELS
1
2
5kΩ
5kΩ
5kΩ
18
17
16
R2
18
OUT
R2
OUT
IN
R
2
R
6
7
8
R3
R4
R5
OUT
OUT
OUT
17
16
6
7
RS-232
LEVELS
R3
R4
R5
RS-232
LEVELS
IN
IN
IN
R3
R4
R3
R4
5kΩ
OUT
IN
R
R
3
4
R
R
3
4
OUT
IN
5kΩ
5kΩ
5kΩ
5kΩ
15
23
15
23
8
EN
R
R5
R5
5
OUT
IN
R
5
22
FORCEON
V
CC
SHDN
GND
22
21
25
V
CC
FORCEOFF
INVALID
TO POWER
CONTROL
LOGIC
GND
25
FN4910 Rev 23.00
Sep 24, 2018
Page 6 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Pin Configurations
ICL3221E
(16 LD SSOP, TSSOP)
TOP VIEW
ICL3222E
(18 LD PDIP, SOIC)
TOP VIEW
EN
C1+
V+
1
2
3
4
5
6
7
8
16 FORCEOFF
15 VCC
EN
C1+
V+
1
2
3
4
5
6
7
8
9
18 SHDN
17 VCC
14 GND
16 GND
15 T1OUT
14 R1IN
13 R1OUT
12 T1IN
11 T2IN
13 T1OUT
12 FORCEON
11 T1IN
C1-
C2+
C2-
V-
C1-
C2+
C2-
10 INVALID
V-
R1IN
9
R1OUT
T2OUT
R2IN
10
R2OUT
ICL3222E
ICL3223E
(20 LD SSOP, TSSOP)
(20 LD SSOP, TSSOP)
TOP VIEW
TOP VIEW
EN
1
2
20 FORCEOFF
EN
C1+
1
2
20 SHDN
19 VCC
18 GND
17 T1OUT
16 R1IN
15 R1OUT
14 NC
C1+
V+
19 VCC
3
18 GND
3
V+
17 T1OUT
16 R1IN
C1-
4
C1-
4
C2+
5
C2+
5
C2-
6
15 R1OUT
14 FORCEON
13 T1IN
C2-
6
V-
7
V-
7
T2OUT
R2IN
R2OUT
8
T2OUT
R2IN
R2OUT
8
13 T1IN
9
12
T2IN
9
12
T2IN
10
11 INVALID
10
11 NC
ICL3232E
ICL3232E
(16 LD SOIC, SSOP, TSSOP-16)
(20 LD TSSOP-20)
TOP VIEW
TOP VIEW
C1+
V+
1
2
3
4
5
6
7
8
16 VCC
NC
C1+
V+
1
2
20 NC
15 GND
14 T1OUT
13 R1IN
12 R1OUT
11 T1IN
10 T2IN
19 VCC
C1-
3
18 GND
17 T1OUT
16 R1IN
15 R1OUT
14 T1IN
C2+
C2-
C1-
4
C2+
C2-
5
V-
6
T2OUT
R2IN
V-
7
9
R2OUT
T2OUT
R2IN
NC
8
13
12
T2IN
R2OUT
9
10
11 NC
FN4910 Rev 23.00
Sep 24, 2018
Page 7 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Pin Configurations(Continued)
ICL3241E
(28 LD SOIC, SSOP, TSSOP)
TOP VIEW
ICL3243E
(28 LD SOIC, SSOP, TSSOP)
TOP VIEW
C2+
C2-
1
2
28 C1+
27 V+
C2+
C2-
1
2
28 C1+
27 V+
3
26 VCC
25 GND
24 C1-
V-
3
26 VCC
V-
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T2OUT
4
25 GND
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T2OUT
4
5
5
24 C1-
6
23 EN
6
23 FORCEON
22 FORCEOFF
21 INVALID
7
22 SHDN
21 R1OUTB
7
8
8
9
20
R2OUTB
9
20
R2OUTB
10
19 R1OUT
18 R2OUT
17 R3OUT
16 R4OUT
15 R5OUT
10
19 R1OUT
18 R2OUT
17 R3OUT
16 R4OUT
15 R5OUT
T3OUT 11
T3IN 12
T2IN 13
T1IN 14
T3OUT 11
T3IN 12
T2IN 13
T1IN 14
Pin Descriptions
PIN
FUNCTION
VCC
V+
System power supply input (3.0V to 5.5V)
Internally generated positive transmitter supply (+5.5V)
Internally generated negative transmitter supply (-5.5V)
Ground connection
V-
GND
C1+
C1-
External capacitor (voltage doubler) is connected to this lead
External capacitor (voltage doubler) is connected to this lead
External capacitor (voltage inverter) is connected to this lead
External capacitor (voltage inverter) is connected to this lead
TTL/CMOS compatible transmitter inputs
C2+
C2-
TIN
TOUT
RIN
15kV ESD protected, RS-232 level (nominally 5.5V) transmitter outputs
15kV ESD protected, RS-232 compatible receiver inputs
TTL/CMOS level receiver outputs
ROUT
ROUTB
TTL/CMOS level, noninverting, always enabled receiver outputs
INVALID Active low output that indicates no valid RS-232 levels are present on any receiver input
EN
Active low receiver enable control; does not disable R
outputs
OUTB
SHDN
Active low input to shut down transmitters and on-board power supply to place device in low-power mode
FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and
FORCEON (see Table 2 on page 16)
FORCEON Active high input to override automatic power-down circuitry, which keeps transmitters active (FORCEOFF must be
high)
FN4910 Rev 23.00
Sep 24, 2018
Page 8 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Ordering Information
TEMP
PART NUMBER
(Notes 2, 3)
PART
MARKING
RANGE
(°C)
TAPE AND REEL
(UNITS) (Note 1)
PKG.
DWG. #
PACKAGE
ICL3221ECAZ
ICL32 21ECAZ
ICL32 21ECAZ
ICL32 21ECAZ
ICL32 21EIAZ
ICL32 21EIAZ
ICL32 21EIAZ
3221 EIVZ
0 to +70
0 to +70
-
1k
250
-
16 Ld SSOP (Pb-free) M16.209
16 Ld SSOP (Pb-free) M16.209
16 Ld SSOP (Pb-free) M16.209
16 Ld SSOP (Pb-free) M16.209
16 Ld SSOP (Pb-free) M16.209
16 Ld SSOP (Pb-free) M16.209
16 Ld TSSOP (Pb-free) M16.173
16 Ld TSSOP (Pb-free) M16.173
16 Ld TSSOP (Pb-free) M16.173
20 Ld SSOP (Pb-free) M20.209
20 Ld SSOP (Pb-free) M20.209
ICL3221ECAZ-T
ICL3221ECAZ-T7A
ICL3221EIAZ
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
ICL3221EIAZ-T
ICL3221EIAZ-T7A
ICL3221EIVZ
1k
250
-
ICL3221EIVZ-T
ICL3221EIVZ-T7A
ICL3222ECAZ
3221 EIVZ
2.5k
250
-
3221 EIVZ
ICL32 22ECAZ
ICL32 22ECAZ
ICL3222ECAZ-T
0 to +70
1k
-
ICL3222ECP (No longer available, no ICL3222ECP
0 to +70
18 Ld PDIP
E18.3
recommended replacement)
ICL3222ECVZ
ICL3222ECVZ-T
ICL3222EIAZ
ICL32 22ECVZ
ICL32 22ECVZ
ICL32 22EIAZ
ICL32 22EIAZ
3222EIBZ
0 to +70
0 to +70
-
2.5k
-
20 Ld TSSOP (Pb-free) M20.173
20 Ld TSSOP (Pb-free) M20.173
20 Ld SSOP (Pb-free) M20.209
20 Ld SSOP (Pb-free) M20.209
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
ICL3222EIAZ-T
ICL3222EIBZ
1k
-
18 Ld SOIC (Pb-free)
18 Ld SOIC (Pb-free)
M18.3
M18.3
ICL3222EIBZ-T
ICL3222EIVZ
3222EIBZ
1k
-
ICL32 22EIVZ
ICL32 22EIVZ
ICL32 23ECAZ
ICL32 23ECAZ
ICL32 23ECVZ
ICL32 23ECVZ
ICL32 23EIAZ
ICL32 23EIAZ
ICL32 23EIVZ
ICL32 23EIVZ
3232 ECAZ
20 Ld TSSOP (Pb-free) M20.173
20 Ld TSSOP (Pb-free) M20.173
20 Ld SSOP (Pb-free) M20.209
20 Ld SSOP (Pb-free) M20.209
20 Ld TSSOP (Pb-free) M20.173
20 Ld TSSOP (Pb-free) M20.173
20 Ld SSOP (Pb-free) M20.209
20 Ld SSOP (Pb-free) M20.209
20 Ld TSSOP (Pb-free) M20.173
20 Ld TSSOP (Pb-free) M20.173
16 Ld SSOP (Pb-free) M16.209
16 Ld SSOP (Pb-free) M16.209
16 Ld SSOP (Pb-free) M16.209
ICL3222EIVZ-T
ICL3223ECAZ
ICL3223ECAZ-T
ICL3223ECVZ
ICL3223ECVZ-T
ICL3223EIAZ
2.5k
-
0 to +70
1k
-
0 to +70
0 to +70
2.5k
-
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
ICL3223EIAZ-T
ICL3223EIVZ
1k
-
ICL3223EIVZ-T
ICL3232ECAZ
ICL3232ECAZ-T
ICL3232ECAZ-T7A
ICL3232ECBZ
ICL3232ECBZ-T
ICL3232ECBNZ
ICL3232ECBNZ-T
ICL3232ECV-16Z
ICL3232ECV-16Z-T
2.5k
-
3232 ECAZ
0 to +70
1k
250
-
3232 ECAZ
0 to +70
3232ECBZ
0 to +70
16 Ld SOIC (Pb-free)
16 Ld SOIC (Pb-free)
16 Ld SOIC (Pb-free)
16 Ld SOIC (Pb-free)
M16.3
3232ECBZ
0 to +70
1k
-
M16.3
3232ECBNZ
3232ECBNZ
3232E CV-16Z
3232E CV-16Z
0 to +70
M16.15
M16.15
0 to +70
2.5k
-
0 to +70
16 Ld TSSOP (Pb-free) M16.173
16 Ld TSSOP (Pb-free) M16.173
0 to +70
2.5k
FN4910 Rev 23.00
Sep 24, 2018
Page 9 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Ordering Information(Continued)
TEMP
PART NUMBER
(Notes 2, 3)
PART
MARKING
RANGE
(°C)
TAPE AND REEL
(UNITS) (Note 1)
PKG.
DWG. #
PACKAGE
ICL3232ECV-20Z(Nolongeravailable, ICL3232 ECV-20Z
recommended replacement:
ICL3232EIV-16Z)
0 to +70
-
20 Ld TSSOP (Pb-free) M20.173
20 Ld TSSOP (Pb-free) M20.173
16 Ld TSSOP (Pb-free) M16.173
16 Ld TSSOP (Pb-free) M16.173
ICL3232ECV-20Z-T (No longer
available, recommended
ICL3232 ECV-20Z
0 to +70
2.5k
-
replacement: ICL3232EIV-16Z-T)
ICL3232EFV-16Z (No longer available, 3232E FV-16Z
recommended replacement:
ICL3232EIV-16Z)
-40 to +125
-40 to +125
ICL3232EFV-16Z-T (No longer
available, recommended
3232E FV-16Z
2.5k
replacement: ICL3232EIV-16Z-T)
ICL3232EIAZ
3232 EIAZ
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
-
1k
-
16 Ld SSOP (Pb-free) M16.209
16 Ld SSOP (Pb-free) M16.209
ICL3232EIAZ-T
ICL3232EIBZ
3232 EIAZ
3232EIBZ
16 Ld SOIC (Pb-free)
16 Ld SOIC (Pb-free)
16 Ld SOIC (Pb-free)
16 Ld SOIC (Pb-free)
M16.3
ICL3232EIBZ-T
ICL3232EIBNZ
ICL3232EIBNZ-T
ICL3232EIV-16Z
ICL3232EIV-16Z-T
ICL3232EIV-20Z
ICL3232EIV-20Z-T
ICL3241ECAZ
3232EIBZ
1k
-
M16.3
3232EIBNZ
M16.15
M16.15
3232EIBNZ
2.5k
-
3232E IV-16Z
3232E IV-16Z
ICL3232 EIV-20Z
ICL3232 EIV-20Z
ICL3241 ECAZ
ICL3241 ECAZ
ICL3241ECBZ
16 Ld TSSOP (Pb-free) M16.173
16 Ld TSSOP (Pb-free) M16.173
20 Ld TSSOP (Pb-free) M20.173
20 Ld TSSOP (Pb-free) M20.173
28 Ld SSOP (Pb-free) M28.209
28 Ld SSOP (Pb-free) M28.209
2.5k
-
2.5k
-
ICL3241ECAZ-T
0 to +70
1k
-
ICL3241ECBZ (No longer available,
recommended replacement:
ICL3241EIVZ)
0 to +70
28 Ld SOIC (Pb-free)
M28.3
ICL3241ECBZ-T (No longer available, ICL3241ECBZ
recommended replacement:
ICL3241EIVZ)
0 to +70
-
28 Ld SOIC (Pb-free)
M28.3
ICL3241ECVZ
ICL3241ECVZ-T
ICL3241EIAZ
ICL3241EIAZ-T
ICL3241 ECVZ
ICL3241 ECVZ
ICL3241 EIAZ
ICL3241 EIAZ
ICL3241EIBZ
0 to +70
0 to +70
-
2.5k
-
28 Ld TSSOP (Pb-free) M28.173
28 Ld TSSOP (Pb-free) M28.173
28 Ld SSOP (Pb-free) M28.209
28 Ld SSOP (Pb-free) M28.209
-40 to +85
-40 to +85
-40 to +85
1k
-
ICL3241EIBZ (No longer available,
recommended replacement:
ICL3241EIVZ)
28 Ld SOIC (Pb-free)
M28.3
ICL3241EIBZ-T (No longer available, ICL3241EIBZ
recommended replacement:
ICL3241EIVZ)
-40 to +85
-
28 Ld SOIC (Pb-free)
M28.3
ICL3241EIVZ
ICL3241EIVZ-T
ICL3243ECAZ
ICL3243ECAZ-T
ICL3243ECBZ
ICL3241 EIVZ
ICL3241 EIVZ
ICL32 43ECAZ
ICL32 43ECAZ
ICL3243ECBZ
-40 to +85
-40 to +85
0 to +70
0 to +70
0 to +70
-
2.5k
-
28 Ld TSSOP (Pb-free) M28.173
28 Ld TSSOP (Pb-free) M28.173
28 Ld SSOP (Pb-free) M28.209
28 Ld SSOP (Pb-free) M28.209
1k
-
28 Ld SOIC (Pb-free)
M28.3
FN4910 Rev 23.00
Sep 24, 2018
Page 10 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Ordering Information(Continued)
TEMP
PART NUMBER
(Notes 2, 3)
PART
MARKING
RANGE
(°C)
TAPE AND REEL
(UNITS) (Note 1)
PKG.
DWG. #
PACKAGE
ICL3243ECBZ-T
ICL3243ECBZ
ICL3243 ECVZ
ICL3243 ECVZ
ICL32 43EIAZ
ICL32 43EIAZ
ICL3243 EIVZ
ICL3243 EIVZ
ICL3243 EIVZ
0 to +70
0 to +70
1k
-
28 Ld SOIC (Pb-free)
M28.3
ICL3243ECVZ
ICL3243ECVZ-T
ICL3243EIAZ
ICL3243EIAZ-T
ICL3243EIVZ
ICL3243EIVZ-T
ICL3243EIVZ-T7A
NOTES:
28 Ld TSSOP (Pb-free) M28.173
28 Ld TSSOP (Pb-free) M28.173
28 Ld SSOP (Pb-free) M28.209
28 Ld SSOP (Pb-free) M28.209
28 Ld TSSOP (Pb-free) M28.173
28 Ld TSSOP (Pb-free) M28.173
28 Ld TSSOP (Pb-free) M28.173
0 to +70
2.5k
-
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
1k
-
2.5k
250
1. Refer to TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), refer to the ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E product
information pages. For more information about MSL, refer to TB363.
FN4910 Rev 23.00
Sep 24, 2018
Page 11 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Absolute Maximum Ratings Thermal Information
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Thermal Resistance (Typical, Note 4)
Θ
(°C/W)
JA
CC
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
18 Ld PDIP Package . . . . . . . . . . . . . . . . . .
16 Ld Wide SOIC Package . . . . . . . . . . . . . .
16 Ld Narrow SOIC Package . . . . . . . . . . . .
18 Ld SOIC Package . . . . . . . . . . . . . . . . . .
28 Ld SOIC Package . . . . . . . . . . . . . . . . . .
16 Ld SSOP Package. . . . . . . . . . . . . . . . . .
20 Ld SSOP Package. . . . . . . . . . . . . . . . . .
16 Ld TSSOP Package. . . . . . . . . . . . . . . . .
20 Ld TSSOP Package. . . . . . . . . . . . . . . . .
28 Ld SSOP and TSSOP Packages. . . . . . . . .
80
100
115
75
T
R
, FORCEOFF, FORCEON, EN, SHDN . . . . . . -0.3V to 6V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±28V
IN
75
IN
Output Voltages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
135
122
145
140
100
T
R
OUT
, INVALID . . . . . . . . . . . . . . . . . -0.3V to V
+0.3V
OUT CC
Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
T
OUT
Maximum Junction Temperature (Plastic Package) . +150°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . see TB493
ESD Rating . . . . . . . See “Electrical Specifications” on page 12
Recommended Operating Conditions
Temperature Range
ICL32xxECX . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ICL32xxEFX . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
ICL32xxEIX. . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . 3.3V or 5V
CC
Rx Input Voltage . . . . . . . . . . . . . . . . . . . . . -15V to +15V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact
product reliability and result in failures not covered by warranty.
NOTE:
4. is measured with the component mounted on a low-effective thermal conductivity test board in free air. See TB379 for
JA
details.
Electrical Specifications Test Conditions: V = 3.0V to 5.5V, C - C = 0.1µF; unless otherwise specified. Typicals are
CC
1
4
at T = +25°C. Boldface limits apply across the operating temperature range.
A
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Note 6)
TYP
(Note 6) UNITS
DC CHARACTERISTICS
Supply Current, Automatic All R Open, FORCEON = GND, FORCEOFF = V
Power-Down
25
25
25
-
-
-
1.0
1.0
0.3
10
10
µA
µA
IN
(ICL3221E, ICL3223E, ICL3243E Only)
CC
Supply Current,
Power-Down
FORCEOFF = SHDN = GND (Except ICL3232E)
Supply Current,
Automatic Power-Down
Disabled
All Outputs Unloaded,
FORCEON=FORCEOFF ICL3243
= SHDN = V
CC
V
= 3.0V, ICL3241,
1.0
mA
CC
V
V
= 3.0V, ICL3223
25
25
-
-
0.7
0.3
3.0
1.0
mA
mA
CC
CC
= 3.15V, ICL3221,
ICL3222, ICL3223,
ICL3232
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low , FORCEON, FORCEOFF, EN, SHDN
Input Logic Threshold High T , FORCEON,
T
Full
Full
Full
Full
Full
Full
-
2.0
2.4
-
-
0.8
-
V
V
IN
V
V
= 3.3V
= 5.0V
-
IN
FORCEOFF, EN, SHDN
CC
CC
-
-
V
Input Leakage Current
T
, FORCEON,
All but ICL3232EF
ICL3232EF
0.01
0.01
0.05
1.0
10
10
µA
µA
µA
IN
FORCEOFF, EN, SHDN
-
Output Leakage Current
(Except ICL3232E)
FORCEOFF = GND or EN = V
-
CC
Output Voltage Low
Output Voltage High
I
I
= 1.6mA
Full
Full
Full
-
-
0.4
V
V
V
OUT
OUT
= -1.0mA
All but ICL3232EF
ICL3232EF
V
V
- 0.6 V
- 0.1
-
-
CC
CC
CC
- 0.9 V
- 0.1
CC
FN4910 Rev 23.00
Sep 24, 2018
Page 12 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Electrical Specifications Test Conditions: V = 3.0V to 5.5V, C - C = 0.1µF; unless otherwise specified. Typicals are
CC
1
4
at T = +25°C. Boldface limits apply across the operating temperature range. (Continued)
A
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Note 6)
TYP
(Note 6) UNITS
AUTOMATIC POWER-DOWN (ICL3221E, ICL3223E, ICL3243E Only, FORCEON = GND, FORCEOFF = V
CC
)
Receiver Input Thresholds ICL32xxE Powers Up (see Figure 6 on page 17)
to Enable Transmitters
Full
Full
Full
Full
25
-2.7
-0.3
-
-
2.7
0.3
0.4
-
V
V
Receiver Input Thresholds ICL32xxE Powers Down (see Figure 6 on
-
-
to Disable Transmitters
page 17)
INVALID Output Voltage
Low
I
= 1.6mA
V
OUT
INVALID Output Voltage
High
I
= -1.0mA
V
- 0.6
-
V
OUT
CC
Receiver Threshold to
Transmitters Enabled Delay
-
-
100
-
µs
(t
)
WU
Receiver Positive or
Negative Threshold to
INVALID High Delay
25
25
1
-
-
µs
µs
(t
INVH)
Receiver Positive or
-
30
Negative Threshold to
INVALID Low Delay (t
RECEIVER INPUTS
Input Voltage Range
Input Threshold Low
INVL)
25
25
25
25
25
25
25
-25
0.6
0.8
-
-
25
-
V
V
V
V
V
V
= 3.3V
= 5.0V
= 3.3V
= 5.0V
1.2
1.5
1.5
1.8
0.5
5
CC
CC
CC
CC
-
V
Input Threshold High
2.4
2.4
-
V
-
V
Input Hysteresis
Input Resistance
-
V
3
7
kΩ
TRANSMITTER OUTPUTS
Output Voltage Swing
Output Resistance
All Transmitter Outputs Loaded with 3kΩ to Ground Full
5.0
300
-
5.4
10M
35
-
-
V
Ω
V
= V+ = V- = 0V, Transmitter Output = 2V
Full
Full
CC
Output Short-Circuit
Current
60
mA
Output Leakage Current
V
=12V, V
CC
= 0V or 3V to 5.5V,
Full
Full
Full
-
-
25
µA
V
OUT
Automatic Power-Down or
FORCEOFF = SHDN = GND
MOUSE DRIVEABILITY (ICL324XE Only)
TransmitterOutputVoltage T1 = T2 = GND, T3 = V , T3
(see Figure 9 on page 19) with 3kΩ to GND, T1
Loaded
5
-
-
IN
IN
IN
CC
OUT
OUT
Loaded with
and T2
OUT
2.5mA Each
TIMING CHARACTERISTICS
Maximum Data Rate
R = 3kΩ, C = 1000pF, One Transmitter
Switching
250
500
-
kbps
L
L
Receiver Propagation Delay Receiver Input to
Receiver Output,
t
t
25
25
-
-
0.15
0.15
-
-
µs
µs
PHL
PLH
C = 150pF
L
Receiver Output Enable
Time
Normal Operation (Except ICL3232E)
25
-
200
-
ns
FN4910 Rev 23.00
Sep 24, 2018
Page 13 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Electrical Specifications Test Conditions: V = 3.0V to 5.5V, C - C = 0.1µF; unless otherwise specified. Typicals are
CC
1
4
at T = +25°C. Boldface limits apply across the operating temperature range. (Continued)
A
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Note 6)
TYP
(Note 6) UNITS
Receiver Output Disable
Time
Normal Operation (Except ICL3232E)
25
-
200
-
ns
Transmitter Skew
t
t
to t
to t
(Note 5)
25
25
25
25
-
-
100
50
-
-
ns
ns
PHL
PLH
PLH
Receiver Skew
-
PHL
Transition Region Slew Rate
V
= 3.3V,
C = 150pF to 2500pF
4
6
30
30
V/µs
V/µs
CC
L
L
R = 3kΩto 7kΩ
Measured from 3V to
-3V or -3V to 3V
C = 150pF to 1000pF
-
L
ESD PERFORMANCE
RS-232 Pins (TOUT, RIN)
Human Body Model
25
25
25
25
-
-
-
-
15
8
-
-
-
-
kV
kV
kV
kV
IEC61000-4-2 Contact Discharge
IEC61000-4-2 Air Gap Discharge
Human Body Model
15
2
All Other Pins
NOTES:
5. Transmitter skew is measured at the transmitter zero crossing points.
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
enters the power-down mode (see Table 2 on page 16).
These outputs can be driven to ±12V when disabled.
Detailed Description
The ICL32xxE interface ICs operate from a single +3V to
+5.5V supply, guarantee a 250kbps minimum data rate,
require only four small external 0.1µF capacitors, feature
low power consumption, and meet all ElA RS-232C and
V.28 specifications. The circuit consists of three sections:
the charge-pump, transmitters, and receivers.
All devices operate at a 250kbps data rate for full load
conditions (3kΩ and 1000pF), V 3.0V, with one
CC
transmitter operating at full speed. Under more typical
conditions of V 3.3V, R = 3kΩ, and C = 250pF, one
CC
L
L
transmitter easily operates at 900kbps.
The transmitter inputs float if left unconnected, and can
Charge-Pump
The ICL32xxE family uses regulated on-chip dual
charge-pumps as voltage doublers, and voltage inverters
increase I . Connect unused inputs to GND for the best
CC
performance.
to generate ±5.5V transmitter supplies from a V
CC
Receivers
supply as low as 3.0V. This allows these devices to
maintain RS-232 compliant output levels over the ±10%
tolerance range of 3.3V powered systems. The efficient
on-chip power supplies require only four small external
0.1µF capacitors for the voltage doubler and inverter
All the ICL32xxE devices contain standard inverting
receivers that three-state (except for the ICL3232E)
from the EN or FORCEOFF control lines. The two
ICL324XE devices include noninverting (monitor)
receivers (denoted by the ROUTB label) that are always
active, regardless of the state of any control lines. All
the receivers convert RS-232 signals to CMOS output
levels and accept inputs up to ±25V while presenting
the required 3kΩ to 7kΩ input impedance (see Figure 1
on page 15) even if the power is off (VCC = 0V). The
receivers’ Schmitt trigger input stage uses hysteresis to
increase noise immunity and decrease errors due to
slow input signal transitions.
functions at V
page 18 and Table 3 on page 18 for capacitor
= 3.3V. See “Capacitor Selection” on
CC
recommendations for other operating conditions. The
charge pumps operate discontinuously (they turn off as
soon as the V+ and V- supplies are pumped up to the
nominal values), resulting in significant power savings.
Transmitters
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. Coupled with the on-chip ±5.5V supplies,
these transmitters deliver true RS-232 levels across a
wide range of single supply system voltages.
The ICL3221E, ICL3222E, ICL3223E, and ICL3241E
inverting receivers disable only when EN is driven high.
The ICL3243E receiver disables during forced (manual)
power-down, but not during automatic power-down (see
Table 2).
Except for the ICL3232E, all transmitter outputs disable
and assume a high impedance state when the device
FN4910 Rev 23.00
Sep 24, 2018
Page 14 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
The ICL3241E and ICL3243E monitor receivers remain
Low Power Operation
active even during manual power-down and forced
receiver disable, making them extremely useful for Ring
Indicator monitoring. Standard receivers driving
powered down peripherals must be disabled to prevent
current flow through the peripheral’s protection diodes
(see Figures 2 and 3). This renders them useless for
wake up functions, but the corresponding monitor
receiver can be dedicated to this task, as shown in
Figure 3.
These 3V devices require a nominal supply current of
0.3mA, even at V = 5.5V, during normal operation
CC
(not in power-down mode). This is considerably less than
the 5mA to 11mA current required by comparable 5V RS-
232 devices, allowing users to reduce system power
simply by switching to this family.
Pin-Compatible Replacements for 5V
Devices
V
CC
The ICL3221E, ICL3222E, ICL3232E are pin-compatible
with existing 5V RS-232 transceivers. See “Features” on
page 1 for more information.
R
R
XIN
XOUT
GND V
V
CC
-25V V
RIN
+25V
5kΩ
ROUT
The pin compatibility coupled with the low I
CC
and wide
GND
operating supply range make the ICL32xxE potential
lower power, higher performance drop-in replacements
for existing 5V applications. As long as the 5V RS-232
output swings are acceptable, and transmitter input
pull-up resistors are not required, the ICL32xxE works
in most 5V applications.
FIGURE 1. INVERTING RECEIVER CONNECTIONS
V
CC
V
CC
CURRENT
FLOW
V
CC
When replacing a device in an existing 5V application,
you can terminate C to V
Operating Circuits” on page 4. If possible, terminate C
as shown in the “Typical
3
CC
V
= V
CC
OUT
3
to GND for slightly better performance.
Rx
POWERED
DOWN
UART
Power-Down Functionality
(Except ICL3232E)
Tx
The already low current requirement drops significantly
when the device enters power-down mode. In power-
down, supply current drops to 1µA because the on-chip
OLD
RS-232 CHIP
SHDN = GND
GND
charge pump turns off (V+ collapses to V
and V-
CC
collapses to GND), and the transmitter outputs three-
state. Inverting receiver outputs may or may not
disable in power-down; refer to Table 2 for details. This
micro-power mode makes these devices ideal for battery
powered and portable applications.
FIGURE 2. POWER DRAIN THROUGH POWERED
DOWN PERIPHERAL
V
CC
Software Controlled (Manual) Power-Down
TRANSITION
DETECTOR
Most devices in the ICL32xxE family provide pins that
allow the user to force the IC into the low power, standby
state.
TO
ICL324XE
WAKE-UP
LOGIC
On the ICL3222E and ICL3241E, the power-down control
is a simple shutdown (SHDN) pin. Driving this pin high
enables normal operation, while driving it low forces the
V
CC
R2
OUTB
IC into its power-down state. Connect SHDN to V
if the
CC
R
T
V
= HI-Z
X
OUT
power-down function is not needed. Note that all the
receiver outputs remain enabled during shutdown (see
Table 2). For the lowest power consumption during
power-down, the receivers should also be disabled by
driving the EN input high (see “Receiver ENABLE Control
(ICL3221E, ICL3222E, ICL3223E, and ICL3241E Only)”
on page 18, and Figures 2 and 3).
R2
OUT
POWERED
DOWN
UART
R2
IN
T1
IN
X
T1
OUT
FORCEOFF = GND
OR SHDN = GND, EN = V
CC
The ICL3221E, ICL3223E, and ICL3243E use a two pin
approach in which the FORCEON and FORCEOFF inputs
determine the IC’s mode. For always enabled operation,
FORCEON and FORCEOFF are both strapped high. To
switch between active and power-down modes, under
logic or software control, only the FORCEOFF input needs
FIGURE 3. DISABLED RECEIVERS PREVENT POWER
DRAIN
FN4910 Rev 23.00
Sep 24, 2018
Page 15 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
to be driven. The FORCEON state is not critical, as
FORCEOFF overrides FORCEON. However, if strictly
manual control over power-down is desired, the user
must strap FORCEON high to disable the automatic
power-down circuitry. The ICL3243E inverting (standard)
receiver outputs also disable when the device is in
manual power-down, eliminating the possible current
path through a shutdown peripheral’s input protection
diode (see Figures 2 and 3).
TABLE 2. POWER-DOWN AND ENABLE LOGIC TRUTH TABLE
RS-232
SIGNAL
PRESENT AT FORCEOFF
R
OUTB
TRANSMITTER RECEIVER OUTPUTS INVALID
RECEIVER
INPUT?
OR SHDN FORCEON
INPUT
EN
INPUT
MODE OF
OPERATION
INPUT
OUTPUTS
OUTPUTS (Note 7) OUTPUT
ICL3222E, ICL3241E
N/A
N/A
L
L
N/A
N/A
L
High-Z
High-Z
Active
Active
Active
N/A
N/A
Manual Power-Down
H
High-Z
Manual Power-Down
with Receiver Disabled
N/A
N/A
H
H
N/A
N/A
L
Active
Active
Active
Active
Active
N/A
N/A
Normal Operation
H
High-Z
Normal Operation with
Receiver Disabled
ICL3221E, ICL3223E
No
No
H
H
H
H
L
Active
Active
Active
N/A
N/A
L
L
Normal Operation
(Auto Power-Down
Disabled)
H
High-Z
Yes
Yes
H
H
L
L
L
Active
Active
Active
N/A
N/A
H
H
Normal Operation
(Auto Power-Down
Enabled)
H
High-Z
No
No
H
H
L
L
L
High-Z
High-Z
Active
N/A
N/A
L
L
Power-Down Due to
Auto
Power-Down Logic
H
High-Z
Yes
Yes
L
L
X
X
L
High-Z
High-Z
Active
N/A
N/A
H
H
Manual Power-Down
H
High-Z
Manual Power-Down
with Receiver Disabled
No
No
L
L
X
X
L
High-Z
High-Z
Active
N/A
N/A
L
L
Manual Power-Down
H
High-Z
Manual Power-Down
with Receiver Disabled
ICL3243E
No
H
H
H
H
L
N/A
N/A
N/A
Active
Active
High-Z
Active
Active
Active
Active
Active
Active
L
H
L
Normal Operation
(Auto Power-Down
Disabled)
Yes
No
Normal Operation
(Auto Power-Down
Enabled)
L
Power-Down Due to
Auto
Power-Down Logic
Yes
No
L
L
X
X
N/A
N/A
High-Z
High-Z
High-Z
High-Z
Active
Active
H
L
Manual Power-Down
Manual Power-Down
NOTE:
7. Applies only to the ICL3241E and ICL3243E.
The INVALID output always indicates whether a valid RS-
232 signal is present at any of the receiver inputs (see
Table 2), providing an easy way to determine when the
interface block should power down. If an interface cable
is disconnected and all the receiver inputs are floating
(but pulled to GND by the internal receiver pull down
resistors), the INVALID logic detects the invalid levels
and drives the output low. The power management logic
then uses this indicator to power down the interface
block. Reconnecting the cable restores valid levels at the
receiver inputs, INVALID switches high, and the power
management logic wakes up the interface block. INVALID
can also indicate the DTR or RING INDICATOR signal, as
long as the other receiver inputs are floating or driven to
FN4910 Rev 23.00
Sep 24, 2018
Page 16 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
GND (as in the case of a powered down driver).
Automatic Power-Down
(ICL3221E, ICL3223E, and ICL3243E Only)
Connecting FORCEOFF and FORCEON together disables
the automatic power-down feature, enabling them to
function as a manual SHUTDOWN input (see Figure 4).
Even greater power savings are available by using the
devices that feature an automatic power-down function.
When no valid RS-232 voltages are sensed on any
receiver input for 30µs (see Figure 6), the charge pump
and transmitters power down, reducing supply current to
1µA. Invalid receiver levels occur whenever the driving
peripheral’s outputs are shut off (powered down) or
when the RS-232 interface cable is disconnected. The
ICL32xxE powers back up whenever it detects a valid
RS-232 voltage level on any receiver input. This
automatic power-down feature provides additional
system power savings without changes to the existing
operating system.
FORCEOFF
PWR
FORCEON
MGT
LOGIC
INVALID
ICL3221E,
ICL3223E,
ICL3243E
I/O
UART
CPU
VALID RS-232 LEVEL - ICL32xxE IS ACTIVE
2.7V
INDETERMINATE - POWER-DOWN MAY OR
MAY NOT OCCUR
0.3V
FIGURE 4. CONNECTIONS FOR MANUAL
POWER-DOWN WHEN NO VALID
RECEIVER SIGNALS ARE PRESENT
INVALID LEVEL - POWER-DOWN OCCURS AFTER 30µs
-0.3V
INDETERMINATE - POWER-DOWN MAY OR
MAY NOT OCCUR
With any of the control schemes, the time required to
exit power-down and resume transmission is 100µs. A
mouse or other application may need more time to wake
up from shutdown. If automatic power-down is used, the
RS-232 device reenters power-down if valid receiver
levels are not reestablished within 30µs of the ICL32xxE
powering up. Figure 5 illustrates a circuit that keeps the
ICL32xxE from initiating automatic power-down for
100ms after powering up. This gives the slow-to-wake
peripheral circuit time to reestablish valid RS-232 output
levels.
-2.7V
VALID RS-232 LEVEL - ICL32xxE IS ACTIVE
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER
LEVELS
Automatic power-down operates when the FORCEON
input is low and the FORCEOFF input is high. Tying
FORCEON high disables automatic power-down, but
manual power-down is always available with the
overriding FORCEOFF input. Table 2 on page 16
summarizes the automatic power-down functionality.
MASTER POWER-DOWN LINE
0.1µF
POWER
MANAGEMENT
UNIT
1MΩ
FORCEOFF
FORCEON
ICL3221E, ICL3223E, ICL3243E
FIGURE 5. CIRCUIT TO PREVENT AUTO
POWER-DOWN FOR 100ms AFTER
FORCED POWER-UP
FN4910 Rev 23.00
Sep 24, 2018
Page 17 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Devices with the automatic power-down feature include
an INVALID output signal, which switches low to indicate
that invalid levels have persisted on all of the receiver
inputs for more than 30µs (see Figure 7). INVALID
switches high 1µs after detecting a valid RS-232 level on
a receiver input. INVALID operates in all modes (forced
or automatic power-down, or forced on), so it is also
useful for systems employing manual power-down
circuitry. When automatic power-down is utilized,
INVALID = 0 indicates that the ICL32xxE is in
power-down mode.
Resistance (ESR) usually rises at low temperatures and it
influences the amount of ripple on V+ and V-.
TABLE 3. REQUIRED CAPACITOR VALUES
V
(V)
C
(µF)
C , C , C
CC
1
2
3
4
(µF)
3.0 to 3.6
4.5 to 5.5
3.0 to 5.5
0.1
0.1
0.047
0.1
0.33
0.47
The time to recover from automatic power-down mode is
typically 100µs.
Power Supply Decoupling
In most circumstances, a 0.1µF bypass capacitor is
adequate. In applications that are particularly sensitive
RECEIVER
INPUTS
INVALID
REGION
to power supply noise, decouple V
to ground with a
capacitor of the same value as the charge-pump
CC
}
capacitor C . Connect the bypass capacitor as close as
1
possible to the IC.
TRANSMITTER
OUTPUTS
Operation Down to 2.7V
V
CC
0
INVALID
OUTPUT
t
t
The ICL32xxE transmitter outputs meet RS-562 levels
INVL
INVH
(±3.7V) at full data rate, with V
RS-562 levels typically ensure interoperability with
as low as 2.7V.
CC
PWR UP
AUTOPWDN
V+
RS-232 devices.
V
CC
0
Transmitter Outputs when
Exiting Power-Down
Figure 8 shows the response of two transmitter outputs
when exiting power-down mode. As they activate, the
two transmitter outputs properly go to opposite RS-232
levels, with no glitching, ringing, or undesirable
transients. Each transmitter is loaded with 3kΩin parallel
with 2500pF. Note that the transmitters enable only
when the magnitude of the supplies exceeds
approximately 3V.
V-
FIGURE 7. AUTOMATIC POWER-DOWN AND
INVALID TIMING DIAGRAMS
Receiver ENABLE Control (ICL3221E,
ICL3222E, ICL3223E, and ICL3241E Only)
The ICL3221E, ICL3222E, ICL3223E, and ICL3241E also
feature an EN input to control the receiver outputs.
Driving EN high disables all the inverting (standard)
receiver outputs, placing them in a high impedance
state. This is useful for eliminating supply current, due to
a receiver output forward biasing the protection diode,
5V/DIV
FORCEOFF
T1
when driving the input of a powered down (V
peripheral (see Figure 2 on page 15). The enable input
= GND)
CC
has no effect on transmitter or monitor (R
) outputs.
2V/DIV
OUTB
Capacitor Selection
The charge pumps require 0.1µF capacitors for 3.3V
operation. For other supply voltages, refer to Table 3 for
capacitor values. Do not use values smaller than those
listed in Table 3. Increasing the capacitor values (by a
factor of 2) reduces ripple on the transmitter outputs and
T2
V
C
= +3.3V
CC
- C = 0.1µF
1
4
TIME (20µs/DIV)
slightly reduces power consumption. C , C , and C can
2
3
4
FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING
POWER-DOWN
be increased without increasing C ’s value; however, do
1
not increase C without also increasing C , C , and C to
1
2
3
4
maintain the proper ratios (C to the other capacitors).
1
Mouse Driveability
When using minimum required capacitor values, make
sure that capacitor values do not degrade excessively
with temperature. If in doubt, use capacitors with a
larger nominal value. The capacitor’s Equivalent Series
The ICL3241E and ICL3243E have been specifically
designed to power a serial mouse while operating from
low voltage supplies. Figure 9 on page 19 shows the
transmitter output voltages under increasing load
FN4910 Rev 23.00
Sep 24, 2018
Page 18 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
current. The on-chip switching regulator ensures the
transmitters supply at least 5V during worst case
5V/DIV
conditions (15mA for paralleled V+ transmitters, 7.3mA
for a single V- transmitter). The Automatic Power-Down
feature does not work with a mouse, so FORCEOFF and
T1
IN
FORCEON should be connected to V
.
CC
6
5
4
3
T1
OUT
OUT
V
+
OUT
V
= 3.0V
CC
2
1
R1
T1
V
C
= +3.3V
CC
0
V
+
- C = 0.1µF
OUT
1
4
-1
-2
-3
-4
-5
-6
T2
T3
5µs/DIV
ICL3241E, ICL3243E
FIGURE 11. LOOPBACK TEST AT 120kbps
V
V
-
CC
1
OUT
V
-
OUT
5V/DIV
T1
0
2
3
4
5
6
7
8
9
10
LOAD CURRENT PER TRANSMITTER (mA)
IN
FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CURRENT (PER TRANSMITTER, DOUBLE
CURRENT AXIS FOR TOTAL V
CURRENT)
OUT+
T1
OUT
OUT
High Data Rates
The ICL32xxE devices maintain the RS-232 5V
minimum transmitter output voltages even at high data
rates. Figure 10 details a transmitter loopback test
circuit, and Figure 11 illustrates the loopback test result
at 120kbps. For this test, all transmitters were
simultaneously driving RS-232 loads in parallel with
1000pF at 120kbps. Figure 12 shows the loopback
results for a single transmitter driving 1000pF and an
RS-232 load at 250kbps. The static transmitters were
also loaded with an RS-232 receiver.
R1
V
C
= +3.3V
CC
- C = 0.1µF
1
4
2µs/DIV
FIGURE 12. LOOPBACK TEST AT 250kbps
Interconnection with 3V and 5V
Logic
V
CC
+
0.1µF
The ICL32XX devices directly interface with 5V CMOS
and TTL logic families. The AC, HC, and CD4000 outputs
can drive ICL32XX inputs with the ICL32XX at 3.3V and
the logic supply at 5V, but ICL32XX outputs do not reach
V
CC
V+
V-
+
C1+
C1-
C2+
C2-
+
C
1
2
the minimum V for these logic families. See Table 4.
C
IH
3
4
ICL32xxE
TABLE 4. LOGIC FAMILY COMPATIBILITY WITH
VARIOUS SUPPLY VOLTAGES
+
C
C
+
SYSTEM
V
CC
POWER-SUPPLY SUPPLY
T
T
VOLTAGE
(V)
VOLTAGE
(V)
IN
OUT
COMPATIBILITY
1000pF
R
IN
R
OUT
3.3
3.3
Compatible with all CMOS
families
EN
5K
5
5
Compatible with all TTL and
CMOS logic families
SHDN OR
V
CC
FORCEOFF
5
3.3
Compatible with ACT and HCT
CMOS, and with TTL. ICL32XX
outputs are incompatible with
AC, HC, and CD4000 CMOS
inputs
FIGURE 10. TRANSMITTER LOOPBACK TEST CIRCUIT
FN4910 Rev 23.00
Sep 24, 2018
Page 19 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
IEC61000-4-2 Testing
The IEC61000 test method applies to finished
±15kV ESD Protection
All pins on ICL32XX devices include ESD protection
structures, but the ICL32xxE family incorporates
advanced structures that allow the RS-232 pins
(transmitter outputs and receiver inputs) to survive ESD
events up to ±15kV. The RS-232 pins are particularly
vulnerable to ESD damage because they typically
connect to an exposed port on the exterior of the finished
product. Simply touching the port pins, or connecting a
cable, can cause an ESD event that might destroy
unprotected ICs. The ESD structures protect the device
whether or not it is powered up, protect without allowing
any latch-up mechanism to activate, and do not interfere
with RS-232 signals as large as ±25V.
equipment, rather than to an individual IC. Therefore,
the pins most likely to suffer an ESD event are those that
are exposed to the outside world (the RS-232 pins in this
case), and the IC is tested in its typical application
configuration (power applied) rather than testing each
pin-to-pin combination. The lower current limiting
resistor coupled with the larger charge storage capacitor
yields a test that is much more severe than the HBM test.
The extra ESD protection built into this device’s RS-232
pins allows the design of equipment meeting level 4
criteria without the need for additional board level
protection on the RS-232 port.
AIR-GAP DISCHARGE TEST METHOD
Human Body Model (HBM) Testing
For this test method, a charged probe tip moves toward
the IC pin until the voltage arcs to it. The current
waveform delivered to the IC pin depends on approach
speed, humidity, temperature, etc., so it is difficult to
obtain repeatable results. The “E” device RS-232 pins
withstand ±15kV air-gap discharges.
This test method emulates the ESD event delivered to an
IC during human handling. The tester delivers the charge
through a 1.5kΩ current limiting resistor, making the test
less severe than the IEC61000 test which utilizes a
330Ω limiting resistor. The HBM method determines an
IC’s ability to withstand the ESD transients typically
present during handling and manufacturing. Due to the
random nature of these events, each pin is tested with
respect to all other pins. The RS-232 pins on “E” family
devices can withstand HBM ESD events to ±15kV.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and
predictable test, but equipment limits prevent testing
devices at voltages higher than ±8kV. All “E” family
devices survive ±8kV contact discharges on the RS-232
pins.
FN4910 Rev 23.00
Sep 24, 2018
Page 20 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Performance Curves
V
= 3.3V, T = +25°C.
A
CC
25
20
6
V
+
OUT
4
2
1 TRANSMITTER AT 250kbps
1 OR 2 TRANSMITTERS AT 30kbps
15
10
0
-SLEW
-2
-4
+SLEW
V
-
OUT
5
0
-6
0
1000
2000
3000
4000
5000
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
FIGURE 14. SLEW RATE vs LOAD CAPACITANCE
FIGURE 13. TRANSMITTER OUTPUT VOLTAGE vs
LOAD CAPACITANCE
45
45
ICL3222E, ICL3223E, ICL3232E
40
ICL3221E
40
250kbps
35
35
250kbps
30
25
30
25
120kbps
20
15
10
5
120kbps
20kbps
20
15
20kbps
10
5
0
0
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
FIGURE 16. SUPPLY CURRENT vs LOAD
FIGURE 15. SUPPLY CURRENT vs LOAD
CAPACITANCE WHEN TRANSMITTING
DATA
CAPACITANCE WHEN TRANSMITTING
DATA
45
40
35
30
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
ICL324XE
NO LOAD
ALL OUTPUTS STATIC
250kbps
ICL3221E, ICL3222E, ICL3223E, ICL3232E
120kbps
25
20
20kbps
4000
15
10
ICL324XE
ICL324XE
2.5 3.0
5000
2000
3000
1000
0
3.5
4.0
4.5
5.0
5.5
6.0
LOAD CAPACITANCE (pF)
SUPPLY VOLTAGE (V)
FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 17. SUPPLY CURRENT vs LOAD
CAPACITANCE WHEN TRANSMITTING
DATA
FN4910 Rev 23.00
Sep 24, 2018
Page 21 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ICL3221E: 286
ICL3222E: 338
ICL3223E: 357
ICL3232E: 296
ICL324XE: 464
PROCESS:
Si Gate CMOS
FN4910 Rev 23.00
Sep 24, 2018
Page 22 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure
you have the latest Rev.
DATE
REVISION
CHANGE
9/24/18 FN4910.23 -Updated on-chip voltage converter V
conditions from 2.7V to 3.3V on page 1
CC
-Added product information page links to Related Literature section on page 1
-Updated Ordering Information table on page 8:
-Added Tape and Reel (Units) column
-Removed the following retired parts:
-ICL3221ECA, ICL3221ECA-T
-ICL3221ECAZA, ICL3221ECAZA-T
-ICL3221ECV, ICL3221ECV-T
-ICL3221EIA, ICL3221EIA-T
-ICL3221ECA, ICL3221ECA-T
-ICL3222ECV, ICL3222ECV-T
-ICL3222EIAZ, ICL3222EIAZ-T
-ICL3222EIB, ICL3222EIB-T
-ICL3223ECA, ICL3223ECA-T
-ICL3223ECV, ICL3223ECV-T
-ICL3223EIAZ, ICL3223EIAZ-T
-Added retirement notifications and replacement recommendations for the following parts:
-ICL3232ECV-20Z
-ICL3232ECV-20Z-T
-ICL3232EFV-16Z
-ICL3232EFV-16Z
-Updated R from ±25V to ±28V in the Absolute Maximum Ratings on page 12
IN
-Updated Package Outline Drawing M16.15 from Rev. 1 to Rev. 2 on page 25
-Updated graphics to new standard layout and removed the dimensions table
-Removed About Intersil section
-Added Renesas disclaimer
12/9/15 FN4910.22 -Updated Ordering Information table starting on page 8
-Updated “Products” section to “About Intersil”
-POD E18.3 updated from rev 2 to rev 3. Changes since rev 2:
1) Removed the dimension chart and replaced with new standard format values for each dimension letter.
2) Updated D dimension (in side view; length of package) from 0.845(min) : 0.880(max) to
0.880(33.27)(min) : 0.920(34.65)(max)
3) Change JEDEC reference from MS-001-BC issue D to MS-001-AC issue D
-POD M16.173 updated from rev 1 to rev 2. Changes since rev 1: Converted to new POD format by
moving dimensions from table onto drawing and adding land pattern. No dimension changes.
-POD M20.173 updated from rev 1 to rev 2. Changes since rev 1: Converted to new POD format by
moving dimensions from table onto drawing and adding land pattern. No dimension changes.
-POD M28.173 udpated from rev 0 to rev 1. Changes since rev 1: Converted to new POD format by
moving dimensions from table onto drawing and adding land pattern. No dimension changes.
-POD M28.3 updated from rev 0 to rev 1. Changes since rev 1: Added land pattern
2/22/10 FN4910.21 Revision history begins with this revision.
-Converted to new Intersil template.
-Added new temp grade (F = extended industrial) to ICL3232. Updated ordering info table, Operating
Conditions, and added 125°C specs for input lkg currents, and rcvr output high voltage.
-Pages 8-10: Removed all withdrawn devices from Ordering Information table.
-Pages 12-14: Added "Boldface limits apply over the operating temperature range." to common
conditions of Electrical Specs table. Replaced Note 6 "Parts are 100% tested at +25°C. Full temp limits
are guaranteed by bench and tester characterization." with "Parameters with MIN and/or MAX limits
are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested."
FN4910 Rev 23.00
Sep 24, 2018
Page 23 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
For the most recent package outline drawing, see E18.3.
Package Outline Drawings
E18.3
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE
Rev. 3, 11/11
18
0.280 (7.11)
5
0.240 (6.10)
INDEX
1
2
3
AREA
6
0.325 (8.25)
TOP VIEW
0.300 (7.62)
C
L
6
5
0.300 (7.62) BSC
0.920 (34.65)
0.880 (33.27)
0.014 (0.355)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
0.430 (10.92) MAX
0.210 (5.33) MAX
4
-C-
7
SEATING
PLANE
0.150 (3.81)
0.115 (2.93)
4
5
2X 0.005 (0.13) MIN
0.015 (0.39) MIN
4
0.070 (1.77)
0.045 (1.15)
8
0.100 (2.54) BSC
0.022 (0.558)
0.014 (0.356)
SIDE VIEW
NOTES:
1. Controlling Dimensions: INCH (Metric dimensions in parentheses).
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions are measured with the package seated in JEDEC seating
plane gauge GS-3.
5. Dimensions do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.010 inch (0.25mm).
6. Dimensions are measured with the leads constrained to be perpendicular
to datum
.
-C-
7. Dimension measured at the lead tips with the leads unconstrained.
8. Maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. Package outline compliant to JEDEC MS-001-AC ISSUE D.
FN4910 Rev 23.00
Sep 24, 2018
Page 24 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
For the most recent package outline drawing, see M16.15.
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 2, 11/17
FN4910 Rev 23.00
Sep 24, 2018
Page 25 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
For the most recent package outline drawing, see M16.173.
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
5.00 ±0.10
SEE DETAIL "X"
9
16
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
8
B
0.09-0.20
0.65
TOP VIEW
END VIEW
1.00 REF
-
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25 +0.05/-0.06
0.25
5
0.10
C B A
M
0.10 C
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
(5.65)
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
(0.65 TYP)
(0.35 TYP)
6. Dimension in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
7. Conforms to JEDEC MO-153.
FN4910 Rev 23.00
Sep 24, 2018
Page 26 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
For the most recent package outline drawing, see M16.209.
Small Outline Plastic Packages (SSOP)
M16.209 (JEDEC MO-150-AC ISSUE B)
N
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
GAUGE
PLANE
SYMBOL
MIN
MAX
0.078
-
MIN
-
MAX
2.00
-
NOTES
-B-
A
A1
A2
B
-
-
0.002
0.065
0.009
0.004
0.233
0.197
0.05
1.65
0.22
0.09
5.90
5.00
-
1
2
3
0.072
0.014
0.009
0.255
0.220
1.85
0.38
0.25
6.50
5.60
-
L
0.25
0.010
SEATING PLANE
A
9
-A-
C
-
D
D
3
-C-
E
4
e
0.026 BSC
0.65 BSC
-
A2
e
A1
C
0.292
0.022
0.322
0.037
7.40
0.55
8.20
0.95
-
H
L
B
0.10(0.004)
6
0.25(0.010) M
C
A M B S
N
16
16
7
0°
8°
0°
8°
-
NOTES:
Rev. 3 6/05
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimen-
sion at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN4910 Rev 23.00
Sep 24, 2018
Page 27 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
For the most recent package outline drawing, see M16.3.
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
L
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
10.10
7.40
MAX
2.65
NOTES
-B-
A
A1
B
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
0.4133
0.2992
-
0.30
-
1
2
3
0.51
9
SEATING PLANE
A
C
D
E
0.0091
0.3977
0.2914
0.32
-
-A-
10.50
7.60
3
h x 45°
D
4
-C-
e
0.050 BSC
1.27 BSC
-
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
H
e
A1
C
5
h
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
16
16
7
0°
8°
0°
8°
-
NOTES:
Rev. 1 6/05
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN4910 Rev 23.00
Sep 24, 2018
Page 28 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
For the most recent package outline drawing, see M18.3.
Small Outline Plastic Packages (SOIC)
M18.3 (JEDEC MS-013-AB ISSUE C)
N
18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
L
B M
H
INCHES
MIN
MILLIMETERS
E
SYMBOL
MAX
0.1043
0.0118
0.0200
0.0125
0.4625
0.2992
MIN
2.35
0.10
0.33
0.23
11.35
7.40
MAX
2.65
NOTES
-B-
A
A1
B
0.0926
0.0040
0.013
-
0.30
-
1
2
3
0.51
9
SEATING PLANE
A
C
D
E
0.0091
0.4469
0.2914
0.32
-
-A-
11.75
7.60
3
h x 45°
D
4
-C-
e
0.050 BSC
1.27 BSC
-
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
H
e
A1
C
5
h
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
18
18
7
0°
8°
0°
8°
-
NOTES:
Rev. 1 6/05
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Thelead width“B”, as measured 0.36mm (0.014inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN4910 Rev 23.00
Sep 24, 2018
Page 29 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
For the most recent package outline drawing, see M20.173.
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
6.50 ±0.10
SEE DETAIL "X"
10
20
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
9
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
H
-
0.05
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25
0.25 +0.05/-0.06
5
0.10
C B A
M
0.10 C
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
(5.65)
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
(0.65 TYP)
(0.35 TYP)
6. Dimension in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
7. Conforms to JEDEC MO-153.
FN4910 Rev 23.00
Sep 24, 2018
Page 30 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
For the most recent package outline drawing, see M20.209.
Shrink Small Outline Plastic Packages (SSOP)
N
M20.209 (JEDEC MO-150-AE ISSUE B)
INDEX
AREA
M
M
B
0.25(0.010)
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
H
E
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
-B-
SYMBOL
MAX
0.078
0.008’
0.070’
0.015
0.008
0.289
0.212
MIN
1.73
0.05
1.68
0.25
0.09
7.07
5.20’
MAX
1.99
0.21
1.78
0.38
0.20’
7.33
5.38
NOTES
A
A1
A2
B
0.068
0.002
0.066
0.010’
0.004
0.278
0.205
1
2
3
L
0.25
0.010
SEATING PLANE
A
9
-A-
D
C
D
3
4
-C-
E
A2
e
A1
e
0.026 BSC
0.65 BSC
C
B
0.10(0.004)
0.301
0.025
0.311
0.037
7.65
0.63
7.90’
0.95
H
L
M
M
S
B
0.25(0.010)
C
A
6
7
N
20
20
0 deg.
8 deg.
0 deg.
8 deg.
NOTES:
Rev. 3 11/02
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
FN4910 Rev 23.00
Sep 24, 2018
Page 31 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
For the most recent package outline drawing, see M28.173.
M28.173
28 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 1, 5/10
A
1
3
9.70± 0.10
SEE DETAIL "X"
15
28
6.40
PIN #1
I.D. MARK
4.40 ± 0.10
2
3
0.20 C B A
1
14
+0.05
0.15
-0.06
B
0.65
TOP VIEW
END VIEW
1.00 REF
H
-
0.05
+0.15
0.90
C
-0.10
GAUGE
PLANE
1.20 MAX
0.25
SEATING PLANE
0.10 C
+0.05
-0.06
0.25
0.10
0°-8°
5
0.05 MIN
0.15 MAX
0.60 ±0.15
C B A
M
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
(5.65)
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
(0.65 TYP)
TYPICAL RECOMMENDED LAND PATTERN
(0.35 TYP)
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153.
FN4910 Rev 23.00
Sep 24, 2018
Page 32 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
For the most recent package outline drawing, see M28.209.
Shrink Small Outline Plastic Packages (SSOP)
M28.209 (JEDEC MO-150-AH ISSUE B)
N
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
GAUGE
PLANE
SYMBOL
MIN
MAX
0.078
-
MIN
-
MAX
2.00
-
NOTES
-B-
A
A1
A2
B
-
-
0.002
0.065
0.009
0.004
0.390
0.197
0.05
1.65
0.22
0.09
9.90
5.00
-
1
2
3
0.072
0.014
0.009
0.413
0.220
1.85
0.38
0.25
10.50
5.60
-
L
0.25
0.010
SEATING PLANE
A
9
-A-
C
-
D
D
3
-C-
E
4
e
0.026 BSC
0.65 BSC
-
A2
e
A1
C
0.292
0.022
0.322
0.037
7.40
0.55
8.20
0.95
-
H
L
B
0.10(0.004)
6
0.25(0.010) M
C
A M B S
N
28
28
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
Rev. 2 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
“B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN4910 Rev 23.00
Sep 24, 2018
Page 33 of 35
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
For the most recent package outline drawing, see M28.3.
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
L
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
NOTES
-B-
A
A1
B
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
0.30
-
1
2
3
0.51
9
SEATING PLANE
A
C
D
E
0.0091
0.6969
0.2914
0.32
-
0.7125 17.70
18.10
7.60
3
-A-
h x 45o
D
0.2992
7.40
4
e
0.05 BSC
1.27 BSC
-
-C-
a
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
H
e
A1
C
5
h
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C
A M B S
N
28
28
7
o
o
o
o
0
8
0
8
-
Rev. 1, 1/13
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
TYPICAL RECOMMENDED LAND PATTERN
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
(1.50mm)
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
(9.38mm)
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
(1.27mm TYP)
(0.51mm TYP)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN4910 Rev 23.00
Sep 24, 2018
Page 34 of 35
Notice
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Colophon 7.2
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