ISL12020MIRZ-T_技术文档

DATASHEET

ISL12020M

FN6667

Rev 6.00

January 9, 2015

Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature

Compensation and Auto Daylight Saving

The ISL12020M device is a low power Real Time Clock (RTC)

Features

with an embedded temperature sensor and crystal. Device

• Embedded 32.768kHz quartz crystal in the package

functions include oscillator compensation, clock/calendar,

power fail and low battery monitors, brownout indicator,

one-time, periodic or polled alarms, intelligent battery backup

switching, Battery Reseal™ function and 128 bytes of

battery-backed user SRAM. The device is offered in a

20 Ld DFN module that contains the RTC and an embedded

32.768kHz quartz crystal. The calibrated oscillator provides

less than ±5ppm drift across the 0°C to +85°C temperature

range.

• 20 Ld DFN package (for SOIC version, refer to the

ISL12022M)

• Calendar

• On-chip oscillator temperature compensation

• 10-bit digital temperature sensor output

• 15 selectable frequency outputs

• Interrupt for alarm or 15 selectable frequency outputs

• Automatic backup to battery or supercapacitor

The RTC tracks time with separate registers for hours, minutes

and seconds. The calendar registers track date, month, year

and day of the week and are accurate through 2099, with

automatic leap year correction.

• V and battery status monitors

DD

• Battery Reseal™ function to extend battery shelf life

• Power status brownout monitor

Daylight Savings time adjustment is done automatically, using

parameters entered by the user. Power fail and battery

monitors offer user-selectable trip levels. The time stamp

• Time stamp for battery switchover

function records the time and date of switchover from V to

• 128 Bytes battery-backed user SRAM

DD

V

power and also from V

BAT

to V power.

DD

2

BAT

• I C-Bus™

• RoHS compliant

Related Literature

• AN1549, “Addressing Power Issues in Real Time Clock

Applications”

Applications

• Utility meters

• AN1389, “Using Intersil’s High Accuracy Real Time Clock

Module”

• POS equipment

• Printers and copiers

• Digital cameras

1

2

3

4

5

6

7

8

9

X2

X1 20

X1 19

X2

X1 18

X2

X1 17

3.3V

C₁

X2

X1 16

SCHOTTKY DIODE

BAT54

NC

V_BAT

GND

NC

NC 15

R₂

R₃

R₁

0.1µF

V_DD14

IRQ/F_OUT13

SCL 12

SDA 11

10k 10k 10k

BATTERY

3.0V

C₂

0.1µF

VDD

SCL

MCU

INTERFACE

10 NC

SDA

GND

ISL12020M

IRQ/F_OUT

FIGURE 1. TYPICAL APPLICATION CIRCUIT

FN6667 Rev 6.00

January 9, 2015

Page 1 of 34

ISL12020M

Table of Contents

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DC Operating Characteristics - RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Power-Down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2

I C Interface Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SDA vs SCL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Symbol Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power Control Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Normal Mode (V ) to Battery-Backup Mode (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DD BAT

Battery-Backup Mode (V

) to Normal Mode (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

BAT DD

Power Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Brownout Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Battery Level Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Real Time Clock Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Single Event and Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Frequency Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

General Purpose User SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2

I C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Oscillator Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Real Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Addresses [00h to 06h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Control and Status Registers (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Addresses [07h to 0Fh]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Interrupt Control Register (INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Initial AT and DT setting Register (ITRO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ALPHA Register (ALPHA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

BETA Register (BETA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Final Analog Trimming Register (FATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Final Digital Trimming Register (FDTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

ALARM Registers (10h to 15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Time Stamp VDD to Battery Registers (TSV2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Time Stamp Battery to VDD Registers (TSB2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DST Control Registers (DSTCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

TEMP Registers (TEMP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

NPPM Registers (NPPM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

XT0 Registers (XT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

ALPHA Hot Register (ALPHAH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

User Registers (Accessed by Using Slave Address 1010111x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Addresses [00h to 7Fh]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2

I C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Protocol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Device Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Application Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Power Supply Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

FN6667 Rev 6.00

January 9, 2015

Page 2 of 34

ISL12020M

Battery-Backup Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Measuring Oscillator Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Temperature Compensation Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Daylight Savings Time (DST) Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

FN6667 Rev 6.00

January 9, 2015

Page 3 of 34

ISL12020M

Block Diagram

SDA

SECONDS

MINUTES

HOURS

BUFFER

2

I C

CONTROL

LOGIC

REGISTERS

INTERFACE

SCL

X1

BUFFER

DAY OF WEEK

DATE

CRYSTAL

OSCILLATOR

RTC

DIVIDER

X2

MONTH

V

DD

YEAR

POR

FREQUENCY

OUT

ALARM

CONTROL

REGISTERS

V

TRIP

+

-

USER

SRAM

SWITCH

INTERNAL

SUPPLY

V

BAT

IRQ/F

OUT

FREQUENCY

CONTROL

TEMPERATURE

SENSOR

GND

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

PART

V

RANGE

(V)

TEMP RANGE

(°C)

PACKAGE

(RoHS Compliant)

DD

MARKING

ISL 12020MIRZ

Evaluation Board

PKG DWG #

L20.5.5x4.0

ISL12020MIRZ

2.7 to 5.5

-40 to +85

20 Ld DFN

ISL12020MIRZ-EVALZ

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin

plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12020M. For more information on MSL please see techbrief TB363.

FN6667 Rev 6.00

January 9, 2015

Page 4 of 34

ISL12020M

Pin Configuration

ISL12020M

(20 LD DFN)

TOP VIEW

X2

1

2

3

4

5

6

7

8

9

20 X1

19 X1

18

X2

X1

X2

17 X1

16 X1

15 NC

X2

NC

BAT

V

14

13

DD

THERMAL

PAD

IRQ/F

GND

NC

OUT

12 SCL

11 SDA

NC 10

Pin Descriptions

PIN NUMBER

SYMBOL

DESCRIPTION

1, 2, 3, 4, 5, 16,

17, 18, 19, 20

X2

X1

Crystal Connection. The X1 and X2 pins are the input and output, respectively, of an inverting amplifier and are also

connected to the internal 32.768kHz quartz crystal, which is the timebase for the real time clock. Compensation

circuitry with an internal temperature sensor provides frequency correction to ±5ppm across the temperature range

from 0°C to +85°C. The X1 and X2 pins are not to be connected to any other circuitry or power voltages and are best

left floating. Do not connect in an application circuit, floating electrical connection.

6, 9, 10, 15

7

NC

No connection. Do not connect to a signal or supply voltage.

V

Backup Supply. This input provides a backup supply voltage to the device. The V supplies power to the device in the

BAT

event that the V supply fails. This pin can be connected to a battery, a Super Capacitor or tied to ground if not used.

DD

See the Battery Monitor parameter in the “Electrical Specifications” table “DC Operating Characteristics - RTC” on

page 6.

11

SDA

Serial Data. The SDA is a bidirectional pin used to transfer data into and out of the device. It has an open-drain output

and may be ORed with other open-drain or open collector outputs. The input buffer is always active (not gated) in normal

mode.

An open-drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal

2

with the use of a slope controlled pull-down. The circuit is designed for 400kHz I C interface speeds. It is disabled when

the backup power supply on the V

pin is activated. The SDA is a bidirectional pin used to transfer serial data into and

BAT

out of the device. It has an open-drain output and may be wire OR’ed with other open-drain or open collector outputs.

12

13

SCL

Serial Clock. The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always

active (not gated). It is disabled when the backup power supply on the V

consumption.

pin is activated to minimize power

BAT

IRQ/F

OUT

Interrupt Output/Frequency Output (Default 32.768kHz frequency output). This dual function pin can be used as an

interrupt or frequency output pin. The IRQ/F mode is selected via the frequency out control bits of the control/status

OUT

register. Multi-functional pin that can be used as interrupt or frequency output pin. The function is set via the

configuration register. The output is open drain and requires a pull-up resistor.

Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has

occurred and requests action. It is an open-drain active low output.

Frequency Output Mode. The pin outputs a clock signal, which is related to the crystal frequency. The frequency output

2

is user selectable and enabled via the I C bus. It is an open-drain output.

14

V

Power supply. Chip power supply and ground pins. The device will operate with a power supply from V = 2.7V to

DD

5.5VDC. A 0.1µF capacitor is recommended on the V pin to ground.

DD

8

GND

NC

Ground Pin

Thermal Pad

No Connection. Do not connect to a signal or supply voltage.

FN6667 Rev 6.00

January 9, 2015

Page 5 of 34

ISL12020M

Absolute Maximum Ratings

Thermal Information

Voltage on V , V

and IRQ/F

pins

Thermal Resistance (Typical)

20 Lead DFN (Notes 4, 5) . . . . . . . . . . . . . . 40

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Pb-Free Reflow Profile (Note 7). . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493



(°C/W)



(°C/W)

3.5

DD BAT

OUT

JA

JC

(Respect to Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Voltage on SCL and SDA pins

(Respect to Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V + 0.3V

DD

Voltage on X1 and X2 pins

(Respect to Ground, Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V

ESD Rating

Human Body Model (Tested per MIL-STD-883 Method 3014) . . . . >3kV

Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300V

Latch-up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA or 1.5 * V

Input

MAX

Shock Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . 5000g, 0.3ms, 1/2 sine

Vibration (Ultrasound cleaning not advised) . . . . . . . . . . . 20g/10-2000Hz,

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4.  is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

5. For  , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

6. The X1 and X2 pins are connected internally to a crystal and should be a floating electrical connection.

7. The ISL12020M Oscillator Initial Accuracy can change after solder reflow attachment. The amount of change will depend on the reflow temperature

and length of exposure. A general rule is to use only one reflow cycle and keep the temperature and time as short as possible. Changes on the order

of ±1ppm to ±3ppm can be expected with typical reflow profiles.

DC Operating Characteristics - RTC Test Conditions: V = +2.7 to +5.5V, T = -40°C to +85°C, unless otherwise stated. Boldface

DD

A

limits apply across the operating temperature range, -40°C to +85°C.

MIN

TYP

MAX

SYMBOL

PARAMETER

Main Power Supply

CONDITIONS

(Note 8)

(Note 9)

(Note 8)

UNITS

V

NOTES

V

(Note 10)

2.7

5.5

15

DD

V

Battery Supply Voltage

1.8

V

11

BAT

2

I

Supply Current. (I C not active,

V

= 5V

= 3V

4.1

3.5

µA

12, 13

DD1

DD

temperature conversion not active, F

not active)

OUT

14

2

I

Supply Current. (I C Active, Temperature

V

= 5V

200

120

500

400

µA

12, 13

DD2

DD

Conversion not Active, F

not Active)

OUT

2

Supply Current. (I C not Active,

Temperature Conversion Active, F

Active)

DD3

not

OUT

I

Battery Supply Current

V

= 0V, V = 3V, T = +25°C

BAT A

1.0

1.6

5.0

µA

12

BAT

DD

= 0V, V

= 3V

BAT

I

Battery Input Leakage

= 5.5V, V

= 1.8V

BAT

100

1.0

nA

BATLKG

I

Input Leakage Current on SCL

I/O Leakage Current on SDA

Battery Level Monitor Threshold

V

= 0V, V = V

-1.0

-100

2.0

±0.1

µA

LI

IL

IH

DD

I

V

= 0V, V = V

1.0

µA

LO

IH

V

+100

2.4

mV

V

BATM

V

Brownout Level Monitor Threshold

PBM

TRIP

V

Mode Threshold

(Note 10)

2.2

30

50

±2

BAT

V

Hysteresis

mV

ppm

15

TRIPHYS

TRIP

V

Hysteresis

BAT

BATHYS

Fout

Oscillator Initial Accuracy

V

= 3.3V, T = +25°C

7, 15

25°C

DD

A

FN6667 Rev 6.00

January 9, 2015

Page 6 of 34

ISL12020M

DC Operating Characteristics - RTC Test Conditions: V = +2.7 to +5.5V, T = -40°C to +85°C, unless otherwise stated. Boldface

DD

A

limits apply across the operating temperature range, -40°C to +85°C. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

CONDITIONS

(Note 8)

(Note 9)

(Note 8)

UNITS

ppm

°C

NOTES

7, 15

15

Fout

Oscillator Stability vs Temperature

V

= 3.3V, 0°C to +85°C

= 3.3V, -30°C to +85°C

= 3.3V, -40°C to +85°C

-5

+5

+10

+15

+3

T

DD

-10

-15

-3

Fout

Oscillator Stability vs Voltage

Temperature Sensor Accuracy

(OPEN-DRAIN OUTPUT)

2.7V  V  5.5V

DD

V

= V

= 3.3V

BAT

±2

15

DD

IRQ/F

OUT

V

Output Low Voltage

V

= 5V, I = 3mA

OL

0.4

V

OL

DD

= 2.7V, I = 1mA

OL

DD

Power-Down Timing Test Conditions: V = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated. Boldface limits apply

DD

across the operating temperature range, -40°C to +85°C.

MIN

TYP

MAX

SYMBOL

PARAMETER

CONDITIONS

(Note 8)

(Note 9)

(Note 8)

UNITS

V/ms

NOTES

14

V

Negative Slew Rate

10

DDSR-

DD

V

Positive Slew Rate, Minimum

.05

17

DDSR+

2

I C Interface Specifications Test Conditions: V = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.

DD

Boldface limits apply across the operating temperature range, -40°C to +85°C.

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 8)

(Note 9)

(Note 8)

UNITS

V

NOTES

V

SDA and SCL Input Buffer LOW

Voltage

-0.3

0.3 x V

DD

IL

V

SDA and SCL Input Buffer HIGH

Voltage

0.7 x V

V + 0.3

DD

V

IH

DD

Hysteresis

SDA and SCL Input Buffer

Hysteresis

0.05 x V

0.02

15, 16

DD

V

SDA Output Buffer LOW Voltage,

Sinking 3mA

V

= 5V, I = 3mA

DD OL

0

0.4

V

OL

C

SDA and SCL Pin Capacitance

T

= +25°C, f = 1MHz,

10

pF

A

V

= 5V, V = 0V,

IN

DD

= 0V

OUT

f

SCL Frequency

400

50

kHz

ns

SCL

t

Pulse Width Suppression Time at Any pulse narrower than the

IN

SDA and SCL Inputs

max spec is suppressed.

t

SCL Falling Edge to SDA Output

Data Valid

SCL falling edge crossing

30% of V , until SDA exits

DD

900

ns

AA

the 30% to 70% of V

DD

window.

t

Time the Bus Must be Free Before SDA crossing 70% of V

1300

ns

BUF

DD

during a STOP condition, to

SDA crossing 70% of V

the Start of a New Transmission

Clock LOW Time

DD

during the following START

condition.

t

Measured at the 30% of V

crossing.

ns

LOW

DD

FN6667 Rev 6.00

January 9, 2015

Page 7 of 34

ISL12020M

2

I C Interface Specifications Test Conditions: V = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.

DD

Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

Clock HIGH Time

TEST CONDITIONS

(Note 8)

(Note 9)

(Note 8)

UNITS

ns

NOTES

t

Measured at the 70% of V

crossing.

600

HIGH

DD

t

START Condition Setup Time

START Condition Hold Time

SCL rising edge to SDA

600

ns

SU:STA

falling edge. Both crossing

70% of V

.

DD

t

From SDA falling edge

crossing 30% of V to SCL

DD

falling edge crossing 70% of

600

100

20

HD:STA

V

.

DD

t

Input Data Setup Time

Input Data Hold Time

From SDA exiting the 30% to

70% of V window, to SCL

DD

rising edge crossing 30% of

ns

SU:DAT

HD:DAT

V

DD.

t

From SCL falling edge

crossing 30% of V to SDA

DD

entering the 30% to 70% of

900

V

window.

DD

t

STOP Condition Setup Time

From SCL rising edge

crossing 70% of V , to SDA

DD

rising edge crossing 30% of

600

SU:STO

HD:STO

V

.

DD

t

STOP Condition Hold Time

Output Data Hold Time

From SDA rising edge to SCL

falling edge. Both crossing

600

0

ns

70% of V

.

DD

t

From SCL falling edge

DH

crossing 30% of V , until

DD

SDA enters the 30% to 70%

of V window.

DD

t

SDA and SCL Rise Time

SDA and SCL Fall Time

From 30% to 70% of V

From 70% to 30% of V

20 + 0.1 x

Cb

300

400

ns

16

R

DD.

t

20 + 0.1 x

Cb

F

Cb

Capacitive Loading of SDA or SCL Total on-chip and off-chip

SDA and SCL Bus Pull-up Resistor Maximum is determined by

10

1

pF

16

R

kΩ

PU

Off-chip

t and t .

R F

For Cb = 400pF, max is

about 2kΩ~2.5kΩ.

For Cb = 40pF, max is about

15kΩ~20kΩ

NOTES:

8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

9. Specified at +25°C.

10. Minimum V and/or V

DD

of 1V to sustain the SRAM. The value is based on characterization and it is not tested.

BAT

11. Temperature Conversion is inactive below V

BAT

= 2.7V. Device operation is not guaranteed at VBAT<1.8V.

12. IRQ/F

OUT

Inactive.

13. V > V

DD

V

BAT + BATHYS

14. In order to ensure proper timekeeping, the V

specification must be followed.

DD SR-

15. Limits should be considered typical and are not production tested.

2

16. These are I C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate

specification.

17. To avoid EEPROM recall issues, it is advised to use this minimum power up slew rate. Not tested, shown as typical only.

FN6667 Rev 6.00

January 9, 2015

Page 8 of 34

ISL12020M

SDA vs SCL Timing

t

R

F

HIGH

LOW

SCL

t

SU:DAT

t

HD:DAT

t

SU:STA

SU:STO

t

HD:STA

SDA

(INPUT TIMING)

t

BUF

DH

t

AA

SDA

(OUTPUT TIMING)

Symbol Table

EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V

5.0V

= 5V

DD

WAVEFORM

INPUTS

OUTPUTS

Must be steady

Will be steady

FOR V = 0.4V

OL

1533Ω

100pF

AND I

= 3mA

OL

SDA

AND

Ma y change

from LO W

to HIGH

Will change

from LOW

to HIGH

IRQ/F

OUT

Ma y change

from HIGH

to LO W

Will change

from HIGH

to LOW

FIGURE 2. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE

WITH V = 5.0V

DD

Don’t Care:

Changing:

Changes Allowed

State Not Known

N/A

Center Line is

High Impedance

Typical Performance Curves Temperature is +25°C unless otherwise specified.

1050

1000

950

1600

1400

1200

1000

800

V

= 5.5V

BAT

900

V

= 3.0V

BAT

850

V

= 1.8V

60

BAT

800

1.8

600

-40

2.3

2.8

3.3

3.8

4.3

4.8

5.3

-20

0

20

40

80

V

VOLTAGE (V)

TEMPERATURE (°C)

BAT

FIGURE 4. I

vs TEMPERATURE

FIGURE 3. I

vs V

BAT

FN6667 Rev 6.00

January 9, 2015

Page 9 of 34

ISL12020M

Typical Performance Curves Temperature is +25°C unless otherwise specified. (Continued)

6

5

4

3

4.4

4.2

4.0

3.8

3.6

3.4

3.2

3.0

V

= 5.5V

BAT

V

= 2.7V

DD

V

= 3.3V

DD

2

-40

-20

0

20

40

60

80

2.7

3.2

3.7

4.2

(V)

4.7

5.2

V

TEMPERATURE (°C)

DD

FIGURE 5. I

DD1

vs TEMPERATURE

FIGURE 6. I

vs V

DD1

DD

6

5

4

3

V

= 5.5V

5

4

3

2

DD

2

1

V

= 5.5V

DD

0

V

= 2.7V

-1

-2

-3

-4

-5

DD

V

= 3.3V

DD

V

= 2.7V

DD

V

= 3.3V

DD

-40

-20

0

20

40

60

80

0.01

0.1

1

10

100

1k

10k

1M

TEMPERATURE (°C)

FREQUENCY OUTPUT (Hz)

FIGURE 8. F

OUT

vs I

DD

FIGURE 7. OSCILLATOR ERROR vs TEMPERATURE

5.5

110

100

90

80

70

60

50

40

30

20

5.0

4.5

4.0

3.5

3.0

2.5

F

= 32kHz

OUT

V

= 5.5V

= 3.0V

BAT

V

BAT

F

= 1Hz AND 64Hz

OUT

V

= 1.8V

20

BAT

-40

-20

0

20

40

60

80

-40

-20

0

40

60

80

TEMPERATURE (°C)

FIGURE 9. I vs TEMPERATURE, 3 DIFFERENT F

DD OUT

FIGURE 10. I

WITH TSE = 1, BTSE = 1 vs TEMPERATURE

BAT

FN6667 Rev 6.00

January 9, 2015

Page 10 of 34

ISL12020M

Typical Performance Curves Temperature is +25°C unless otherwise specified. (Continued)

110

100

90

80

62.5ppm

32ppm

60

40

V

= 5.5V

DD

V

= 3.3V

DD

20

80

0ppm

0

70

-20

-40

-60

-80

-31ppm

-61.5ppm

60

V

= 2.7V

0

BAT

50

40

-40

-20

20

40

60

80

-40

-20

0

20

40

60

80

TEMPERATURE (°C)

FIGURE 11. I with TSE = 1 vs TEMPERATURE

DD

FIGURE 12. OSCILLATOR CHANGE vs TEMPERATURE AT DIFFERENT

AGING SETTINGS (IATR) (BETA SET FOR 1ppm STEPS)

General Description

Functional Description

The ISL12020M device is a low power Real Time Clock (RTC) with

embedded temperature sensor and crystal. It contains crystal

frequency compensation circuitry over the temperature range of

0°C to 85°C good to ±5ppm accuracy. It also contains a

clock/calendar with Daylight Savings Time (DST) adjustment,

power fail and low battery monitors, brownout indicator, 1 periodic

or polled alarm, intelligent battery-backup switching and 128

Bytes of battery-backed user SRAM.

Power Control Operation

The power control circuit accepts a V and a V

types of batteries can be used with Intersil RTC products. For

example, 3.0V or 3.6V Lithium batteries are appropriate and

battery sizes are available that can power the ISL12020M for up

to 10 years. Another option is to use a Super Capacitor for

input. Many

DD BAT

applications where V is interrupted for up to a month. See the

DD

“Application Section” on page 28 for more information.

The oscillator uses an internal 32.768kHz crystal. The real time

clock tracks time with separate registers for hours, minutes and

seconds. The device has calendar registers for date, month, year

and day of the week. The calendar is accurate through 2099,

with automatic leap year correction. In addition, both the

ISL12020M could be programmed for automatic Daylight

Savings Time (DST) adjustment by entering local DST

information.

Normal Mode (V ) to Battery-Backup Mode

DD

(V

)

BAT

To transition from the V to V

mode, both of the following

DD

BAT

conditions must be met:

Condition 1:

V

< V

- V

BAT BATHYS

DD

The ISL12020M’s alarm can be set to any clock/calendar value

for a match. For example, every minute, every Tuesday or at

5:23 AM on March 21. The alarm status is available by checking

the Status Register, or the device can be configured to provide a

where V  50mV

BATHYS

Condition 2:

V

< V

DD

TRIP

hardware interrupt via the IRQ/F

pin. There is a repeat mode

where V

 2.2V

OUT

for the alarm allowing a periodic interrupt every minute, every

hour, every day, etc.

Battery-Backup Mode (V

) to Normal Mode

BAT

(V

)

DD

The device also offers a backup power input pin. This V

BAT

allows the device to be backed up by battery or Super Capacitor

The ISL12020M device will switch from the V

to V mode

DD

BAT

with automatic switchover from V to V . The ISL12020M

when one of the following conditions occurs:

DD BAT

device is specified for V = 2.7V to 5.5V and the clock/calendar

portion of the device remains fully operational in battery-backup

DD

Condition 1:

V

> V

+ V

BATHYS

mode down to 1.8V (Standby Mode). The V

level is monitored

DD

BAT

BATHYS

BAT

where V

50mV

and reported against preselected levels. The first report is

registered when the V level falls below 85% of nominal level,

BAT

Condition 2:

the second level is set for 75%. Battery levels are stored in

PWR_VBAT registers.

V

> V

+ V

TRIP TRIPHYS

DD

where V

 30mV

TRIPHYS

The ISL12020M offers a “Brownout” alarm once the V falls

DD

These power control situations are illustrated in Figures 13 and

14.

below a preselected trip level. This allows system Micro to save

vital information to memory before complete power loss. There

are six V levels that could be selected for initiation of the

DD

Brownout alarm.

FN6667 Rev 6.00

January 9, 2015

Page 11 of 34

ISL12020M

85% and 75%, the LBAT85 bit is set in the status register. When

the level drops below 75%, both LBAT85 and LBAT75 bits are set

in the status register.

BATTERY-BACKUP

MODE

V

DD

The battery level monitor is not functional in battery backup mode.

V

TRIP

2.2V

1.8V

In order to read the monitor bits after powering up V , instigate a

DD

battery level measurement, which is set by setting the TSE bit to "1"

(BETA register) and then read the bits.

V

BAT

V

+ V

BATHYS

BAT

V

- V

BATHYS

BAT

There is a Battery Time Stamp Function available. Once the V is

DD

low enough to enable switchover to the battery, the RTC time/date

are written into the TSV2B register. This information can be read

FIGURE 13. BATTERY SWITCHOVER WHEN V

< V

TRIP

BAT

from the TSV2B registers to discover the point in time of the V

power-down. If there are multiple power-down cycles before

DD

reading these registers, the first values stored in these registers

will be retained. These registers will hold the original power-down

value until they are cleared by setting CLRTS = 1 to clear the

registers.

BATTERY-BACKUP

MODE

V

DD

V

BAT

3.0V

2.2V

The normal power switching of the ISL12020M is designed to

V

TRIP

switch into battery-backup mode only if the V power is lost.

DD

This will ensure that the device can accept a wide range of

backup voltages from many types of sources while reliably

switching into backup mode.

V

+ V

TRIPHYS

TRIP

Note that the ISL12020M is not guaranteed to operate with

FIGURE 14. BATTERY SWITCHOVER WHEN V

> V

TRIP

BAT

V

< 1.8V. If the battery voltage is expected to drop lower than

BAT

this minimum, correct operation of the device, especially after a

power-down cycle, is not guaranteed.

2

The I C bus is deactivated in battery-backup mode to reduce

power consumption. Aside from this, all RTC functions are

operational during battery-backup mode. Except for SCL and SDA,

all the inputs and outputs of the ISL12020M are active during

battery-backup mode unless disabled via the control register.

V

DD

The minimum V

to insure SRAM is stable is 1.0V. Below that,

BAT

the SRAM may be corrupted when V power resumes.

DD

Real Time Clock Operation

The device Time Stamps the switchover from V to V

DD BAT

and

V

to V and the time is stored in t

and t registers

The Real Time Clock (RTC) uses an integrated 32.768kHz quartz

crystal to maintain an accurate internal representation of

second, minute, hour, day of week, date, month and year. The

RTC also has leap-year correction. The clock also corrects for

months having fewer than 31 days and has a bit that controls

24-hour or AM/PM format. When the ISL12020M powers up

BAT

DD SV2B

SB2V

respectively. If multiple V power-down sequences occur before

DD

status is read, the earliest V to V

DD BAT

power-down time is stored

and the most recent V

to V time is stored.

BAT

DD

Temperature conversion and compensation can be enabled in

battery-backup mode. Bit BTSE in the BETA register controls this

operation, as described in “BETA Register (BETA)” on page 20.

after the loss of both V and V , the clock will not begin

DD BAT

incrementing until at least one byte is written to the clock

register.

Power Failure Detection

The ISL12020M provides a Real Time Clock Failure Bit (RTCF) to

detect total power failure. It allows users to determine if the

device has powered up after having lost all power to the device

Single Event and Interrupt

The alarm mode is enabled via the MSB bit. Choosing single

event or interrupt alarm mode is selected via the IM bit. Note that

when the frequency output function is enabled, the alarm

function is disabled.

(both V and V ).

DD BAT

Brownout Detection

The standard alarm allows for alarms of time, date, day of the

week, month and year. When a time alarm occurs in single

The ISL12020M monitors the V level continuously and

provides warning if the V level drops below prescribed levels.

DD

There are six (6) levels that can be selected for the trip level.

DD

event mode, the IRQ/F

pin will be pulled low and the alarm

OUT

status bit (ALM) will be set to “1”.

These values are 85% below popular V levels. The LVDD bit in

DD

the Status Register will be set to “1” when brownout is detected.

Note that the I C serial bus remains active unless the Battery

The pulsed Interrupt mode allows for repetitive or recurring alarm

functionality. Hence, once the alarm is set, the device will

continue to alarm for each occurring match of the alarm and

present time. Thus, it will alarm as often as every minute (if only

the nth second is set) or as infrequently as once a year (if at least

the nth month is set). During pulsed Interrupt mode, the

2

V

levels are reached.

TRIP

Battery Level Monitor

The ISL12020M has a built in warning feature once the Back Up

battery level drops first to 85% and then to 75% of the battery’s

IRQ/F

pin will be pulled low for 250ms and the alarm status

bit (ALM) will be set to “1”.

OUT

nominal V

level. When the battery voltage drops to between

BAT

FN6667 Rev 6.00

January 9, 2015

Page 12 of 34

ISL12020M

The ALM bit can be reset by the user or cleared automatically

using the auto reset mode (see ARST bit). The alarm function can

be enabled/disabled during battery-backup mode using the

FOBATB bit. For more information on the alarm, please see

“ALARM Registers (10h to 15h)” on page 22.

Register Descriptions

The battery-backed registers are accessible following a slave

byte of “1101111x” and reads or writes to addresses [00h:2Fh].

The defined addresses and default values are described in

Table 1. The battery backed general purpose SRAM has a

different slave address (1010111x), so it is not possible to

read/write that section of memory while accessing the registers.

Frequency Output Mode

The ISL12020M has the option to provide a clock output signal

using the IRQ/F

open-drain output pin. The frequency output

OUT

REGISTER ACCESS

mode is set by using the FO bits to select 15 possible output

frequency values from 1/32Hz to 32kHz. The frequency output

can be enabled/disabled during battery-backup mode using the

FOBATB bit.

The contents of the registers can be modified by performing a byte

or a page write operation directly to any register address.

The registers are divided into 8 sections. They are:

General Purpose User SRAM

1. Real Time Clock (7 bytes): Address 00h to 06h.

2. Control and Status (9 bytes): Address 07h to 0Fh.

3. Alarm (6 bytes): Address 10h to 15h.

The ISL12020M provides 128 bytes of user SRAM. The SRAM will

continue to operate in battery-backup mode. However, it should

2

be noted that the I C bus is disabled in battery-backup mode.

4. Time Stamp for Battery Status (5 bytes): Address 16h to 1Ah.

2

5. Time Stamp for V Status (5 bytes): Address 1Bh to 1Fh.

DD

I C Serial Interface

2

6. Daylight Savings Time (8 bytes): 20h to 27h.

7. TEMP (2 bytes): 28h to 29h

The ISL12020M has an I C serial bus interface that provides

access to the control and status registers and the user SRAM.

The I C serial interface is compatible with other industry I C

serial bus protocols using a bidirectional data signal (SDA) and a

clock signal (SCL).

2

8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah, 2Bh

9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch

10. Crystal ALPHA at high temperature, ALPHA_H (1 byte): 2Dh

11. Scratch Pad (2 bytes): Address 2Eh and 2Fh

Oscillator Compensation

The ISL12020M provides both initial timing correction and

temperature correction due to variation of the crystal oscillator.

Analog and digital trimming control is provided for initial

adjustment and a temperature compensation function is provided

to automatically correct for temperature drift of the crystal. Initial

values for the initial AT and DT settings (ITR0), temperature

coefficient (ALPHA), crystal capacitance (BETA), as well as the

crystal turn-over temperature (XTO), are preset internally and

recalled to RAM registers on power-up. These values can be

overwritten by the user although this is not suggested as the

resulting temperature compensation performance will be

compromised. The compensation function can be

Write capability is allowable into the RTC registers (00h to 06h)

only when the WRTC bit (bit 6 of address 08h) is set to “1”. A

multi-byte read or write operation should be limited to one

section per operation for best RTC timekeeping performance.

A register can be read by performing a random read at any

address at any time. This returns the contents of that register

location. Additional registers are read by performing a sequential

read. For the RTC and Alarm registers, the read instruction

latches all clock registers into a buffer, so an update of the clock

does not change the time being read. At the end of a read, the

master supplies a stop condition to end the operation and free

the bus. After a read, the address remains at the previous

address +1 so the user can execute a current address read and

continue reading the next register. When the previous address is

2Fh, the next address will wrap around to 00h.

enabled/disabled at any time and can be used in battery mode as

well.

It is not necessary to set the WRTC bit prior to writing into the

control and status, alarm and user SRAM registers.

FN6667 Rev 6.00

January 9, 2015

Page 13 of 34

ISL12020M

TABLE 1. REGISTER MEMORY MAP (X INDICATES DEFAULT VARIES WITH EACH DEVICE. YELLOW SHADING INDICATES THOSE BITS SHOULD NOT BE

CHANGED BY THE USER)

BIT

REG

ADDR. SECTION

RTC

NAME

SC

7

6

SC22

MN22

0

5

SC21

MN21

HR21

DT21

0

4

SC20

MN20

HR20

DT20

MO20

YR20

0

3

2

1

0

RANGE DEFAULT

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

0

SC13

MN13

HR13

DT13

MO13

YR13

0

SC12

MN12

HR12

DT12

MO12

YR12

DW2

SC11

MN11

HR11

DT11

MO11

YR11

DW1

SC10

MN10

HR10

DT10

MO10

YR10

DW0

RTCF

FO0

0 to 59

0 to 23

1 to 31

1 to 12

0 to 99

0 to 6

N/A

00h

01h

00h

01h

00h

XXh

00h

MN

HR

MIL

0

DT

0

MO

0

YR

YR23

0

YR22

0

YR21

0

DW

CSR

SR

BUSY

ARST

CLRTS

OSCF

WRTC

D

DSTADJ

IM

ALM

LVDD

FO3

LBAT85

FO2

LBAT75

FO1

INT

FOBATB

D

N/A

PWR_VDD

PWR_VBAT

ITRO

ALPHA

BETA

FATR

FDTR

SCA0

MNA0

HRA0

DTA0

MOA0

DWA0

VSC

D

V

Trip2

V

Trip1

DD

V

Trip0

DD

N/A

DD

RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0

N/A

IDTR01

IDTR00

ALPHA6

BTSE

0

IATR05

ALPHA5

BTSR

IATR04

ALPHA4

BETA4

IATR03

ALPHA3

BETA3

IATR02

ALPHA2

BETA2

IATR01

ALPHA1

BETA1

IATR00

ALPHA0

BETA0

N/A

D

N/A

TSE

N/A

0

FFATR5

0

FATR4

FATR3

FATR2

FATR1

FATR0

N/A

0

FDTR4

SCA020

FDTR3

SCA013

FDTR2

SCA012

FDTR1

SCA011

FDTR0

SCA010

N/A

ALARM

ESCA0

SCA022

SCA021

00 to 59

EMNA0

MNA022 MNA021 MNA020 MNA013 MNA012 MNA011 MNA010 00 to 59

EHRA0

D

HRA021 HRA020 HRA013 HRA012 HRA011 HRA010

0 to 23

EDTA0

D

DTA021

D

DTA020

DTA013

DTA012

DTA011

DTA010

01 to 31

EMOA00

D

MOA020 MOA013 MOA012 MOA011 MOA010 01 to 12

EDWA0

D

DWA02

VSC12

VMN12

VHR12

VDT12

VMO12

BSC12

BMN12

BHR12

BDT12

BMO12

DWA01

VSC11

VMN11

VHR11

VDT11

VMO11

BSC11

BMN11

BHR11

BDT11

BMO11

DWA00

VSC10

VMN10

VHR10

VDT10

VMO10

BSC10

BMN10

BHR10

BDT10

BMO10

0 to 6

0 to 59

0 to 23

1 to 31

1 to 12

0 to 59

0 to 23

1 to 31

1 to 12

TSV2B

TSB2V

0

VSC22

VSC21

VMN21

VHR21

VDT21

0

VSC20

VMN20

VHR20

VDT20

VMO20

BSC20

BMN20

BHR20

BDT20

BMO20

VSC13

VMN13

VHR13

VDT13

VMO13

BSC13

BMN13

BHR13

BDT13

BMO13

VMN

VHR

VMN22

VMIL

0

VDT

0

VMO

BSC

0

BSC22

BSC21

BMN21

BHR21

BDT21

0

BMN

BHR

0

BMN22

BMIL

0

BDT

BMO

0

FN6667 Rev 6.00

January 9, 2015

Page 14 of 34

ISL12020M

TABLE 1. REGISTER MEMORY MAP (X INDICATES DEFAULT VARIES WITH EACH DEVICE. YELLOW SHADING INDICATES THOSE BITS SHOULD NOT BE

CHANGED BY THE USER) (Continued)

BIT

REG

ADDR. SECTION

NAME

7

6

5

4

3

2

1

0

RANGE DEFAULT

20h

21h

22h

23h

24h

25h

26h

27h

DSTCR

DstMoFd

DSTE

D

DstMoFd DstMoFd DstMoFd DstMoFd DstMoFd

20 13 12 11 10

1 to 12

00h

DstDwFd

DstDtFd

DstHrFd

DstMoRv

DstDwRv

DstDtRv

DstHrRv

D

DstDwFd DstWkFd DstWkFd DstWkFd DstDwFd DstDwFd DstDwFd

0 to 6

E

12

11

10

12

11

10

D

DstDtFd2 DstDtFd2 DstDtFd1 DstDtFd1 DstDtFd1 DstDtFd1

1 to 31

0 to 23

1

0

3

2

1

0

D

DstHrFd2 DstHrFd2 DstHrFd1 DstHrFd1 DstHrFd1 DstHrFd1

1

0

3

2

1

0

D

XDstMoR DstMoRv DstMoR1 DstMoRv DstMoRv 01 to 12

v20 13 2v 11 10

DstDwRv DstWkrv1 DstWkRv DstWkRv DstDwRv DstDwRv DstDwRv

0 to 6

E

2

11

10

12

11

10

D

DstDtRv2 DstDtRv2 DstDtRv1 DstDtRv1 DstDtRv1 DstDtRv1 01 to 31

1

0

3

2

1

0

D

DstHrRv2 DstHrRv2 DstHrRv1 DstHrRv1 DstHrRv1 DstHrRv1

0 to 23

1

TK05

0

3

2

1

0

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

TEMP

NPPM

XT0

TK0L

TK0M

NPPML

NPPMH

XT0

TK07

TK06

0

TK04

0

TK03

0

TK02

TK01

TK00

00 to FF

00 to 03

00 to FF

00 to 07

00 to FF

00 to 7F

00 to FF

00h

XXh

00h

0

NPPM7

0

TK09

TK08

NPPM6

0

NPPM5

0

NPPM4

0

NPPM3

0

NPPM2

NPPM10

XT2

NPPM1

NPPM9

XT1

NPPM0

NPPM8

XT0

D

XT4

XT3

ALPHAH ALPHAH

D

ALP_H6

GPM16

GPM26

ALP_H5

GPM15

GPM25

ALP_H4

GPM14

GPM24

ALP_H3

GPM13

GPM23

ALP_H2

GPM12

GPM22

ALP_H1

GPM11

GPM21

ALP_H0

GPM10

GPM20

GPM

GPM1

GPM2

GPM17

GPM27

LEAP YEARS

Real Time Clock Registers

Addresses [00h to 06h]

Leap years add the day February 29 and are defined as those years

that are divisible by 4. Years divisible by 100 are not leap years,

unless they are also divisible by 400. This means that the year 2000

is a leap year and the year 2100 is not. The ISL12020M does not

correct for the leap year in the year 2100.

RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW)

These registers depict BCD representations of the time. As such,

SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour)

can either be a 12-hour or 24-hour mode, DT (Date) is 1 to 31,

MO (Month) is 1 to 12, YR (Year) is 0 to 99 and DW (Day of the

Week) is 0 to 6.

Control and Status Registers

(CSR)

Addresses [07h to 0Fh]

The Control and Status Registers consist of the Status Register,

Interrupt and Alarm Register, Analog Trimming and Digital

Trimming Registers.

The DW register provides a Day of the Week status and uses three

bits DW2 to DW0 to represent the seven days of the week. The

counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-…

The assignment of a numerical value to a specific day of the

week is arbitrary and may be decided by the system software

designer. The default value is defined as “0”.

Status Register (SR)

The Status Register is located in the memory map at address

07h. This is a volatile register that provides either control or

status of RTC failure (RTCF), Battery Level Monitor (LBAT85,

LBAT75), alarm trigger, Daylight Saving Time, crystal oscillator

enable and temperature conversion in progress bit.

24-HOUR TIME

If the MIL bit of the HR register is “1”, the RTC uses a 24-hour

format. If the MIL bit is “0”, the RTC uses a 12-hour format and

HR21 bit functions as an AM/PM indicator with a “1”

representing PM. The clock defaults to 12-hour format time with

HR21 = “0”.

FN6667 Rev 6.00

January 9, 2015

Page 15 of 34

ISL12020M

clear when the V

is above the pre-selected trip level at the

next detection cycle either by manual or automatic trigger.

TABLE 2. STATUS REGISTER (SR)

BAT

ADDR

07h

7

6

5

4

3

2

1

0

In Battery Mode (V ), this bit indicates the device has entered

BAT

BUSY OSCF DSTDJ ALM LVDD LBAT85 LBAT75 RTCF

into battery mode by polling once every 10 minutes. The LBAT85

detection happens automatically once when the minute register

reaches x9h or x0h minutes.

BUSY BIT (BUSY)

Busy Bit indicates temperature sensing is in progress. In this

mode, Alpha, Beta and ITRO registers are disabled and cannot be

accessed.

Example - When the LBAT85 is Set To “1” In Battery Mode:

The minute the register changes to 19h when the device is in

battery mode, the LBAT85 is set to “1” the next time the device

switches back to Normal Mode.

OSCILLATOR FAIL BIT (OSCF)

Oscillator Fail Bit indicates that the oscillator has failed. The

oscillator frequency is either zero or very far from the desired

32.768kHz due to failure, PC board contamination or mechanical

issues.

Example - When the LBAT85 Remains at “0” In Battery

Mode:

If the device enters into battery mode after the minute register

reaches 20h and switches back to Normal Mode before the

minute register reaches 29h, then the LBAT85 bit will remain at

“0” the next time the device switches back to Normal Mode.

DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ)

DSTADJ is the Daylight Saving Time Adjusted Bit. It indicates the

daylight saving time forward adjustment has happened. If a DST

Forward event happens, DSTADJ will be set to “1”. The DSTADJ bit

will stay high when DSTFD event happens and will be reset to “0”

when the DST Reverse event happens. It is read-only and cannot

be written. Setting time during a DST forward period will not set

this bit to “1”.

LOW BATTERY INDICATOR 75% BIT (LBAT75)

In Normal Mode (V ), this bit indicates when the battery level

DD

has dropped below the preselected trip levels. The trip points are

selected by three bits: VB75Tp2, VB75Tp1 and VB75Tp0 in the

PWR_VBAT registers. The LBAT75 detection happens

automatically once every minute when seconds register reaches

59. The detection can also be manually triggered by setting the

TSE bit in BETA register to “1”. The LBAT75 bit is set when the

The DSTE bit must be enabled when the RTC time is more than

one hour before the DST Forward or DST Reverse event time

setting, or the DST event correction will not happen.

V

has dropped below the preselected trip level and will self

BAT

clear when the V

is above the preselected trip level at the next

DSTADJ is reset to “0” upon power-up. It will reset to “0” when the

DSTE bit in Register 15h is set to “0” (DST disabled), but no time

adjustment will happen.

BAT

detection cycle either by manual or automatic trigger.

In Battery Mode (V ), this bit indicates the device has entered

BAT

into battery mode by polling once every 10 minutes. The LBAT85

detection happens automatically once when the minute register

reaches x9h or x0h minutes.

ALARM BIT (ALM)

This bit announces if the alarm matches the real time clock. If

there is a match, the respective bit is set to “1”. This bit can be

manually reset to “0” by the user or automatically reset by

enabling the auto-reset bit (see ARST bit). A write to this bit in the

SR can only set it to “0”, not “1”. An alarm bit that is set by an

alarm occurring during an SR read operation will remain set after

the read operation is complete.

Example - When the LBAT75 is Set to “1” in Battery Mode:

The minute register changes to 30h when the device is in battery

mode, the LBAT75 is set to “1” the next time the device switches

back to Normal Mode.

Example - When the LBAT75 Remains at “0” in Battery Mode:

LOW V INDICATOR BIT (LVDD)

DD

If the device enters into battery mode after the minute register

reaches 49h and switches back to Normal Mode before minute

register reaches 50h, then the LBAT75 bit will remain at “0” the

next time the device switches back to Normal Mode.

This bit indicates when V has dropped below the pre-selected

DD

trip level (Brownout Mode). The trip points for the brownout levels

are selected by three bits: V Trip2, V Trip1 and V Trip0 in

DD

PWR_VDD registers. The LVDD detection is only enabled in V

mode and the detection happens in real time. The LVDD bit is set

DD

REAL TIME CLOCK FAIL BIT (RTCF)

whenever the V has dropped below the preselected trip level

and self clears whenever the V is above the preselected trip

DD

level.

This bit is set to a “1” after a total power failure. This is a read

only bit that is set by hardware (ISL12020M internally) when the

DD

device powers up after having lost all power (defined as V = 0V

DD

and V

BAT

= 0V). The bit is set regardless of whether V or V

DD

BAT

LOW BATTERY INDICATOR 85% BIT (LBAT85)

is applied first. The loss of only one of the supplies does not set

the RTCF bit to “1”. The first valid write to the RTC section after a

complete power failure resets the RTCF bit to “0” (writing one

byte is sufficient).

In Normal Mode (V ), this bit indicates when the battery level

DD

has dropped below the preselected trip levels. The trip points are

selected by three bits: VB85Tp2, VB85Tp1 and VB85Tp0 in the

PWR_VBAT registers. The LBAT85 detection happens

automatically once every minute when seconds register reaches

59. The detection can also be manually triggered by setting the

TSE bit in BETA register to “1”. The LBAT85 bit is set when the

V

has dropped below the preselected trip level and will self

BAT

FN6667 Rev 6.00

January 9, 2015

Page 16 of 34

ISL12020M

TABLE 5. FREQUENCY SELECTION OF IRQ/F

OUT

Interrupt Control Register (INT)

FREQUENCY,

TABLE 3. INTERRUPT CONTROL REGISTER (INT)

F

UNITS

Hz

FO3

0

FO2

0

FO1

0

FO0

0

OUT

ADDR

08h

7

6

5

4

3

2

1

0

ARST WRTC

IM

FOBATB FO3 FO2 FO1 FO0

32768

4096

1024

64

0

1

0

1

0

AUTOMATIC RESET BIT (ARST)

This bit enables/disables the automatic reset of the ALM, LVDD,

LBAT85 and LBAT75 status bits only. When ARST bit is set to “1”,

these status bits are reset to “0” after a valid read of the

respective status register (with a valid STOP condition). When the

ARST is cleared to “0”, the user must manually reset the ALM,

LVDD, LBAT85 and LBAT75 bits.

0

1

0

1

0

32

0

1

0

1

16

0

1

0

8

0

1

WRITE RTC ENABLE BIT (WRTC)

4

1

0

The WRTC bit enables or disables write capability into the RTC

Timing Registers. The factory default setting of this bit is “0”.

Upon initialization or power-up, the WRTC must be set to “1” to

enable the RTC. Upon the completion of a valid write (STOP), the

RTC starts counting. The RTC internal 1Hz signal is synchronized

to the STOP condition during a valid write cycle.

2

1

0

1

0

1

0

1/2

1/4

1/8

1/16

1/32

1

0

1

0

1

0

1

INTERRUPT/ALARM MODE BIT (IM)

1

0

This bit enables/disables the interrupt mode of the alarm

function. When the IM bit is set to “1”, the alarm will operate in

the interrupt mode, where an active low pulse width of 250ms

1

will appear at the IRQ/F

alarm, as defined by the alarm registers (0Ch to 11h). When the

IM bit is cleared to “0”, the alarm will operate in standard mode,

pin when the RTC is triggered by the

OUT

POWER SUPPLY CONTROL REGISTER (PWR_VDD)

Clear Time Stamp Bit (CLRTS)

TABLE 6.

where the IRQ/F

cleared to “0”.

pin will be set low until the ALM status bit is

OUT

ADDR

09h

7

6

0

5

0

4

0

3

0

2

1

0

TABLE 4.

CLRTS

V

Trip2

DD

V

Trip1

DD

V

Trip0

DD

IM BIT

INTERRUPT/ALARM FREQUENCY

0

1

Single Time Event Set By Alarm

This bit clears Time Stamp V to Battery (TSV2B) and Time

DD

Stamp Battery to V Registers (TSB2V). The default setting is 0

Repetitive/Recurring Time Event Set By Alarm

DD

(CLRTS = 0) and the Enabled setting is 1 (CLRTS = 1).

FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)

This bit enables/disables the IRQ/F pin during

V

Brownout Trip Voltage BITS (V Trip<2:0>)

DD

These bits set the trip level for the V alarm, indicating that V

DD DD

has dropped below a preset level. In this event, the LVDD bit in

the Status Register is set to “1”. See Table 7.

OUT

battery-backup mode (i.e. V

power source active). When the

BAT

FOBATB is set to “1”, the IRQ/F

pin is disabled during

OUT

battery-backup mode. This means that both the frequency output

and alarm output functions are disabled. When the FOBATB is

TABLE 7. V TRIP LEVELS

DD

cleared to “0”, the IRQ/F

backup mode. Note that the open-drain IRQ/F

OUT

pull-up to the battery voltage to operate in battery-backup mode.

pin is enabled during battery-

pin will need a

OUT

TRIP VOLTAGE

(V)

V

Trip2

DD

V

Trip1

DD

V

Trip0

DD

0

1

0

1

0

1

0

1

0

1

2.295

2.550

2.805

3.060

4.250

4.675

FREQUENCY OUT CONTROL BITS (FO<3:0>)

These bits enable/disable the frequency output function and

select the output frequency at the IRQ/F

pin. See Table 5 for

OUT

frequency selection. Default for the ISL12020M is FO<3:0> = 1h,

or 32.768kHz output (F is ON). When the frequency mode is

OUT

enabled, it will override the alarm mode at the IRQ/F

pin.

OUT

FN6667 Rev 6.00

January 9, 2015

Page 17 of 34

ISL12020M

BATTERY VOLTAGE TRIP VOLTAGE REGISTER

(PWR_VBAT)

TABLE 10. BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>)

BATTERY ALARM TRIP

LEVEL

This register controls the trip points for the two V

BAT

alarms, with

VB75Tp2

VB75Tp1

VB75Tp0

(V)

levels set to approximately 85% and 75% of the nominal battery

level.

0

1

0

1

0

1

0

1

0

1

0

1

0

1.875

2.025

2.250

2.475

2.700

3.750

4.125

TABLE 8.

ADDR

0Ah

7

6

5

4

3

2

1

0

D RESEALB VB85T VB85T VB85T VB75T VB75T VB75T

p2 p1 p0 p2 p1 p0

RESEAL BIT (RESEALB)

This is the Reseal bit for actively disconnecting V

pin from the

BAT

internal circuitry. Setting this bit allows the device to disconnect the

battery and eliminate standby current drain while the device is

Initial AT and DT setting Register (ITRO)

unused. Once V is powered up, this bit is reset and the V

pin is

DD

BAT

These bits are used to trim the initial error (at room temperature)

of the crystal. Both Digital Trimming (DT) and Analog Trimming

(AT) methods are available. The digital trimming uses clock pulse

skipping and insertion for frequency adjustment. Analog

trimming uses load capacitance adjustment to pull the oscillator

frequency. A range of +62.5ppm to -61.5ppm is possible with

combined digital and analog trimming.

then connected to the internal circuitry.

The application for this bit involves placing the chip on a board

with a battery and testing the board. Once the board is tested

and ready to ship, it is desirable to disconnect the battery to keep

it fresh until the board or unit is placed into final use. Setting

RESEALB = “1” initiates the battery disconnect and after V

DD

power is cycled down and up again, the RESEAL bit is cleared to

“0”.

Initial values for the ITR0 register are preset internally and

recalled to RAM registers on power-up. These values can be

overwritten by the user although this is not suggested as the

resulting temperature compensation performance will be

compromised. Aging adjustment is normally a few ppm and can

be handled by writing to the IATR section.

BATTERY LEVEL MONITOR TRIP BITS (VB85TP<2:0>)

Three bits select the first alarm (85% of Nominal V ) level for the

BAT

battery voltage monitor. There are total of 7 levels that could be

selected for the first alarm. Any of the of levels could be selected as

the first alarm with no reference as to nominal battery voltage level.

See Table 9.

AGING AND INITIAL TRIM DIGITAL TRIMMING BITS

(IDTR0<1:0>)

TABLE 9. VB85T ALARM LEVEL

These bits allow ±30.5ppm initial trimming range for the crystal

frequency. This is meant to be a coarse adjustment if the range

needed is outside that of the IATR control. See Table 11. The

IDTR0 register should only be changed while the TSE (Temp

Sense Enable) bit is “0”.

BATTERY ALARM TRIP

LEVEL

VB85Tp2

VB85Tp1

VB85Tp0

(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

2.125

2.295

2.550

2.805

3.060

4.250

4.675

The ISL12020M has a preset Initial Digital Trimming value

corresponding to the crystal in the module. This value is recalled

on initial power-up and should never be changed for best

temperature compensation performance, although the user may

change this preset value to adjust for aging or board mounting

changes if so desired.

TABLE 11. IDTR0 TRIMMING RANGE

IDTR01

IDTR00

TRIMMING RANGE

Default/Disabled

0

1

0

1

0

1

BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>)

+30.5ppm

0ppm

Three bits select the second alarm (75% of Nominal V ) level for

BAT

the battery voltage monitor. There are total of 7 levels that could be

selected for the second alarm. Any of the of levels could be selected

as the second alarm with no reference as to nominal Battery voltage

level. See Table 10.

-30.5ppm

FN6667 Rev 6.00

January 9, 2015

Page 18 of 34

ISL12020M

The IATR0 register should only be changed while the TSE (Temp

Sense Enable) bit is “0”.

AGING AND INITIAL ANALOG TRIMMING BITS

(IATR0<5:0>)

The Initial Analog Trimming Register allows +32ppm to -31ppm

adjustment in 1ppm/bit increments. This enables fine frequency

adjustment for trimming initial crystal accuracy error or to

correct for aging drift.

TABLE 12. INITIAL AT AND DT SETTING REGISTER

ADDR

0Bh

7

6

5

4

3

2

1

0

IDTR0 IDTR0 IATR0 IATR0 IATR0 IATR0 IATR0 IATR0

1

0

5

4

3

2

1

0

The ISL12020M has a preset Initial Analog Trimming value

corresponding to the crystal in the module. This value is recalled

on initial power-up and should never be changed for best

temperature compensation performance, although the user may

change this preset value to adjust for aging or board mounting

changes if so desired.

Note that setting the IATR to the lowest settings (-31ppm) with the

default 32kHz output can cause the oscillator frequency to

become unstable on power-up. The lowest settings for IATR should

be avoided to insure oscillator frequency integrity.

TABLE 13. IATRO TRIMMING RANGE

IATR05

IATR04

IATR03

IATR02

IATR01

IATR00

TRIMMING RANGE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

+32

+31

+30

+29

+28

+27

+26

+25

+24

+23

+22

+21

+20

+19

+18

+17

+16

+15

+14

+13

+12

+11

+10

+9

+8

+7

+6

+5

+4

+3

+2

+1

0

-1

-2

-3

-4

-5

-6

-7

FN6667 Rev 6.00

January 9, 2015

Page 19 of 34

ISL12020M

TABLE 13. IATRO TRIMMING RANGE (Continued)

IATR05

IATR04

IATR03

IATR02

IATR01

IATR00

TRIMMING RANGE

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

-8

-9

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

-22

-23

-24

-25

-26

-27

-28

-29

-30

-31

ALPHA Register (ALPHA)

BETA Register (BETA)

TABLE 14. ALPHA REGISTER

TABLE 15.

4

ADDR

0Ch

7

6

5

4

3

2

1

0

ADDR

7

6

5

3

2

1

0

D

ALPHA ALPHA ALPHA ALPHA ALPHA ALPHA ALPHA

0Dh TSE BTSE BTSR BETA4 BETA3 BETA2 BETA1 BETA0

6

5

4

3

2

1

0

TEMPERATURE SENSOR ENABLED BIT (TSE)

The ALPHA variable is 8 bits and is defined as the temperature

coefficient of crystal from -40°C to T0, or the ALPHA Cold (there

is an Alpha Hot register that must be programmed as well). It is

This bit enables the Temperature Sensing operation, including the

temperature sensor, A/D converter and FATR/FDTR register

adjustment. The default mode after power-up is disabled (TSE = 0).

To enable the operation, TSE should be set to 1 (TSE = 1). When

temp sense is disabled, the initial values for IATR and IDTR registers

are used for frequency control.

2

normally given in units of ppm/°C , with a typical value of

-0.034. The ISL12020M device uses a scaled version of the

absolute value of this coefficient in order to get an integer value.

Therefore, ALPHA<7:0> is defined as the (|Actual ALPHA Value| x

2048) and converted to binary. For example, a crystal with Alpha

All changes to the IDTR, IATR, ALPHA and BETA registers must be

made with TSE = 0. After loading the new values, TSE can be

enabled and the new values are used. When TSE is set to 1, the

temperature conversion cycle begins and will end when two

temperature conversions are completed. The average of the two

conversions is in the TEMP registers.

2

of -0.034ppm/°C is first scaled (|2048*(-0.034)| = 70d) and

then converted to a binary number of 01000110b.

The practical range of Actual ALPHA values is from -0.020 to

-0.060.

The ISL12020M has a preset ALPHA value corresponding to the

crystal in the module. This value is recalled on initial power-up

and should remain unchanged for best compensation

performance, although the user can override this preset value if

so desired.

TEMP SENSOR CONVERSION IN BATTERY MODE BIT

(BTSE)

This bit enables the Temperature Sensing and Correction in battery

mode. BTSE = 0 (default) no conversion, Temp Sensing or

The ALPHA register should only be changed while the TSE (Temp

Sense Enable) bit is “0”. Note that both the ALPHA and the

ALPHA Hot registers need to be programmed with values for full

range temperature compensation.

Compensation in battery mode. BTSE = 1 indicates Temp Sensing

and Compensation enabled in battery mode. The BTSE is disabled

when the battery voltage is lower than 2.7V. No temperature

compensation will take place with V <2.7V.

BAT

FN6667 Rev 6.00

January 9, 2015

Page 20 of 34

ISL12020M

The BETA VALUES result is indexed in the right hand column and

the resulting Beta factor (for the register) is in the same row in

the left column.

FREQUENCY OF TEMPERATURE SENSING AND

CORRECTION BIT (BTSR)

This bit controls the frequency of Temp Sensing and Correction.

BTSR = 0 default mode is every 10 minutes, BTSR = 1 is every

1.0 minute. Note that BTSE has to be enabled in both cases. See

Table 16.

The ISL12020M has a preset BETA value corresponding to the

crystal in the module. This value is recalled on initial power-up

and should never be changed for best temperature

compensation performance, although the user may override this

preset value if so desired.

The temperature measurement conversion time is the same for

battery mode as for V mode, approximately 22ms. The battery

DD

mode current will increase during this conversion time to

typically 68µA. The average increase in battery current is much

lower than this due to the small duty cycle of the ON-time versus

OFF-time for the conversion.

The value for BETA should only be changed while the TSE (Temp

Sense Enable) bit is “0”. The procedure for writing the BETA

register involves two steps. First, write the new value of BETA with

TSE = 0. Then write the same value of BETA with TSE = 1. This will

insure the next temp sense cycle will use the new BETA value.

To figure the average increase in battery current, we take the

change in current times the duty cycle. For the 1 minute

temperature period the average current is as shown in

Equation 1:

TABLE 17. BETA VALUES

BETA<4:0>

01000

00111

00110

00101

00100

00011

00010

00001

00000

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

AT STEP ADJUSTMENT

0.5000

0.5625

0.6250

0.6875

0.7500

0.8125

0.8750

0.9375

1.0000

1.0625

1.1250

1.1875

1.2500

1.3125

1.3750

1.4375

1.5000

1.5625

1.6250

1.6875

1.7500

1.8125

1.8750

1.9375

2.0000

0.022s

60s

(EQ. 1)

-----------------

 68A= 250nA

I

=

BAT

For the 10 minute temperature period the average current is as

shown in Equation 2:

0.022s

(EQ. 2)

-----------------

 68A= 25nA

I

=

BAT

600s

If the application has a stable temperature environment that

doesn’t change quickly, the 10 minute option will work well and

the backup battery lifetime impact is minimized. If quick

temperature variations are expected (multiple cycles of more

than 10° within an hour), then the 1 minute option should be

considered and the slightly higher battery current figured into

overall battery life.

TABLE 16. FREQUENCY OF TEMPERATURE SENSING AND

CORRECTION BIT

TC PERIOD IN

BATTERY MODE

BTSE

BTSR

0

1

0

1

0

1

OFF

10 Minutes

1 Minute

GAIN FACTOR OF AT BIT (BETA<4:0>)

Beta is specified to take care of the Cm variations of the crystal.

Most crystals specify Cm around 2.2fF. For example, if Cm > 2.2fF,

the actual AT steps may reduce from 1ppm/step to approximately

0.80ppm/step. Beta is then used to adjust for this variation and

restore the step size to 1ppm/step.

BETA values are limited in the range from 01000 to 11111 as

shown in Table 17. To use Table 17, the device is tested at two AT

settings in Equation 3:

(EQ. 3)

BETA VALUES = ATmax – ATmin/63

Where:

AT(max) = F

in ppm (at AT = 00H) and

in ppm (at AT = 3FH).

OUT

AT(min) = F

OUT

FN6667 Rev 6.00

January 9, 2015

Page 21 of 34

ISL12020M

Final Analog Trimming Register (FATR)

ALARM Registers (10h to 15h)

This register shows the final setting of AT after temperature

correction. It is read-only; the user cannot overwrite a value to this

register. This value is accessible as a means of monitoring the

temperature compensation function. See Tables 18 and 19 (for

values).

The alarm register bytes are set up identical to the RTC register

bytes, except that the MSB of each byte functions as an enable

bit (enable = “1”). These enable bits specify which alarm

registers (seconds, minutes, etc.) are used to make the

comparison. Note that there is no alarm byte for year.

The alarm function works as a comparison between the alarm

registers and the RTC registers. As the RTC advances, the alarm

will be triggered once a match occurs between the alarm

registers and the RTC registers. Any one alarm register, multiple

registers, or all registers can be enabled for a match.

TABLE 18. FINAL ANALOG TRIMMING REGISTER

ADDR

0Eh

7

0

6

0

5

4

3

2

1

0

FATR5 FATR4 FATR3 FATR2 FATR1 FATR0

Final Digital Trimming Register (FDTR)

There are two alarm operation modes: Single Event and periodic

Interrupt Mode:

This register shows the final setting of DT after temperature

correction. It is read-only; the user cannot overwrite a value to

this register. The value is accessible as a means of monitoring

the temperature compensation function. The corresponding

clock adjustment values are shown in Table 20. The FDTR setting

has both positive and negative settings to adjust for any offset in

the crystal..

• Single Event Mode is enabled by setting the bit 7 on any of the

Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “0” and

disabling the frequency output. This mode permits a one-time

match between the Alarm registers and the RTC registers.

Once this match occurs, the ALM bit is set to “1” and the

IRQ/F

output will be pulled low and will remain low until

OUT

the ALM bit is reset. This can be done manually or by using the

auto-reset feature.

TABLE 19. FINAL DIGITAL TRIMMING REGISTER

ADDR

0Fh

7

0

6

0

5

0

4

3

2

1

0

• Interrupt Mode is enabled by setting the bit 7 on any of the

Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “1” and

FDTR4 FDTR3 FDTR2 FDTR1 FDTR0

disabling the frequency output. The IRQ/F

output will now

OUT

TABLE 20. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL

TRIMMING REGISTER

be pulsed each time an alarm occurs. This means that once

the interrupt mode alarm is set, it will continue to alarm for

each occurring match of the alarm and present time. This

mode is convenient for hourly or daily hardware interrupts in

microcontroller applications such as security cameras or utility

meter reading.

FDTR<4:0>

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

DECIMAL

ppm ADJUSTMENT

0

1

30.5

2

61

To clear a single event alarm, the ALM bit in the status register

must be set to “0” with a write. Note that if the ARST bit is set to

1 (address 08h, bit 7), the ALM bit will automatically be cleared

when the status register is read.

3

91.5

4

122

5

152.5

183

Following are examples of both Single Event and periodic

Interrupt Mode alarms.

6

7

213.5

244

Example 1

8

9

274.5

305

• Alarm set with single interrupt (IM = “0”)

• A single alarm will occur on January 1 at 11:30 a.m.

• Set Alarm registers as follows:

10

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-30.5

-61

-91.5

-122

-152.5

-183

-213.5

-244

-274.5

-305

FN6667 Rev 6.00

January 9, 2015

Page 22 of 34

ISL12020M

captures the FIRST V to Battery Voltage transition time and will

DD

not update upon subsequent events, until cleared (only the first

event is captured before clearing). Set CLRTS = 1 to clear this

TABLE 21.

BIT

ALARM

REGISTER

7

0

1

6

0

5

0

1

4

0

1

3

0

2

0

1

0

HEX

DESCRIPTION

register (Add 09h, PWR_V register).

DD

SCA0

00h Seconds disabled

Note that the time stamp registers are cleared to all “0”,

including the month and day, which is different from the RTC and

alarm registers (those registers default to 01h). This is the

indicator that no time stamping has occurred since the last clear

or initial power-up. Once a time stamp occurs, there will be a

non-zero time stamp.

MNA0

B0h Minutes set to 30,

enabled

HRA0

DTA0

1

0

1

0

1

0

91h Hours set to 11,

enabled

81h Date set to 1,

enabled

Time Stamp Battery to V Registers (TSB2V)

DD

MOA0

DWA0

81h Month set to 1,

enabled

The Time Stamp Battery to V Register bytes are identical to

DD

the RTC register bytes, except they do not extend beyond Month.

00h Day of week

disabled

The Time Stamp captures the LAST transition of V

to V

BAT

DD

(only the last event of a series of power-up/down events is

retained). Set CLRTS = 1 to clear this register (Add 09h,

After these registers are set, an alarm will be generated when the

RTC advances to exactly 11:30 a.m. on January 1 (after seconds

changes from 59 to 00) by setting the ALM bit in the status register

PWR_V register).

DD

DST Control Registers (DSTCR)

to “1” and also bringing the IRQ/F

output low.

OUT

8 bytes of control registers have been assigned for the Daylight

Savings Time (DST) functions. DST beginning (set Forward) time

is controlled by the registers DstMoFd, DstDwFd, DstDtFd and

DstHrFd. DST ending time (set Backward or Reverse) is controlled

by DstMoRv, DstDwRv, DstDtRv and DstHrRv.

Example 2

• Pulsed interrupt once per minute (IM = “1”)

• Interrupts at one minute intervals when the seconds register is

at 30s.

• Set Alarm registers as follows:

TABLE 22.

Tables 23 and 24 describe the structure and functions of the DSTCR.

DST FORWARD REGISTERS (20H TO 23H)

BIT

DST forward is controlled by the following DST Registers:

ALARM

REGISTER

7

1

6

0

5

1

4

1

3

0

2

0

1

0

HEX

DESCRIPTION

DST Enable

SCA0

B0h Seconds set to 30,

enabled

DSTE is the DST Enabling Bit located in Bit 7 of register 20h

(DstMoFdxx). Set DSTE = 1 will enable the DSTE function. Upon

powering up for the first time (including battery), the DSTE bit

defaults to “0”. When DSTE is set to “1” the RTC time must be at

least one hour before the scheduled DST time change for the

correction to take place. When DSTE is set to “0”, the DSTADJ bit

in the Status Register automatically resets to “0”.

MNA0

HRA0

DTA0

0

00h Minutes disabled

00h Hours disabled

00h Date disabled

MOA0

DWA0

00h Month disabled

00h Day of week disabled

DST Month Forward

DstMoFd sets the Month that DST starts. The format is the same

as for the RTC register month, from 1 to 12. The default value for

the DST begin month is 00h.

Once the registers are set, the following waveform will be seen at

IRQ/F

:

OUT

RTC AND ALARM REGISTERS ARE BOTH “30s”

DST Day/Week Forward

DstDwFd contains both the Day of the Week and the Week of the

Month data for DST Forward control. DST can be controlled either

by actual date or by setting both the Week of the month and the

Day of the Week. DstDwFdE sets the priority of the Day/Week

over the Date. For DstDwFdE = 1, Day/Week is the priority. You

must have the correct Day of Week entered in the RTC registers

for the Day/Week correction to work properly.

60s

FIGURE 15. IRQ/F

OUT

WAVEFORM

Note that the status register ALM bit will be set each time the

alarm is triggered, but does not need to be read or cleared.

Time Stamp V to Battery Registers (TSV2B)

DD

The TSV2B Register bytes are identical to the RTC register bytes,

except they do not extend beyond the Month. The Time Stamp

FN6667 Rev 6.00

January 9, 2015

Page 23 of 34

ISL12020M

TABLE 23. DST FORWARD REGISTERS

ADDRESS

20h

FUNCTION

Month Forward

Day Forward

Date Forward

Hour Forward

7

DSTE

0

6

5

4

3

2

1

0

MoFd20

WkFd11

DtFd20

HrFd20

MoFd13

WkFd10

DtFd13

HrFd13

MoFd12

DwFd12

DtFd12

HrFd12

MoFd11

DwFd11

DtFd11

HrFd11

MoFd10

DwFd10

DtFd10

HrFd10

21h

DwFdE

WkFd12

DtFd21

HrFd21

22h

0

23h

TABLE 24. DST REVERSE REGISTERS

ADDRESS

24h

NAME

7

0

6

5

4

3

2

1

0

Month Reverse

Day Reverse

Date Reverse

Hour Reverse

0

MoRv20

WkRv11

DtRv20

HrRv20

MoRv13

WkRv10

DtRv13

HrRv13

MoRv12

DwRv12

DtRv12

HrRv12

MoRv11

DwRv11

DtRv11

HrRv11

MoRv10

DwRv10

DtRv10

HrRv10

25h

DwRvE

WkRv12

DtRv21

HrRv21

26h

0

27h

• Bits 0, 1, 2 contain the Day of the week information, which

sets the Day of the Week that DST starts. Note that Day of the

week counts from 0 to 6, like the RTC registers. The default for

the DST Forward Day of the Week is 00h (normally Sunday).

must have the correct Day of Week entered in the RTC registers

for the Day/Week correction to work properly.

• Bits 0, 1, 2 contain the Day of the week information, which

sets the Day of the Week that DST ends. Note that Day of the

week counts from 0 to 6, like the RTC registers. The default for

the DST Reverse Day of the Week is 00h (normally Sunday).

• Bits 3, 4, 5 contain the Week of the Month information that

sets the week that DST starts. The range is from 1 to 5 and

Week 7 is used to indicate the last week of the month. The

default for the DST Forward Week of the Month is 00h.

• Bits 3, 4, 5 contain the Week of the Month information that sets

the week that DST ends. The range is from 1 to 5 and Week 7 is

used to indicate the last week of the month. The default for the

DST Reverse Week of the Month is 00h.

DST Date Forward

DstDtfd controls which Date DST begins. The format for the Date

is the same as for the RTC register, from 1 to 31. The default

value for DST forward date is 00h. DstDtFd is only effective if

DstDwFdE = 0.

DST Date Reverse

DstDtRv controls which Date DST ends. The format for the Date is

the same as for the RTC register, from 1 to 31. The default value

for DST Date Reverse is 00h. The DstDtRv is only effective if the

DwRvE = 0.

DST Hour Forward

DstHrFd controls the hour that DST begins. The RTC hour and

DstHrFd registers have the same formats except there is no

Military bit for DST hour. The user sets the DST hour with the

same format as used for the RTC hour (AM/PM or MIL) but

without the MIL bit and the DST will still advance as if the MIL bit

were there. The default value for DST hour Forward is 00h.

DST Hour Reverse

DstHrRv controls the hour that DST ends. The RTC hour and

DstHrFd registers have the same formats except there is no

Military bit for DST hour. The user sets the DST hour with the

same format as used for the RTC hour (AM/PM or MIL) but

without the MIL bit and the DST will still advance as if the MIL bit

were there. The default value for DST hour Reverse is 00h.

DST REVERSE REGISTERS (24H TO 27H)

DST end (reverse) is controlled by the following DST Registers:

TEMP Registers (TEMP)

DST Month Reverse

The temperature sensor produces an analog voltage output,

which is input to an A/D converter and produces a 10-bit

temperature value in degrees Kelvin. TK07:00 are the LSBs of the

code and TK09:08 are the MSBs of the code. The temperature

result is actually the average of two successive temperature

measurements to produce greater resolution for the temperature

control. The output code can be converted to degrees Centigrade

by first converting from binary to decimal, dividing by 2 and then

subtracting 273d.

DstMoRv sets the Month that DST ends. The format is the same

as for the RTC register month, from 1 to 12. The default value for

the DST end month is October (10h).

DST Day/Week Reverse

DstDwRv contains both the Day of the Week and the Week of the

Month data for DST Reverse control. DST can be controlled either

by actual date or by setting both the Week of the month and the

Day of the Week. DstDwRvE sets the priority of the Day/Week

over the Date. For DstDwRvE = 1, Day/Week is the priority. You

(EQ. 4)

Temperature in °C = [(TK <9:0>)/2] - 273

FN6667 Rev 6.00

January 9, 2015

Page 24 of 34

ISL12020M

The practical range for the temp sensor register output is from 446d

to 726d, or -50°C to +90°C. The temperature compensation

function is only guaranteed over -40°C to +85°C. The TSE bit must

be set to “1” to enable temperature sensing.

TABLE 26. TURNOVER TEMPERATURE

ADDR

2Ch

7

0

6

0

5

0

4

3

2

1

0

XT4

XT3

XT2

XT1

XT0

TABLE 25.

The ISL12020M has a preset turnover temperature

corresponding to the crystal in the module. This value is recalled

on initial power-up and should never be changed for best

temperature compensation performance, although the user may

override this preset value if so desired.

TEMP

TK0L

TK0M

7

6

5

4

3

2

1

0

TK07 TK06 TK05 TK04 TK03 TK02 TK01 TK00

TK09 TK08

0

Table 27 shows the values available, with a range from +17.5°C

to +32.5°C in +0.5°C increments. The default value is 00000b

or +25°C.

NPPM Registers (NPPM)

The NPPM value is exactly 2x the net correction required to bring

the oscillator to 0ppm error. The value is the combination of

oscillator Initial Correction (IPPM) and crystal temperature

dependent correction (CPPM).

TABLE 27. XT0 VALUES

XT<4:0>

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

TURNOVER TEMPERATURE

32.5

32.0

31.5

31

IPPM is used to compensate the oscillator offset at room

temperature and is controlled by the ITR0 and BETA registers,

which are fixed during factor test.

The CPPM compensates the oscillator frequency fluctuation over

temperature. It is determined by the temperature (T), crystal

curvature parameter (ALPHA) and crystal turn-over temperature

(XT0). T is the result of the temp sensor/ADC conversion, whose

decimal result is 2x the actual temperature in Kelvin. ALPHA is

from either the ALPHA (cold) or ALPHAH (hot) register depending

on T and XT0 is from the XT0 register.

30.5

30

29.5

29.0

28.5

28.0

27.5

27.0

26.5

26.0

25.5

25.0

24.5

24.0

23.5

23.0

22.5

22.0

21.5

21.0

20.5

20.0

19.5

19.0

18.5

NPPM is governed by Equation 5:

NPPM = IPPM(ITR0,BETA) + ALPHA x (T-T0)2

NPPM = IPPM + CPPM

2

ALPHA  T – T0

(EQ. 5)

---------------------------------------------------

NPPM = IPPM +

4096

Where

ALPHA =   2048

T is the reading of the ADC, result is 2 x temperature in degrees

Kelvin.

(EQ. 6)

T = 2  298 + XT0

or

T = 596 + XT0

Note that NPPM can also be predicted from the FATR and FDTR

register by the relationship (all values in decimal):

NPPM = 2*(BETA*FATR - (FDTR-16))

XT0 Registers (XT0)

TURNOVER TEMPERATURE (XT<3:0>)

The apex of the Alpha curve occurs at a point called the turnover

temperature, or XT0. Crystals normally have a turnover

temperature between +20°C and +30°C, with most occurring

near +25°C.

FN6667 Rev 6.00

January 9, 2015

Page 25 of 34

ISL12020M

TABLE 27. XT0 VALUES (Continued)

The ALPHAH register should only be changed while the TSE

(Temp Sense Enable) bit is “0”.

XT<4:0>

TURNOVER TEMPERATURE

11110

11111

18.0

17.5

User Registers (Accessed by

Using Slave Address 1010111x)

ALPHA Hot Register (ALPHAH)

Addresses [00h to 7Fh]

These registers are 128 bytes of battery-backed user SRAM. The

separate I C slave address must be used to read and write to

these registers.

TABLE 28. ALPHA HOT REGISTER

2

ADDR

2Dh

7

6

5

4

3

2

1

0

D

ALP_H ALP_H ALP_H ALP_H ALP_H ALP_H ALP_H

6

2

5

4

3

2

1

0

I C Serial Interface

The ISL12020M supports a bidirectional bus oriented protocol.

The protocol defines any device that sends data onto the bus as a

transmitter and the receiving device as the receiver. The device

controlling the transfer is the master and the device being

controlled is the slave. The master always initiates data transfers

and provides the clock for both transmit and receive operations.

Therefore, the ISL12020M operates as a slave device in all

applications.

The ALPHA Hot variable is 7 bits and is defined as the temperature

coefficient of Crystal from the XT0 value to +85°C (both Alpha Hot

and Alpha Cold must be programmed to provide full temperature

2

compensation). It is normally given in units of ppm/°C , with a

typical value of -0.034. Like the ALPHA cold version, a scaled

version of the absolute value of this coefficient is used in order to

get an integer value. Therefore, ALP_H<7:0> is defined as the

(|Actual Alpha Hot Value| x 2048) and converted to binary. For

2

All communication over the I C interface is conducted by sending

example, a crystal with Alpha Hot of -0.034ppm/°C is first scaled

the MSB of each byte of data first.

(|2048*(-0.034)| = 70d) and then converted to a binary number

of 01000110b.

Protocol Conventions

The practical range of Actual ALPHAH values is from -0.020 to

-0.060.

Data states on the SDA line can change only during SCL LOW

periods. SDA state changes during SCL HIGH are reserved for

indicating START and STOP conditions (see Figure 16). On

power-up of the ISL12020M, the SDA pin is in the input mode.

The ISL12020M has a preset ALPHAH value corresponding to the

crystal in the module. This value is recalled on initial power-up

and should never be changed for best temperature

compensation performance, although the user may override this

preset value if so desired.

.

SCL

SDA

DATA

STABLE

DATA

CHANGE STABLE

DATA

START

STOP

FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS

SCL FROM

MASTER

1

8

9

SDA OUTPUT FROM

TRANSMITTER

HIGH IMPEDANCE

SDA OUTPUT FROM

RECEIVER

START

ACK

FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER

FN6667 Rev 6.00

January 9, 2015

Page 26 of 34

ISL12020M

WRITE

SIGNALS FROM

THE MASTER

S

T

A

R

T

S

T

O

P

IDENTIFICATION

BYTE

ADDRESS

BYTE

DATA

BYTE

SIGNAL AT SDA

1 1 0 1 1 1 1 0

0 0 0 0

SIGNALS FROM

THE ISL12020M

A

C

K

A

C

K

A

C

K

FIGURE 18. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)

2

All I C interface operations must begin with a START condition,

which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The

ISL12020M continuously monitors the SDA and SCL lines for the

START condition and does not respond to any command until this

condition is met (see Figure 16). A START condition is ignored

during the power-up sequence.

In a random read operation, the slave byte in the “dummy write”

portion must match the slave byte in the “read” section. For a

random read of the Control/Status Registers, the slave byte must be

“1101111x” in both places.

SLAVE ADDRESS

1

R/

1

0

1

BYTE

2

All I C interface operations must be terminated by a STOP

condition, which is a LOW-to-HIGH transition of SDA while SCL is

HIGH (see Figure 16). A STOP condition at the end of a read

operation or at the end of a write operation to memory only

places the device in its standby mode.

WORD ADDRESS

A7

D7

A6

D6

A5

D5

A4

D4

A3

D3

A2

D2

A1

D1

A0

D0

DATA BYTE

An acknowledge (ACK) is a software convention used to indicate

a successful data transfer. The transmitting device, either master

or slave, releases the SDA bus after transmitting eight bits.

During the ninth clock cycle, the receiver pulls the SDA line LOW

to acknowledge the reception of the eight bits of data (see

Figure 17).

FIGURE 19. SLAVE ADDRESS, WORD ADDRESS AND DATA BYTES

Write Operation

A Write operation requires a START condition, followed by a valid

Identification Byte, a valid Address Byte, a Data Byte and a STOP

condition. After each of the three bytes, the ISL12020M

The ISL12020M responds with an ACK after recognition of a

START condition followed by a valid Identification Byte and once

again, after successful receipt of an Address Byte. The

ISL12020M also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an ACK

after receiving a Data Byte of a read operation.

2

responds with an ACK. At this time, the I C interface enters a

standby state.

Read Operation

A Read operation consists of a three byte instruction, followed by

one or more Data Bytes (see Figure 20). The master initiates the

operation issuing the following sequence: a START, the

Identification byte with the R/W bit set to “0”, an Address Byte, a

second START and a second Identification byte with the R/W bit

set to “1”. After each of the three bytes, the ISL12020M responds

with an ACK. Then the ISL12020M transmits Data Bytes as long as

the master responds with an ACK during the SCL cycle following

the eighth bit of each byte. The master terminates the read

operation (issuing a STOP condition) following the last bit of the

last Data Byte (see Figure 20).

Device Addressing

Following a start condition, the master must output a Slave Address

Byte. The 7 MSBs are the device identifiers. These bits are

“1101111” for the RTC registers and “1010111” for the User SRAM.

The last bit of the Slave Address Byte defines a read or write

operation to be performed. When this R/W bit is a “1”, a read

operation is selected. A “0” selects a write operation (refer to

Figure 19).

After loading the entire Slave Address Byte from the SDA bus, the

ISL12020M compares the device identifier and device select bits

with “1101111” or “1010111”. Upon a correct compare, the device

outputs an acknowledge on the SDA line.

The Data Bytes are from the memory location indicated by an

internal pointer. This pointer’s initial value is determined by the

Address Byte in the Read operation instruction and increments

by one during transmission of each Data Byte. After reaching the

memory location 2Fh, the pointer “rolls over” to 00h and the

device continues to output data for each ACK received.

Following the Slave Byte is a one byte word address. The word

address is either supplied by the master device or obtained from an

internal counter. On power-up, the internal address counter is set to

address 00h, so a current address read starts at address 00h. When

required, as part of a random read, the master must supply the 1

Word Address Bytes, as shown in Figure 20.

FN6667 Rev 6.00

January 9, 2015

Page 27 of 34

ISL12020M

S

T

A

R

T

S

T

A

R

T

SIGNALS

FROM THE

MASTER

S

T

O

P

IDENTIFICATION

BYTE WITH

R/W = 0

IDENTIFICATION

BYTE WITH

R/W = 1

A

C

K

A

C

K

ADDRESS

BYTE

SIGNAL AT

SDA

1 1 0 1 1 1 1 0

1 1 0 1 1 1 1

1

A

C

K

A

C

K

A

C

K

SIGNALS FROM

THE SLAVE

FIRST READ

DATA BYTE

LAST READ

DATA BYTE

FIGURE 20. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)

.

D

Application Section

Power Supply Considerations

The ISL12022M contains programmed EEPROM registers which

are recalled to volatile RAM registers during initial power-up.

These registers contain DC voltage, frequency and temperature

calibration settings. Initial power-up can be either application of

BAT

V

= 2.7V

ISL12020M

VDD

J

BAT

DD

TO 5.5V

BAT43W

VBAT

+

V

= 1.8V

BAT

C

IN

0.1µF

TO 3.2V

C

BAT

0.1µF

GND

V

or V power, whichever is first. It is important that the

BAT

DD

FIGURE 21. SUGGESTED BATTERY-BACKUP CIRCUIT

initial power-up meet the power supply slew rate specification to

avoid faulty EEPROM power-up recall. Also, any glitches or low

voltage DC pauses should be avoided, as these may activate

recall at a low voltage and load erroneous data into the

The V negative slew rate should be limited to below the data

DD

sheet spec (10V/ms) otherwise battery switchover can be

delayed, resulting in SRAM contents corruption and oscillator

operation interruption.

calibration registers. Note that a very slow V ramp rate

DD

(outside data sheet limits) will almost always trigger erroneous

recall and should be avoided entirely.

Some applications will require separate supplies for the RTC V

DD

2

and the I C pullups. This is not advised, as it may compromise

2

the operation of the I C bus. For applications that do require

Battery-Backup Details

The ISL12020M has automatic switchover to battery-backup

serial bus communication with the RTC V powered down, the

DD

SDA pin must be pulled low during the time the RTC V ramps

DD

down to 0V. Otherwise, the device may lose serial bus

when the V drops below the V

mode threshold. A wide

DD BAT

variety of backup sources can be used, including standard and

rechargeable lithium, Super Capacitors, or regulated secondary

sources. The serial interface is disabled in battery-backup, while

the oscillator and RTC registers are operational. The SRAM

register contents are powered to preserve their contents as well.

communications once V is powered up and will return to

DD

normal operation ONLY once V and V

DD

are both powered

BAT

down together.

Layout Considerations

The ISL12020M contains a quarts crystal and requires special

handling during PC board assembly. Excessive shock and vibrations

should be avoided. Ultrasound cleaning is not advisable. See Note 7

on page 6 in the electrical specifications table pertaining to solder

reflow effects on oscillator accuracy.

The input voltage range for VBAT is 1.8V to 5.5V, but keep in

mind the temperature compensation only operates for

V

> 2.7V. Note that the device is not guaranteed to operate

BAT

with a V

< 1.8V, so the battery should be changed before

BAT

discharging to that level. It is strongly advised to monitor the low

battery indicators in the status registers and take action to

replace discharged batteries.

The crystal pins X1 and X2 have a very high impedance and

oscillator circuits operating at low frequencies (such as

32.768kHz) are known to pick up noise very easily if layout

precautions are not followed. Most instances of erratic clocking

or large accuracy errors can be traced to the susceptibility of the

oscillator circuit to interference from adjacent high speed clock

or data lines. Careful layout of the RTC circuit will avoid noise

pickup and insure accurate clocking.

If a Super Capacitor is used, it is possible that it may discharge to

below 1.8V during prolonged power-down. Once powered up, the

device may lose serial bus communications until both V and

DD

V

are powered down together. To avoid that situation,

BAT

including situations where a battery may discharge deeply, the

circuit in Figure 21 can be used.

The diode, D , will add a small drop to the battery voltage but

BAT

will protect the circuit should battery voltage drop below 1.8V.

The jumper is added as a safeguard should the battery ever need

to be disconnect from the circuit.

FN6667 Rev 6.00

January 9, 2015

Page 28 of 34

ISL12020M

Figure 22 shows a suggested layout for the ISL12020M device.

Three main precautions should be followed:

parasitic elements in the scope probe. Use the F output and a

OUT

frequency counter for the most accurate results.

1. Do not run the serial bus lines or any high speed logic lines in

the vicinity of the X1 and X2 pins. These logic level lines can

induce noise in the oscillator circuit, causing misclocking.

Temperature Compensation Operation

The ISL12020M temperature compensation feature needs to be

enabled by the user. This must be done in a specific order as

follows:

2. Add a ground trace around the device with one end

terminated at the chip ground. This guard ring will provide

termination for emitted noise in the vicinity of the RTC device.

1. Read register 0Dh, the BETA register. This register contains

the 5-bit BETA trimmed value, which is automatically loaded

on initial power-up. Mask off the 5LSB’s of the value just read.

3. Do not run a ground or power plane immediately under the

RTC. This will add capacitance to the X1/X2 pins and change

the trimmed frequency of the oscillator. Instead, try to leave a

2. Bit 7 of the BETA register is the master enable control for

temperature sense operation. Set this to “1” to allow

continuous temperature frequency correction. Frequency

gap in any planes under the RTC device.

.

correction will then happen every 60s with V applied.

DD

GROUND

RING

3. Bits 5 and 6 of the BETA register control temperature

compensation in battery-backup mode (see Table 16 on

page 21). Set the values for the operation desired.

4. Write back to register 0Dh making sure not to change the 5

LSB values and include the desired compensation control

bits.

F

OUT

Note that every time the BETA register is written with the TSE

bit = 1, a temperature compensation cycle is instigated and a

new correction value will be loaded into the FATR/FDTR registers

(if the temperature changed since the last conversion).

SCL

SDA

Also note that registers 0Bh and 0Ch, the ITR0 and ALPHA

registers, should not be changed. If they must be written be sure

to write the same values that are recalled from initial power-up.

The ITR0 register may be written if the user wishes to recalibrate

the oscillator frequency at room temperature for aging or board

mounting. The original recalled value can be rewritten if desired

after testing.

FIGURE 22. SUGGESTED LAYOUT FOR ISL12020M

The best way to run clock lines around the RTC is to stay outside

of the ground ring by at least a few millimeters. Also, use the

V

and V as guard ring lines as well, they can isolate clock

BAT

DD

lines from the X1 and X2 pins. In addition, if the IRQ/F

pin is

OUT

used as a clock, it should be routed away from the RTC device as

well.

Daylight Savings Time (DST) Example

DST involves setting the forward and back times and allowing the

RTC device to automatically advance the time or set the time

back. This can be done for current year and future years. Many

regions have DST rules that use standard months, weeks and

time of the day, which permit a preprogrammed, permanent

setting.

Measuring Oscillator Accuracy

The best way to analyze the ISL12020M frequency accuracy is to

set the IRQ/F

pin for a specific frequency and look at the

output of that pin on a high accuracy frequency counter (at least

OUT

7 digits accuracy). Note that the IRQ/F

will require a pull-up resistor.

is an drain output and

OUT

An example setup for the ISL12020M is in Table 29.

TABLE 29. DST EXAMPLE

Using the 1.0Hz output frequency is the most convenient as the

ppm error is just as shown in Equation 7:

VARIABLE

VALUE

REGISTER

15h

VALUE

84h

(EQ. 7)

ppm error = F

– 1  1e6

OUT

Month Forward and DST

Enable

April

Other frequencies may be used for measurement but the error

calculation becomes more complex.

Week and Day Forward

and select Day/Week, not Sunday

Date

1st Week and 16h

48h

When the proper layout guidelines above are observed, the

oscillator should start-up in most circuits in less than one second.

When testing RTC circuits, a common impulse is to apply a scope

probe to the circuit at the X2 pin (oscillator output) and observe

the waveform. DO NOT DO THIS! Although in some cases you may

see a usable waveform, due to the parasitics (usually 10pF to

ground) applied with the scope probe, there will be no useful

information in that waveform other than the fact that the circuit

is oscillating. The X2 output is sensitive to capacitive impedance

so the voltage levels and the frequency will be affected by the

Date Forward

not used

2am

17h

18h

19h

00h

02h

10h

78h

Hour Forward

Month Reverse

Week and Day Reverse

and select Day/Week, not Sunday

Date

October

Last Week and 1Ah

Date Reverse

not used

1Bh

00h

FN6667 Rev 6.00

January 9, 2015

Page 29 of 34

ISL12020M

TABLE 29. DST EXAMPLE (Continued)

VARIABLE VALUE REGISTER

Hour Reverse 1Ch

VALUE

02h

2am

The Enable bit (DSTE) is in the Month forward register, so the BCD

value for that register is altered with the additional bit. The Week

and Day values along with Week/Day vs Date select bit is in the

Week/Day register, so that value is also not straight BCD. Hour

and Month are normal BCD, but the Hour doesn’t use the MIL bit

since Military time PM values are already discretely different

from AM/PM time PM values. The DST reverse setting utilizes the

option to select the last week of the month for October, which

could have 4 or 5 weeks but needs to have the time change on

the last Sunday.

Note that the DSTADJ bit in the status register monitors whether

the DST forward adjustment has happened. When it is “1”, DST

forward has taken place. When it is “0”, then either DST reverse

has happened, or it has been reset either by initial power-up or if

the DSTE bit has been set to “0”.

FN6667 Rev 6.00

January 9, 2015

Page 30 of 34

ISL12020M

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest Rev.

DATE

REVISION

FN6667.6

CHANGE

Updated datasheet applying Intersil’s new standards.

January 9, 2015

On page 1, added bullet (AN1389) to the Related Literature section.

Updated the temperature range from “-40°C to +85°C” to “0°C to +85°C” on page 1 in paragraph 1, on page 5

in the Pin Descriptions table for X2 and X1 pins and on page 11 in paragraph 1.

On page 7, updated Fout by the following:

T

added “0°C to +85°C” to the test conditions

added “-30°C to +85C” and “-40°C to +85°C” rows

Updated Products verbiage to About Intersil verbiage.

October 28, 2011

FN6667.5

On page 1, corrected Figure 1, Typical Application Circuit to show that pin 6/15 are not connected to ground.

On page 4, Ordering Information, added ISL12020MIRZ-EVALZ evaluation board.

On page 5, Pin Descriptions, added Ground pin row, separated VDD pin. Bolded No Connection for the Thermal

Pad.

On page 6, Absolute Maximum Ratings, added shock, vibration.

On page 6, for IDD1 at 3V/5V limits, changed MAX from 7/6µA to 15/14µA.

On page 7, added V

as typical, with Note 17.

DDSR+

On page 8, added Note 17 for V

DDSR+

On page 16, under Oscillator Fail Bit, changed text to: “Oscillator Fail Bit indicates that the oscillator has failed.

The oscillator frequency is either zero or very far from the desired 32.768kHz due to failure, PC board

contamination or mechanical issues.”

On page 16, under Daylight Savings Time Change Bit, removed “DSTADJ can be set to “1” for instances where

the RTC device is initialized during the DST Forward period.” Added “It is read-only and cannot be written. Setting

time during a DST forward period will not set this bit to “1”.”

On page 22, Table 19, changed FDTR column head from <2:0> to <4:0>.

On page 22, Tables 20 and 21, corrected addresses.

On page 28, added Power Supply Considerations section.

April 23, 2010

Added “Latch-up (Tested per JESD-78B; Class 2, Level A)

Added “Maximum Junction Temperature +85°C” on page 6

Added “” on page 1

100mA or 1.5 * VMAX Input” on page 6

Added “Thermal Pad” description to “Pin Descriptions” on page 5. Added “Thermal Pad” label to “Pin

Configuration” on page 5.

Added cross references to page numbers in “Revision History”.

Updated Package Outline Drawing on page 34 to most recent revision. Changes were as follows:

Revised note 8 from:

"Soldering required to PCB for X1 and X2 pads each on a separate floating metal (GRN)."

to:

"Soldering required to PCB for X1 and X2 pads to separate and non-connected metal pads."

Changed Note 2 from:

"These Intersil plastic packaged products employ special material sets, molding compounds and 100% matte

tin plate plus anneal (e3) termination finish. These products do contain Pb but they are RoHS compliant by

exemption 7 (lead in high melt temp solder for internal connections) and exemption 5 (lead in piezoelectric

elements).."

to:

"These Intersil plastic packaged products employ special material sets, molding compounds and 100% matte

tin plate plus anneal (e3) termination finish. These products do contain Pb but they are RoHS compliant by

exemption 7 (lead in high melting temp solder and in piezoelectronic devices) and exemption 5 (lead in glass

of electronic components).."

FN6667 Rev 6.00

January 9, 2015

Page 31 of 34

ISL12020M

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest Rev. (Continued)

DATE

REVISION

FN6667.4

CHANGE

February 11, 2010

Updated Note 2 in Ordering Information table from “These Intersil Pb-free plastic packaged products employ

special Pb-free material sets, molding compounds/die attach materials and 100% matte tin plate plus anneal (e3

termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free

requirements of IPC/JEDEC J STD-020.” to “These Intersil plastic packaged products employ special material

sets, molding compounds and 100% matte tin plate plus anneal (e3) termination finish. These products do contain

Pb but they are RoHS compliant by exemption 7 (lead in high melt temp solder for internal connections) and

exemption 5 (lead in piezoelectric elements). These Intersil RoHS compliant products are compatible with both

SnPb and Pb-free soldering operations. These Intersil RoHS compliant products are MSL classified at Pb-free peak

reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.”

Changed "Pb-Free" in page 1 “Features” and page 4 “Ordering Information” to "RoHS Compliant"

October 22, 2009

Converted to New Intersil Template - Matched front page to match ISL12022M with the exception of pinout

change from SOIC to DFN. Updated ordering information by numbering all notes, setting up links, added MSL

(Moisture Sensitivity Level) note. Updated word "Pinout" to "Pin Configuration". Pin Descriptions updated by

adding descriptive text taken from page 9. Deleted Text Pin Descriptions that were on page 9. Changed Thermal

information from "Tja 85, Tjc 3" To "Tja 40, Tjc 3.5" to match ASYD in Intrepid. Pb-free reflow link now shown in

blue. Updated Notes in Electrical Spec Tables to follow flow of numbers when referenced. Added "boldface

limits..." text in Electrical Spec Conditions to indicate Min and Max over-temp. Bolded all over-temp Min and Max

values. Added Revision History and Products information with links. Updated POD from Rev0 to Rev1 to match

Intrepid. Added Table of Contents.

July 24, 2009

June 22, 2009

January 15, 2009

FN6667.3

Page 1: in the Features section, corrected typo in the second bullet from:

20 Ld DFN Package (for SOIC package see ISL12020M)

To:20 Ld DFN Package (for SOIC package see ISL12022M)

No rev, no date change, no formal review necessary

Changes in Word document attached in Intrepid.

http://intranet.intrepid.intersil.com/Windchill/servlet/WindchillAuthGW/wt.content.ContentHttp/viewContent

/12020M.doc?u8&HttpOperationItem=wt.content.ApplicationData%3A120896672&ContentHolder=ext.isil.p

art.mcol.MCOL%3A120896665

FN6667.2

Added text and equations for Ibat for temp sense ON and for relative accuracy for 1m vs 10m interval

Added text clarifying that no compensation at Vbat<2.7V

Revised entire “DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ)” on page 16

Added Application Example for DST - “Daylight Savings Time (DST) Example” on page 29

Added requirement for Vbat>1.8V in Vbat note.

Added apps circuit to survive Vbat<1.8V

Corrected all occurrences of Alpha tables

Bolded and shaded the COMPENSATION registers in Table 1 to indicate they are not to be overwritten. Also

bolded an advisory in the register sections.

Fixed blank bits in register tables and in text.

Register Table 1: Change default values for compensation to xx's, they are different with each device.

Added Datasheet curves

Added statement to Apps section on crystal handling (in “Layout Considerations” on page 28.)

Applied Intersil standards as follows: Updated lead finish note in “Ordering Information”, added Theta JC note

for thermal resistance, updated over-temp note in Electrical Specification tables, numbered equations that were

not initially, updated POD to latest version, which includes following edits:

Note 6 revised from “Soldering required to PCB for X1 and X2 pads each on a separate floating metal (GRN).”to

“The X1 and X2 pads need to be soldered down to the PCB on separate and electrically isolated land pads.”

Minor dimensions included based on customer input and laid out in new format.

On page 6: IDD1 - Changed Max from 6.5 to 7 for VDD = 5V and 5.5 to 6 for VDD = 3V.

On page 3: Remove DeltaATLSB spec

On page 7: Hysteresis spec - Remove Min and set Typ to 0.05 x VDD

on page 8: tHD:DAT - Change Min from 0 to 20

On page 14: For Table 1, yellow shaded and bolded XTO and ALPHAH registers

On page 21: Eq. 3 - Changed "BETAVALUES" to "BETA VALUES"

On page 29: Eq. 7 - Change "ppmerror" to "ppm error"

On page 26: Changed title for Table 28 from “ALPHA REGISTER” to "ALPHA HOT REGISTER"

On Page 16: Under “Initial AT and DT setting Register (ITRO)” on page 18, changed range value from 62.6ppm

to 62.5ppm.

FN6667 Rev 6.00

January 9, 2015

Page 32 of 34

ISL12020M

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest Rev. (Continued)

DATE

REVISION

FN6667.1

CHANGE

March 28, 2008

Removed Min and Max limits for “Oscillator Initial Accuracy” on page 6. Added Typ of ±2, Replaced Note 11

(Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production

tested.) with Note 9 (Limits should be considered typical and are not production tested).

February 27, 2008

FN6667.0

Initial Release to web

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products

address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com.

You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.

Reliability reports are also available from our website at www.intersil.com/support

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6667 Rev 6.00

January 9, 2015

Page 33 of 34

ISL12020M

Package Outline Drawing

L20.5.5x4.0

20 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

Rev 2, 9/09

0.10

2.10

10X 0.50

0.66

5.5

A

0.300

R0.0750

0.30

B

11

20

10 X 0.50

2X1.30

R0.0750

2.20

PIN #1

INDEX AREA

6

0.10

2X

10

18X 0.50

1

10X 0.25

0.20

2.25

PIN 1

INDEX AREA

TOP VIEW

(4.95)

0.10M C A B 10 x 0.25

4

0.35

2.45

BOTTOM VIEW

(2X 0.20)

10X 0.45

(4.50 )

10X 0.50 10X 0.50

10 X 0.25

10X 0.70

SEE DETAIL "X"

0.10 C

(4.40)

PACKAGE

BOUNDARY

1.30

(2.20)

(0.10)

C

SEATING PLANE

0.08 C

(3.0)

SIDE VIEW

2X 1.50

0.68

0.16

0.30

10X 0.25

2.10

2X 2.45

5

(4.85)

(4.95)

0.2 REF

C

0-0.05

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

Angular ±2°

4. Dimension applies to the metallized terminal and is measured

between 0.015mm and 0.30mm from the terminal tip.

5. Tiebar shown (if present) is a non-functional feature.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

7. No other electrical connection allowed under backside of X1 or X2 areas.

Soldering required to PCB for X1 and X2 pads to separate and

non-connected metal pads.

8.

FN6667 Rev 6.00

January 9, 2015

Page 34 of 34


型号：	ISL12020MIRZ-T
厂家：	RENESAS TECHNOLOGY CORP
描述：	Real Time Clock with Embedded Crystal, ±5ppm Accuracy; DFN20; Temp Range: -40° to 85°C 时钟光电二极管外围集成电路
文件：	总34页 (文件大小：1647K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL12020MIRZ-T [RENESAS]

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