ISL12027IB27Z-T_技术文档

OBSOLETE PRODUCT

DATASHEET

NO RECOMMENDED REPLACEMENT

contact our Technical Support Center at

1-888-INTERSIL or www.intersil.com/tsc

ISL12027, ISL12027A

Real Time Clock/Calendar with EEPROM

FN8232

Rev 9.00

September 23, 2015

The ISL12027 device is a low power real time clock with

timing and crystal compensation, clock/calender, power-fail

indicator, two periodic or polled alarms, intelligent battery

backup switching, CPU Supervisor and integrated 512x8-bit

EEPROM, in 16 Byte per page format.

Features

• Real Time Clock/Calendar

- Tracks Time in Hours, Minutes and Seconds

- Day of the Week, Day, Month and Year

• Two Non-Volatile Alarms

The oscillator uses an external, low-cost 32.768kHz crystal.

The real time clock tracks time with separate registers for

hours, minutes, and seconds. The device has calendar

registers for date, month, year and day of the week. The

calendar is accurate through 2099, with automatic leap year

correction.

- Settable on the Second, Minute, Hour, Day of the Week,

Day, or Month

- Repeat Mode (Periodic Interrupts)

• Automatic Backup to Battery or SuperCap

• On-Chip Oscillator Compensation

The ISL12027 and ISL12027A Power Control Settings are

different. The ISL12027 uses the Legacy Mode Setting, and

the ISL12027A uses the Standard Mode Setting.

- Internal Feedback Resistor and Compensation

Capacitors

- 64 Position Digitally Controlled Trim Capacitor

Applications that have V

> V

will require only the

BAT

DD

- 6 Digital Frequency Adjustment Settings to ±30ppm

ISL12027A. Please refer to“Power Control Operation” on

page 15 for more details. Also, please refer to “I²C

Communications During Battery Backup and LVR Operation”

on page 24 for important details.

• 512x8-Bits of EEPROM

- 16-Byte Page Write Mode (32 total pages)

- 8 Modes of BlockLock™ Protection

- Single Byte Write Capability

Pinouts

• High Reliability

ISL12027, ISL12027A

(8 LD TSSOP)

TOP VIEW

- Data Retention: 50 years

- Endurance: >2,000,000 Cycles Per Byte

• I²C-bus™ Interface

V

BAT

SCL

1

2

8

7

6

5

V

SDA

DD

X1

X2

- 400kHz Data Transfer Rate

GND

RESET

3

4

• 800nA Battery Supply Current

• Package Options

- 8 Ld SOIC and 8 Ld TSSOP Packages

ISL12027, ISL12027A

(8 LD SOIC)

• Pb-Free (RoHS Compliant)

TOP VIEW

Applications

V

X1

X2

• Utility Meters

DD

1

2

8

7

6

5

BAT

• HVAC Equipment

SCL

SDA

RESET

GND

• Audio/Video Components

• Modems

3

4

• Network Routers, Hubs, Switches, Bridges

• Cellular Infrastructure Equipment

• Fixed Broadband Wireless Equipment

• Pagers/PDA

• POS Equipment

• Test Meters/Fixtures

• Office Automation (Copiers, Fax)

• Home Appliances

• Computer Products

• Other Industrial/Medical/Automotive

FN8232 Rev 9.00

Page 1 of 29

September 23, 2015

ISL12027, ISL12027A

Pin Descriptions

PIN NUMBER

SOIC

TSSOP

SYMBOL

BRIEF DESCRIPTION

1

3

X1

The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external

32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source.

2

3

4

5

X2

The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external

32.768kHz quartz crystal.

RESET

RESET. This is a reset signal output. This signal notifies a host processor that the “watchdog” time period

has expired or that the voltage has dropped below a fixed V

threshold. It is an open drain active LOW

TRIP

output. Recommended value for the pull-up resistor is 5k. If unused, connect to ground.

4

5

6

7

GND

SDA

Ground.

Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an

open drain output and may be wire OR’ed with other open drain or open collector outputs.

6

7

8

1

2

SCL

The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on

this pin is always active (not gated).

V

This input provides a backup supply voltage to the device. V

supplies power to the device in the event

BAT

that the V

supply fails. This pin should be tied to ground if not used.

DD

V

Power Supply.

DD

Ordering Information

PART

V

RESET

NUMBER

PART

V

TRIP POINT BSW BIT DEFAULT

VOLTAGE TEMP. RANGE PACKAGE

PKG.

BAT

(Notes 1, 2, 3)

MARKING

(V)

SETTING

BSW = 1

(V)

(°C)

(Pb-Free)

8 Ld SOIC

DWG. #

ISL12027IB27Z

ISL12027IB27AZ

ISL12027IB30AZ

ISL12027IBZ

12027 IB27Z

12027 IB27AZ

12027 IB30AZ

12027 IBZ

V

< V

2.63

2.92

3.09

4.38

4.64

2.63

2.92

3.09

4.38

-40 to +85

M8.15

DD

BAT

M8.15

ISL12027IBAZ

ISL12027IV27Z

ISL12027IV27AZ

ISL12027IV30AZ

12027 IBAZ

2027 I27Z

8 Ld TSSOP M8.173

2027 27AZ

2027 30AZ

2027 IVZ

ISL12027IVZ (No

longer available or

supported)

ISL12027IVAZ (No 2027 IVAZ

longer available or

supported)

V

< V

BSW = 1

BSW = 0

BSW =0

4.64

2.63

-40 to +85

8 Ld TSSOP M8.173

DD

BAT

ISL12027AIB27Z

(Nolongeravailable

or supported)

12027A IB27Z

8 Ld SOIC

M8.15

ISL12027AIV27Z

(Nolongeravailable

or supported)

2027A I27Z

8 Ld TSSOP M8.173

NOTES:

1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-

020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12027, ISL12027A. For more information on MSL please see

techbrief TB363.

FN8232 Rev 9.00

Page 2 of 29

September 23, 2015

ISL12027, ISL12027A

Block Diagram

OSC COMPENSATION

BATTERY

SWITCH

CIRCUITRY

TIME

X1

X2

TIMER

CALENDAR

LOGIC

V

DD

1Hz

FREQUENCY

DIVIDER

32.768kHZ

KEEPING

REGISTERS

(SRAM)

OSCILLATOR

BAT

STATUS

CONTROL/

REGISTERS

(EEPROM)

CONTROL

DECODE

LOGIC

COMPARE

SERIAL

INTERFACE

DECODER

REGISTERS

SCL

SDA

ALARM

(SRAM)

ALARM REGS

(EEPROM)

8

4k

EEPROM

ARRAY

WATCHDOG

TIMER

LOW VOLTAGE

RESET

FN8232 Rev 9.00

Page 3 of 29

September 23, 2015

ISL12027, ISL12027A

Absolute Maximum Ratings

Thermal Information

Voltage on V , V , SCL, SDA, and RESET pins

DD BAT

Thermal Resistance (Typical)



(°C/W)



(°C/W)

JC

JA

(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Voltage on X1 and X2 pins

8 Ld SOIC Package (Notes 5, 6) . . . . .

8 Ld TSSOP Package (Notes 5, 6) . . .

115

140

50

40

(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V

Latchup (Note 4) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±2kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175V

Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and

X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.

5.  is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

6. For  , the “case temp” location is taken at the package top center.

JC

DC Electrical Specifications Unless otherwise noted, V = +2.7V to +5.5V, T = -40°C to +85°C, Typical values are at T = +25°C and

DD

A

V

= 3.3V. Boldface limits apply over the operating temperature range, -40°C to +85°C.

DD

MIN

MAX

SYMBOL

PARAMETER

Main Power Supply

Backup Power Supply

CONDITIONS

(Note 16)

TYP

(Note 16)

UNIT

V

NOTES

V

2.7

1.8

5.5

DD

V

BAT

Electrical Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.

MIN

MAX

SYMBOL

PARAMETER

CONDITIONS

= 2.7V

(Note 16)

TYP

(Note 16)

UNIT

µA

NOTES

I

Supply Current with I²C Active

V

500

7, 8, 9

DD1

DD

BAT

= 5.5V

= 2.7V

= 5.5V

800

µA

I

Supply Current for Non-Volatile

Programming

2.5

mA

µA

7, 8, 9

9

DD2

DD3

3.5

Supply Current for Main

Timekeeping (Low Power Mode)

= V

= 2.7V

= 5.5V

10

SDA

SCL

20

µA

I

Battery Supply Current

V

= 1.8V,

= V = V

800

850

1000

nA

7, 10, 11

BAT

= V

RESET

= 0V

DD

SDA

SCL

V

= 3.0V,

1200

nA

BAT

= V

RESET

DD

SDA

SCL

I

Battery Input Leakage

V

= 5.5V, V

= 1.8V

BAT

-100

1.8

100

2.6

nA

V

BATLKG

DD

V

Mode Threshold

Hysteresis

2.2

30

50

11

TRIP

BAT

TRIP

BAT

V

mV

V/ms

11, 14

12

TRIPHYS

V

Hysteresis

BATHYS

V

Negative Slew rate

DD

10

DD SR-

RESET OUTPUT

V

Output Low Voltage

V

= 5.5V

= 3mA

0.4

V

OL

DD

I

OL

V

= 2.7V

DD

I

= 1mA

OL

I

Output Leakage Current

V

= 5.5V

100

400

nA

LO

DD

= 5.5V

OUT

FN8232 Rev 9.00

Page 4 of 29

September 23, 2015

ISL12027, ISL12027A

Watchdog Timer/Low Voltage Reset Parameters

MIN

TYP

MA

SYMBOL

PARAMETER

CONDITIONS

(Note 16) (Note 5) (Note 16)

UNITS

ns

NOTES

t

V

Detect to RESET LOW

DD

500

13

RPD

t

Power-up Reset Time-Out Delay

100

1.0

250

400

ms

PURST

V

Minimum V

Output

for Valid RESET

DD

V

RVALID

V

ISL12027-4.5A Reset Voltage Level

ISL12027 Reset Voltage Level

ISL12027-3 Reset Voltage Level

ISL12027-2.7A Reset Voltage Level

ISL12027-2.7 Reset Voltage Level

Watchdog Timer Period

4.59

4.33

3.04

2.87

2.58

1.70

725

4.64

4.38

3.09

2.92

2.63

1.75

750

4.69

4.43

3.14

2.97

2.68

1.801

775

V

RESET

V

t

32.768kHz crystal between X1

and X2

s

WDO

ms

225

250

275

t

Watchdog Timer Reset Time-Out

Delay

32.768kHz crystal between X1

and X2

225

250

275

RST

t

I²C Interface Minimum Restart Time

1.2

µs

RSP

EEPROM SPECIFICATIONS

EEPROM Endurance

>2,000,000

50

Cycles

Years

EEPROM Retention

Temperature 75°C

Serial Interface (I²C) Specifications

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

V

SDA, and SCL Input Buffer LOW

Voltage

SBIB = 1 (Under V

mode)

-0.3

0.3xV

DD

V

IL

DD

V

SDA, and SCL Input Buffer HIGH

Voltage

0.7xV

V + 0.3

DD

V

IH

DD

Hysteresis SDA and SCL Input Buffer

Hysteresis

0.05xV

0

DD

V

I

SDA Output Buffer LOW Voltage

Input Leakage Current on SCL

I/O Leakage Current on SDA

I

= 4mA

= 5.5V

0.4

V

OL

LI

OL

V

0.1

10

µA

IN

I

V

LO

TIMING CHARACTERISTICS

f

SCL Frequency

400

50

kHz

ns

SCL

t

Pulse Width Suppression Time at

SDA and SCL Inputs

Any pulse narrower than the max spec

is suppressed.

IN

t

SCL Falling Edge to SDA Output

Data Valid

SCL falling edge crossing 30% of V

until SDA exits the 30% to 70% of V

window.

,

900

ns

AA

DD

t

Time the Bus Must be Free Before SDA crossing 70% of V

during a

DD

1300

BUF

the Start of a New Transmission

STOP condition, to SDA crossing 70%

of V during the following START

DD

condition.

t

Clock LOW Time

Clock HIGH Time

Measured at the 30% of V

Measured at the 70% of V

crossing.

1300

600

ns

LOW

DD

t

HIGH

FN8232 Rev 9.00

Page 5 of 29

September 23, 2015

ISL12027, ISL12027A

Serial Interface (I²C) Specifications (Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

t

START Condition Set-up Time

SCL rising edge to SDA falling edge.

600

ns

SU:STA

Both crossing 70% of V

.

DD

t

START Condition Hold Time

Input Data Set-up Time

Input Data Hold Time

From SDA falling edge crossing 30%

of V to SCL falling edge crossing

600

100

0

ns

HD:STA

DD

70% of V

.

DD

t

From SDA exiting the 30% to 70% of

window, to SCL rising edge

SU:DAT

HD:DAT

SU:STO

HD:STO

V

DD

crossing 30% of V

.

DD

t

From SCL falling edge crossing 70% of

to SDA entering the 30% to 70%

V

DD

of V

window.

DD

t

STOP Condition Set-up Time

From SCL rising edge crossing 70% of

, to SDA rising edge crossing 30%

600

V

DD

of V

.

DD

t

STOP Condition Hold Time for

Read, or Volatile Only Write

From SDA rising edge to SCL falling

edge. Both crossing 70% of V

600

0

ns

.

DD

t

Output Data Hold Time

From SCL falling edge crossing 30% of

, until SDA enters the 30% to 70%

DH

V

DD

of V

window.

DD

t

SDA and SCL Rise Time

SDA and SCL Fall Time

From 30% to 70% of V

From 70% to 30% of V

20 +

0.1xCb

250

ns

R

DD

t

20 +

F

0.1xCb

Cpin

SDA, and SCL Pin Capacitance

Non-Volatile Write Cycle Time

SDA and SCL Rise Time

10

20

pF

ms

ns

t

12

14

15

WC

t

From 30% to 70% of V

From 70% to 30% of V

20 +

0.1xCb

250

R

DD

t

SDA and SCL Fall Time

20 +

0.1xCb

250

400

ns

15

F

Cb

Capacitive Loading of SDA or SCL Total on-chip and off-chip

10

1

pF

15

R

SDA and SCL Bus Pull-up Resistor Maximum is determined by t and t .

k

PU

R

F

Off-chip

For Cb = 400pF, max is about

2k~2.5k.

For Cb = 40pF, max is about

15k~20k

NOTES:

7. RESET Inactive (no reset).

8. V = V x 0.1, V = V

x 0.9, f = 400kHz.

SCL

IL

DD

IH

DD

9. V

= 2.63V (V

must be greater than V

), V

= 0V.

BAT

RESET

DD

RESET

10. Bit BSW = 0 (Standard Mode), ATR = 00h, V

11. Specified at +25°C.

≥1.8V.

BAT

12. In order to ensure proper timekeeping, the V

13. Parameter is not 100% tested.

specification must be followed.

DD SR-

14. t

is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write

WC

sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.

15. These are I²C specific parameters and are not directly tested, however they are used during device testing to validate device specification.

16. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

FN8232 Rev 9.00

Page 6 of 29

September 23, 2015

ISL12027, ISL12027A

Timing Diagrams

t

HD:STO

F

HIGH

LOW

R

SCL

t

SU:DAT

t

HD:DAT

t

SU:STA

SU:STO

t

HD:STA

SDA

(INPUT TIMING)

t

BUF

DH

t

AA

SDA

(OUTPUT TIMING)

FIGURE 1. BUS TIMING

SCL

SDA

8TH BIT OF LAST BYTE

ACK

t

WC

STOP

START

CONDITION

FIGURE 2. WRITE CYCLE TIMING

t

>t

RSP

RSP WDO

t

>t

t

RST

t

<t

RST

RSP WDO

SCL

SDA

RESET

START

STOP START

Note: All inputs are ignored during the active reset period (t

).

RST

FIGURE 3. WATCHDOG TIMING

V

RESET

V

DD

t

PURST

t

RPD

t

F

t

R

RESET

V

RVALID

FIGURE 4. RESET TIMING

FN8232 Rev 9.00

Page 7 of 29

September 23, 2015

ISL12027, ISL12027A

Typical Performance Curves Temperature is +25°C unless otherwise specified.

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

BSW = 0 OR 1

SCL, SDA PULL-UPS = 0V

BSW = 0 OR 1

SCL, SDA PULL-UPS = V

BSW = 0 OR 1

BAT

1.8

2.3

2.8

3.3

3.8

(V)

4.3

4.8

5.3

1.8

2.3

2.8

3.3

3.8

(V)

4.3

4.8

5.3

V

BAT

FIGURE 5. I

vs V

SBIB = 0

FIGURE 6. I

vs V SBIB = 1

BAT,

BAT

BAT,

BAT

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

V

= 5.5V

DD

V

= 3.0V

BAT

V

= 3.3V

DD

-45 -35 -25 -15 -5

5

15 25 35 45 55 65 75 85

-45 -35 -25 -15 -5

5

15 25 35 45 55 65 75 85

TEMPERATURE (°C)

FIGURE 7. I

vs TEMPERATURE

FIGURE 8. I

vs TEMPERATURE

BAT

DD3

4.5

80

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

60

40

20

0

-20

-40

1.8

2.3

2.8

3.3

3.8

(V)

4.3

4.8

5.3

-32 -28 -24 -20 -16 -12 -8 -4

0

4

8

12 16 20 24 28

V

ATR SETTING

DD

FIGURE 9. I

vs V

FIGURE 10. F

vs ATR SETTING

OUT

DD3

DD

FN8232 Rev 9.00

Page 8 of 29

September 23, 2015

ISL12027, ISL12027A

This open drain output requires the use of a pull-up resistor.

The pull-up resistor on this pin must use the same voltage

source as V . The output circuitry controls the fall time of the

DD

output signal with the use of a slope controlled pull-down. The

circuit is designed for 400kHz I²C interface speed.

Description

The ISL12027 device is a Real Time Clock with

clock/calendar, two polled alarms with integrated 512x8

EEPROM configured in 16 Byte per page format, oscillator

compensation, CPU Supervisor (Power on Reset, Low Voltage

Sensing and Watchdog Timer) and battery backup switch.

V

BAT

This input provides a backup supply voltage to the device.

supplies power to the device in the event the V supply

The oscillator uses an external, low-cost 32.768kHz crystal. All

compensation and trim components are integrated on the chip.

This eliminates several external discrete components and a

trim capacitor, saving board area and component cost.

V

BAT

DD

fails. This pin can be connected to a battery, a SuperCap or

tied to ground if not used.

Note that the device is not guaranteed to operate with V

BAT

1.8V. If the battery voltage is expected to drop lower than this

minimum, correct operation of the device, (especially after a

<

The Real-Time Clock keeps track of time with separate

registers for Hours, Minutes and Seconds. The Calendar has

separate registers for Date, Month, Year and Day-of-week. The

calendar is correct through 2099, with automatic leap year

correction.

V

power-down cycle) is not guaranteed.

DD

RESET

The Dual Alarms can be set to any Clock/Calendar value for a

match. For instance, every minute, every Tuesday, or 5:23 AM

on March 21. The alarms can be polled in the Status Register.

There is a repeat mode for the alarms allowing a periodic

interrupt.

The RESET signal output can be used to notify a host

processor that the Watchdog timer has expired or the V

DD

voltage supply has dipped below the V

threshold. It is an

RESET

open drain, active LOW output. Recommended value for the

pull-up resistor is 5k. If unused it can be tied to ground.

The ISL12027 device integrates CPU Supervisory functions

(POR, WDT) and Battery Switch. There is Power-On-Reset

(RESET) output with 250ms delay from power on. It will also

In battery mode, the Watchdog timer function is disabled. The

RESET signal output is asserted LOW when the VDD voltage

supply has dipped below the V

threshold but the RESET

RESET

assert RESET when V goes below the specified threshold.

DD

The V threshold is selectable via VTS2/VTS1/VTS0

trip

signal output will not return HIGH until the device is back to

mode (out of Battery Backup mode) even if the V

V

DD

registers to five (5) preselected levels. There is Watchdog

Timer (WDT) with 3 selectable time-out periods (0.25s, 0.75s

and 1.75s) and disabled setting. The Watchdog Timer

activates the RESET pin when it expires.

voltage is above V

threshold.

RESET

X1, X2

The X1 and X2 pins are the input and output, respectively, of

an inverting amplifier. An external 32.768kHz quartz crystal is

used with the ISL12027 to supply a timebase for the real time

clock. Internal compensation circuitry provides high accuracy

over the operating temperature range from -40°C to +85°C.

This oscillator compensation network can be used to calibrate

the crystal timing accuracy over temperature either during

manufacturing or with an external temperature sensor and

microcontroller for active compensation. X2 is intended to drive

a crystal only, and should not drive any external circuit (Figure

11).

The device offers a backup power input pin. This V

BAT

allows the device to be backed up by battery or SuperCap. The

entire ISL12027 device is fully operational from 2.7V to 5.5V

and the clock/calendar portion of the ISL12027 device remains

fully operational down to 1.8V (Standby Mode).

The ISL12027 device provides 4k bits of EEPROM with

8 modes of BlockLock™ control. The BlockLock™ allows a

safe, secure memory for critical user and configuration data,

while allowing a large user storage area.

NO EXTERNAL COMPENSATION RESISTORS OR

CAPACITORS ARE NEEDED OR ARE RECOMMENDED TO

BE CONNECTED TO THE X1 AND X2 PINS.

Pin Descriptions

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the

device. The input buffer on this pin is always active (not gated).

The pull-up resistor on this pin must use the same voltage

X1

X2

source as V

.

DD

Serial Data (SDA)

SDA is a bi-directional pin used to transfer data into and out of

the device. It has an open drain output and may be wire ORed

with other open drain or open collector outputs. The input

buffer is always active (not gated).

FIGURE 11. RECOMMENDED CRYSTAL CONNECTION

FN8232 Rev 9.00

Page 9 of 29

September 23, 2015

ISL12027, ISL12027A

Real Time Clock Operation

Clock/Control Registers (CCR)

The Real Time Clock (RTC) uses an external 32.768kHz

quartz crystal to maintain an accurate internal representation of

the second, minute, hour, day, date, month and year. The RTC

has leap-year correction. The clock also corrects for months

having fewer than 31 days and has a bit that controls 24 hour

or AM/PM format. When the ISL12027 powers up after the loss

The Control/Clock Registers are located in an area separate

from the EEPROM array and are only accessible following a

slave byte of “1101111x” and reads or writes to addresses

[0000h:003Fh]. The clock/control memory map has memory

addresses from 0000h to 003Fh. The defined addresses are

described in Table 2. Writing to and reading from the undefined

addresses are not recommended.

of both V

and V , the clock will not operate until at least

BAT

DD

one byte is written to the clock register.

CCR Access

Reading the Real Time Clock

The contents of the CCR can be modified by performing a byte

or a page write operation directly to any address in the CCR.

Prior to writing to the CCR (except the status register),

however, the WEL and RWEL bits must be set using a three

step process (see “Writing to the Clock/Control Registers” on

page 14).

The RTC is read by initiating a Read command and specifying

the address corresponding to the register of the Real Time

Clock. The RTC Registers can then be read in a Sequential

Read Mode. Since the clock runs continuously and read takes

a finite amount of time, there is a possibility that the clock could

change during the course of a read operation. In this device,

the time is latched by the read command (falling edge of the

clock on the ACK bit prior to RTC data output) into a separate

latch to avoid time changes during the read operation. The

clock continues to run. Alarms occurring during a read are

unaffected by the read operation.

The CCR is divided into 5 sections. These are:

1. Alarm 0 (8 bytes; non-volatile)

2. Alarm 1 (8 bytes; non-volatile)

3. Control (5 bytes; non-volatile)

4. Real Time Clock (8 bytes; volatile)

5. Status (1 byte; volatile)

Writing to the Real Time Clock

The time and date may be set by writing to the RTC registers.

RTC Register should be written ONLY with Page Write. To

avoid changing the current time by an uncompleted write

operation, write to the all 8 bytes in one write operation. When

writing the RTC registers, the new time value is loaded into a

separate buffer at the falling edge of the clock during the

Acknowledge. This new RTC value is loaded into the RTC

Register by a stop bit at the end of a valid write sequence. An

invalid write operation aborts the time update procedure and

the contents of the buffer are discarded. After a valid write

operation, the RTC will reflect the newly loaded data beginning

with the next “one second” clock cycle after the stop bit is

written. The RTC continues to update the time while an RTC

register write is in progress and the RTC continues to run

during any non-volatile write sequences.

Each register is read and written through buffers. The

non-volatile portion (or the counter portion of the RTC) is

updated only if RWEL is set and only after a valid write

operation and stop bit. A sequential read or page write

operation provides access to the contents of only one section

of the CCR per operation. Access to another section requires a

new operation. A read or write can begin at any address in the

CCR.

It is not necessary to set the RWEL bit prior to writing the

status register. Section 5 (status register) supports a single

byte read or write only. Continued reads or writes from this

section terminates the operation.

The state of the CCR can be read by performing a random

read at any address in the CCR at any time. This returns the

contents of that register location. Additional registers are read

by performing a sequential read. The read instruction latches

all Clock registers into a buffer, so an update of the clock does

not change the time being read. A sequential read of the CCR

will not result in the output of data from the memory array. At

the end of a read, the master supplies a stop condition to end

the operation and free the bus. After a read of the CCR, the

address remains at the previous address +1 so the user can

execute a current address read of the CCR and continue

reading the next Register.

Accuracy of the Real Time Clock

The accuracy of the Real Time Clock depends on the accuracy

of the quartz crystal that is used as the time base for the RTC.

Since the resonant frequency of a crystal is temperature

dependent, the RTC performance will also be dependent upon

temperature. The frequency deviation of the crystal is a

function of the turnover temperature of the crystal from the

crystal’s nominal frequency. For example, a >20ppm frequency

deviation translates into an accuracy of >1 minute per month.

These parameters are available from the crystal manufacturer.

Intersil’s RTC family provides on-chip crystal compensation

networks to adjust load-capacitance to tune oscillator

frequency from -34ppm to +80ppm when using a 12.5pF load

crystal. For more detailed information see “Application Section”

on page 22.

Real Time Clock Registers (Volatile)

SC, MN, HR, DT, MO, YR: Clock/Calendar Registers

These registers depict BCD representations of the time. As

such, SC (Seconds) and MN (Minutes) range from 00 to 59,

HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or 0

FN8232 Rev 9.00

Page 10 of 29

September 23, 2015

ISL12027, ISL12027A

to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is 1 to

12, YR (Year) is 0 to 99.

OSCF: Oscillator Fail Indicator

This bit is set to “1” if the oscillator is not operating, or is

operating but has clock jitter which does not affect the

accuracy of RTC counting. The bit is set to “0” if the oscillator is

functioning and does not have clock jitter. This bit is read only,

and is set/reset by hardware.

DW: Day of the Week Register

This register provides a Day of the Week status and uses three

bits DY2 to DY0 to represent the seven days of the week. The

counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-… The

assignment of a numerical value to a specific day of the week

is arbitrary and may be decided by the system software

designer. The default value is defined as ‘0’.

RWEL: Register Write Enable Latch

This bit is a volatile latch that powers up in the LOW (disabled)

state. The RWEL bit must be set to “1” prior to any writes to the

Clock/Control Registers. Writes to RWEL bit do not cause a

non-volatile write cycle, so the device is ready for the next

operation immediately after the stop condition. A write to the

CCR requires both the RWEL and WEL bits to be set in a

specific sequence.

Y2K: Year 2000 Register

Can have value 19 or 20. As of the date of the introduction of

this device, there would be no real use for the value 19 in a

true real time clock, however.

24 Hour Time

WEL: Write Enable Latch

If the MIL bit of the HR register is 1, the RTC uses a 24-hour

format. If the MIL bit is 0, the RTC uses a 12-hour format and

H21 bit functions as an AM/PM indicator with a ‘1’,

representing PM. The clock defaults to standard time with H21

= 0.

The WEL bit controls the access to the CCR during a write

operation. This bit is a volatile latch that powers up in the LOW

(disabled) state. While the WEL bit is LOW, writes to the CCR

address will be ignored, although acknowledgment is still

issued. The WEL bit is set by writing a “1” to the WEL bit and

zeroes to the other bits of the Status Register. Once set, WEL

remains set until either reset to 0 (by writing a “0” to the WEL

bit and zeroes to the other bits of the Status Register) or until

the part powers up again. Writes to WEL bit do not cause a

non-volatile write cycle, so the device is ready for the next

operation immediately after the stop condition.

Leap Years

Leap years add the day February 29 and are defined as those

years that are divisible by 4.

Status Register (SR) (Volatile)

The Status Register is located in the CCR memory map at

address 003Fh. This is a volatile register only and is used to

control the WEL and RWEL write enable latches, read power

status and two alarm bits. This register is separate from both

the array and the Clock/Control Registers (CCR).

RTCF: Real Time Clock Fail Bit

This bit is set to a “1” after a total power failure. This is a read

only bit that is set by hardware (ISL12027 internally) when the

device powers up after having lost all power to the device (both

TABLE 1. STATUS REGISTER (SR)

V

and V

go to 0V). The bit is set regardless of whether

DD

BAT

or V is applied first. The loss of only one of the

BAT

ADDR

003Fh BAT AL1 AL0 OSCF

Default

7

6

5

4

3

0

2

1

0

DD

supplies does not set the RTCF bit to “1”. On power up after a

total power failure, all registers are set to their default states

and the clock will not increment until at least one byte is written

to the clock register. The first valid write to the RTC section

after a complete power failure resets the RTCF bit to “0”

(writing one byte is sufficient).

RWEL WEL RTCF

0

1

BAT: Battery Supply

This bit set to “1” indicates that the device is operating from

, not V . It is a read-only bit and is set/reset by hardware

(ISL12027 internally). Once the device begins operating from

, the device sets this bit to “0”.

V

BAT

DD

Unused Bits:

Bit 3 in the SR is not used, but must be zero. The Data Byte

output during a SR read will contain a zero in this bit location.

V

DD

AL1, AL0: Alarm Bits

These bits announce if either alarm 0 or alarm 1 match the real

time clock. If there is a match, the respective bit is set to ‘1’.

The falling edge of the last data bit in a SR Read operation

resets the flags. Note: Only the AL bits that are set when an SR

read starts will be reset. An alarm bit that is set by an alarm

occurring during an SR read operation will remain set after the

read operation is complete.

FN8232 Rev 9.00

Page 11 of 29

September 23, 2015

ISL12027, ISL12027A

TABLE 2. CLOCK/CONTROL MEMORY MAP

BIT

REG

NAME

RANG

E

ADDR.

003F

0037

0036

0035

0034

0033

0032

0031

0030

0014

0013

0012

0011

0010

000F

000E

000D

000C

000B

000A

0009

0008

0007

0006

0005

0004

0003

0002

0001

0000

TYPE

7

BAT

0

6

AL1

0

5

AL0

Y2K21

0

4

OSCF

Y2K20

0

3

0

2

RWEL

0

1

WEL

0

RTCF

Y2K10

DY0

Y10

G10

D10

H10

M10

S10

VTS0

DTR0

ATR0

0

Status

SR

01h

20h

00h

01h

00h

4Xh

00h

18h

20h

00h

01h

20h

00h

01h

00h

0Xh

00h

18h

20h

00h

RTC

(SRAM)

Y2K

DW

YR

Y2K13

0

19/20

0-6

0

DY2

Y12

G12

D12

H12

M12

S12

VTS2

DTR2

ATR2

0

DY1

Y11

G11

D11

H11

M11

S11

VTS1

DTR1

ATR1

0

Y23

0

Y22

0

Y21

0

Y20

G20

D20

H20

M20

S20

0

Y13

G13

D13

H13

M13

S13

0

0-99

1-12

1-31

0-23

0-59

MO

DT

0

D21

H21

M21

S21

0

HR

MIL

0

MN

M22

S22

BSW

0

SC

0

Control

(EEPROM

)

PWR

DTR

ATR

INT

BL

SBIB

0

ATR5

AL0E

BP0

ATR4

0

ATR3

0

IM

BP2

0

AL1E

BP1

0

WD1

WD0

0

Alarm1

(EEPROM

)

Y2K1

A1Y2K21 A1Y2K20 A1Y2K13

0

A1Y2K10 19/20

DWA1 EDW1

YRA1

0

DY2

DY1

DY0

0-6

Unused - Default = RTC Year value (No EEPROM) - Future expansion

MOA1 EMO1

0

A1G20

A1D20

A1H20

A1M20

A1S20

A1G13

A1D13

A1H13

A1M13

A1S13

A1G12

A1D12

A1H12

A1M12

A1S12

0

A1G11

A1D11

A1H11

A1M11

A1S11

0

A1G10

A1D10

A1H10

A1M10

A1S10

1-12

1-31

0-23

0-59

00h

20h

00h

20h

00h

DTA1

EDT1

0

A1D21

A1H21

A1M21

A1S21

HRA1 EHR1

MNA1 EMN1

SCA1 ESC1

0

A1M22

A1S22

0

Alarm0

(EEPROM

)

Y2K0

0

A0Y2K21 A0Y2K20 A0Y2K13

A0Y2K10 19/20

DWA0 EDW0

YRA0

0

DY2

DY1

DY0

0-6

Unused - Default = RTC Year value (No EEPROM) - Future expansion

MOA0 EMO0

0

A0G20

A0D20

A0H20

A0M20

A0S20

A0G13

A0D13

A0H13

A0M13

A0S13

A0G12

A0D12

A0H12

A0M12

A0S12

A0G11

A0D11

A0H11

A0M11

A0S11

A0G10

A0D10

A0H10

A0M10

A0S10

1-12

1-31

0-23

0-59

00h

DTA0

EDT0

A0D21

A0H21

A0M21

A0S21

HRA0 EHR0

MNA0 EMN0

SCA0 ESC0

0

A0M22

A0S22

NOTE: (Shaded cells indicate that NO other value is to be written to that bit. X indicates the bits are set according to the product variation, see device

“Ordering Information” on page 2).

FN8232 Rev 9.00

Page 12 of 29

September 23, 2015

ISL12027, ISL12027A

Six analog trimming bits, ATR0 to ATR5, are provided in order

to adjust the on-chip load capacitance value for frequency

compensation of the RTC. Each bit has a different weight for

capacitance adjustment. For example, using a Citizen CFS-

206 crystal with different ATR bit combinations provides an

estimated ppm adjustment range from -34ppm to +80ppm to

the nominal frequency compensation.

Alarm Registers (Non-Volatile)

Alarm0 and Alarm1

The alarm register bytes are set up identical to the RTC

register bytes, except that the MSB of each byte functions as

an enable bit (enable = “1”). These enable bits specify which

alarm registers (seconds, minutes, etc.) are used to make the

comparison. Note that there is no alarm byte for year.

X1

The alarm function works as a comparison between the alarm

registers and the RTC registers. As the RTC advances, the

alarm will be triggered once a match occurs between the alarm

registers and the RTC registers. Any one alarm register,

multiple registers, or all registers can be enabled for a match.

See “Device Operation” on page 14 and “Application Section”

on page 22 for more information.

C

X1

X2

CRYSTAL

OSCILLATOR

X2

Control Registers (Non-Volatile)

FIGURE 12. DIAGRAM OF ATR

The Control Bits and Registers described in the following

section are non-volatile.

The effective on-chip series load capacitance, C

, ranges

LOAD

from 4.5pF to 20.25pF with a mid-scale value of 12.5pF

(default). C is changed via two digitally controlled

BL Register

LOAD

capacitors, C and C , connected from the X1 and X2 pins

BP2, BP1, BP0 - Block Protect Bits

X1

X2

to ground (see Figure 12). The value of C and C is given

Equation 1:

X1

X2

The Block Protect Bits, BP2, BP1 and BP0, determine which

blocks of the array are write protected. A write to a protected

block of memory is ignored. The block protect bits will prevent

write operations to one of eight segments of the array. The

partitions are described in Table 3.

C

= 16  b5 + 8  b4 + 4  b3 + 2  b2 + 1  b1 + 0.5  b0 + 9pF

X

(EQ. 1)

The effective series load capacitance is the combination of C

X1

TABLE 3.

and C

:

X2

PROTECTED ADDRESSES

1

----------------------------------

C

=

LOAD

ISL12027

None (Default)

180 – 1FF

ARRAY LOCK

None

1





---------- ----------

+





C

X2

X1

(EQ. 2)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16  b5 + 8  b4 + 4  b3 + 2  b2 + 1  b1 + 0.5  b0 + 9

Upper 1/4









h

-----------------------------------------------------------------------------------------------------------------------------

C

=

pF

LOAD

2

100 – 1FF

Upper 1/2

h

For example, C

(ATR = 00000) = 12.5pF,

LOAD

000 – 1FF

Full Array

h

C

(ATR = 100000) = 4.5pF, and

(ATR = 011111) = 20.25pF. The entire range for the

series combination of load capacitance goes from 4.5pF to

20.25pF in 0.25pF steps. Note that these are typical values.

LOAD

000 – 03F

h

First 4 Pages

First 8 Pages

First 16 Pages

Full Array

LOAD

000 – 07F

h

000 – 0FF

h

000 – 1FF

h

DTR Register - DTR2, DTR1, DTR0: Digital Trimming

Register

The digital trimming Bits DTR2, DTR1 and DTR0 adjust the

number of counts per second and average the ppm error to

achieve better accuracy.

Oscillator Compensation Registers

There are two trimming options.

• ATR. Analog Trimming Register

• DTR. Digital Trimming Register

DTR2 is a sign bit. DTR2 = 0 means frequency compensation

is >0. DTR2 = 1 means frequency compensation is <0.

These registers are non-volatile. The combination of analog

and digital trimming can give up to -64 to +110ppm of total

adjustment.

DTR1 and DTR0 are scale bits. DTR1 gives 10ppm adjustment

and DTR0 gives 20ppm adjustment.

A range from -30ppm to +30ppm can be represented by using

the three DTR bits.

ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,

ATR0: Analog Trimming Register

FN8232 Rev 9.00

Page 13 of 29

September 23, 2015

ISL12027, ISL12027A

TABLE 4. DIGITAL TRIMMING REGISTERS

TABLE 5.

VTS0

DTR REGISTER

VTS2

VTS1

V

RESET

ESTIMATED FREQUENCY

PPM

DTR2

DTR1

DTR0

0

1

0

1

0

1

0

1

0

4.64V

4.38V

3.09V

2.92V

2.63V

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+10

+20

+30

0

In battery mode, the RESET signal output is asserted LOW

when the VDD voltage supply has dipped below the V

RESET

-10

-20

-30

threshold, but the RESET signal output will not return HIGH

until the device is back to V mode even the V voltage is

DD

above V

threshold.

RESET

Device Operation

PWR Register: SBIB, BSW, VTS2, VTS1, VTS0

SBIB: Serial Bus Interface (Enable)

Writing to the Clock/Control Registers

Changing any of the bits of the clock/control registers requires

the following steps:

The serial bus can be disabled in battery backup mode by

setting this bit to “1”. This will minimize power drain on the

battery. The Serial Interface can be enabled in battery backup

mode by setting this bit to “0” (default is “0”). See “Power

Control Operation” on page 15 and “RESET” on page 9.

1. Write a 02h to the Status Register to set the Write Enable

Latch (WEL). This is a volatile operation, so there is no

delay after the write. (Operation preceded by a start and

ended with a stop).

BSW: Power Control Bit

2. Write a 06h to the Status Register to set both the Register

Write Enable Latch (RWEL) and the WEL bit. This is also a

volatile cycle. The zeros in the data byte are required.

(Operation proceeded by a start and ended with a stop).

The Power Control bit, BSW, determines the conditions for

switching between V

options:

and Backup Battery. There are two

DD

Option 1. Standard: Set “BSW = 0” (default for ISL12027A)

Write all 8 bytes to the RTC registers, or one byte to the SR, or

one to five bytes to the control registers. This sequence starts

with a start bit, requires a slave byte of “11011110” and an

address within the CCR and is terminated by a stop bit. A write

to the EEPROM registers in the CCR will initiate a non-volatile

write cycle and will take up to 20ms to complete. A write to the

RTC registers (SRAM) will require much shorter cycle time (t =

Option 2. Legacy /Default Mode: Set “BSW = 1” (default

for ISL12027)

See “Power Control Operation” on page 15 for more details.

Also see “I²C Communications During Battery Backup and

LVR Operation” on page 24 for important details.

t

). Writes to undefined areas have no effect. The RWEL bit

BUF

VTS2, VTS1, VTS0: V

Select Bits

RESET

The ISL12027 is shipped with a default V

is reset by the completion of a write to the CCR, so the

sequence must be repeated to again initiate another change to

the CCR contents. If the sequence is not completed for any

reason (by sending an incorrect number of bits or sending a

start instead of a stop, for example) the RWEL bit is not reset

and the device remains in an active mode. Writing all zeros to

the status register resets both the WEL and RWEL bits. A read

operation occurring between any of the previous operations

will not interrupt the register write operation.

threshold

DD

(V

) per the “Ordering Information” table on page 2. This

RESET

register is a non-volatile with no protection, therefore any

writes to this location can change the default value from that

marked on the package. If not changed with a non-volatile

write, this value will not change over normal operating and

storage conditions. However, ISL12027 has four (4) additional

selectable levels to fit the customers application. Levels are:

4.64V (default), 4.38V, 3.09V, 2.92V and 2.63V. The V

selection is via 3 bits (VTS2, VTS1 and VTS0). See Table 5.

RESET

Alarm Operation

Since the alarm works as a comparison between the alarm

registers and the RTC registers, it is ideal for notifying a host

processor of a particular time event and trigger some action as a

result. The host can be notified by polling the Status Register (SR)

Alarm bits. These two volatile bits (AL1 for Alarm 1 and AL0 for

Alarm 0), indicate if an alarm has happened. The AL1 and AL0

bits in the status register are reset by the falling edge of the eighth

clock of status register read.

Care should be taken when changing the V select bits. If

RESET

the V

voltage selected is higher than V , then the

DD

RESET

device will go into RESET and unless V

is increased, the

DD

device will no longer be able to communicate using the I²C

bus.

FN8232 Rev 9.00

Page 14 of 29

September 23, 2015

ISL12027, ISL12027A

There are two alarm operation modes: Single Event and

periodic Interrupt Mode:

the DWA0 register is being set, then the code can start with

a multiple byte write beginning at address 0006h, and then

write 3 bytes ending with the SCA1 register as follows:

1. Single Event Mode is enabled by setting the AL0E or AL1E

bit to “1”, the IM bit to “0”, and disabling the frequency

output. This mode permits a one-time match between the

alarm registers and the RTC registers. Once this match

occurs, the AL0 or AL1 bit is set to “1”. Once the AL0 or AL1

bit is read, this will automatically reset it. Both Alarm

registers can be set at the same time to trigger alarms.

Polling the SR will reveal which alarm has been set.

Addr Name

0006h DWA0

0007h Y2K0

0008h SCA1

If the Alarm1 is used, SCA1 would need to have the correct

data written.

Power Control Operation

2. Interrupt Mode (or “Pulsed Interrupt Mode” or PIM) is

enabled by setting the AL0E or AL1E bit to “1” the IM bit to

“1”, and disabling the frequency output. If both AL0E and

AL1E bits are set to 1, then only the AL0E PIM alarm will

function (AL0E overrides AL1E). This means that once the

interrupt mode alarm is set, it will continue to alarm for each

occurring match of the alarm and present time. This mode

is convenient for hourly or daily hardware interrupts in

microcontroller applications such as security cameras or

utility meter reading. Interrupt Mode CANNOT be used for

general periodic alarms, however, since a specific time

period cannot be programmed for interrupt, only matches to

a specific time of day. The interrupt mode is only stopped by

disabling the IM bit or the Alarm Enable bits.

The power control circuit accepts a V

and a V

input.

BAT

DD

Many types of batteries can be used with Intersil RTC

products. For example, 3.0V or 3.6V Lithium batteries are

appropriate, and battery sizes are available that can power an

Intersil RTC device for up to 10 years. Another option is to use

a SuperCap for applications where V

a month. See “Application Section” on page 22 for more

information.

is interrupted for up to

DD

There are two options for setting the change-over conditions

from V

to Battery backup mode. The BSW bit in the PWR

DD

register controls this operation.

Option 1 - Standard Mode: Set “BSW = 0” (default for

ISL12027A)

Writing to the Alarm Registers

The Alarm Registers are non-volatile but require special

attention to insure a proper non-volatile write takes place.

Specifically, byte writes to individual registers are good for all

but registers 0006h and 0000Eh, which are the DWA0 and

DWA1 registers, respectively. Those registers will require a

special page write for non-volatile storage. The recommended

page write sequences are as follows:

Option 2 - Legacy/Default Mode: Set “BSW = 1” (default for

ISL12027)

TABLE 6. V

TRIP POINT WITH DIFFERENT BSW SETTING

BAT

V

TRIP

BAT

BSW BIT

POINT (V)

POWER CONTROL SETTING

0

1

2.2

0

Standard Mode (ISL12027A)

Legacy Mode (ISL12027)

1. 16-byte page writes: The best way to write or update the

Alarm Registers is to perform a 16-byte write beginning at

address 0001h (MNA0) and wrapping around and ending at

address 0000h (SCA0). This will insure that non-volatile

storage takes place. This means that the code must be

designed so that the Alarm0 data is written starting with

Minutes register, and then all the Alarm1 data, with the last

byte being the Alarm0 Seconds (the page ends at the

Alarm1 Y2k register and then wraps around to address

0000h).

Note that applications that have V_BAT> V_DDwill require

theISL12027A (standard mode) for proper start-up. The I²C

bus may or may not be operational during battery backup; that

function is controlled by the SBIB bit. That operation is covered

after the power control section.

OPTION 1 - STANDARD POWER CONTROL MODE

(ISL12027A)

Alternatively, the 16-byte page write could start with

address 0009h, wrap around and finish with address

0008h. Note that any page write ending at address 0007h

or 000Fh (the highest byte in each Alarm) will not trigger a

non-volatile write, so wrapping around or overlapping to

the following Alarm's Seconds register is advised.

In the Standard mode, the supply will switch over to the battery

when V drops below V

or V , whichever is lower. In

BAT

DD

TRIP

this mode, accidental operation from the battery is prevented

since the battery backup input will only be used when the V

supply is shut off.

DD

To select Option 1, BSW bit in the Power Register must be set

to “BSW = 0”. A description of power switchover follows.

2. Other non-volatile writes: It is possible to do writes of less

than an entire page, but the final byte must always be

addresses 0000h through 0004h or 0008h though 000Ch to

trigger a non-volatile write. Writing to those blocks of 5 bytes

sequentially, or individually, will trigger a non-volatile write.

If the DWA0 or DWA1 registers need to be set, then enough

bytes will need to be written to overlap with the other Alarm

register and trigger the non-volatile write. For Example, if

Standard Mode Power Switchover

• Normal Operating Mode (V ) to Battery Backup Mode

DD

(V

)

BAT

FN8232 Rev 9.00

Page 15 of 29

September 23, 2015

ISL12027, ISL12027A

To transition from the V

to V

mode, both of the

decreases, the device will no longer operate from V . If that

DD

BAT

following conditions must be met:

is the situation on initial power-up, then I²C communication

may not be possible. For these applications, the ISL12027A

should be used.

• Condition 1:

V

< V

- V

DD

BAT BATHYS

where V

 50mV

BATHYS

To select the Option 2, BSW bit in the Power Register must

be set to “BSW = 1”.

• Condition 2:

V

< V

DD

TRIP

• Normal Mode (V ) to Battery Backup Mode (V

)

where V

 2.2V

DD

BAT

To transition from the V

to V mode, the following

BAT

• Battery Backup Mode (V

) to Normal Mode (V

)

DD

BAT

conditions must be met:

V < V - V

DD

The ISL12027 device will switch from the V

when one of the following conditions occurs:

to V mode

DD

BAT

BATHYS

• Condition 1:

• Battery Backup Mode (V

) to Normal Mode (V

)

BAT

DD

V

> V

+ V

DD

BAT BATHYS

The device will switch from the V

following condition occurs:

to V

mode when the

where V

 50mV

BAT

DD

BATHYS

• Condition 2:

V

> V

+ V

DD

TRIP TRIPHYS

V

> V

+V

DD

BAT BATHYS

where V

 30mV

TRIPHYS

The Legacy Mode power control conditions are illustrated in

Figure 15.

There are two discrete situations that are possible when

using Standard Mode: V

< V

and V

> V

.

BAT

TRIP

BAT

TRIP

V

DD

These two power control situations are illustrated in

Figures 13 and 14.

VOLTAGE

ON

V

BAT

IN

OFF

BATTERY BACKUP

MODE

V

DD

V

FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE

TRIP

2.2V

1.8V

V

BAT

Power On Reset

V

+ V

BATHYS

Application of power to the ISL12027 activates a Power On

Reset Circuit that pulls the RESET pin active. This signal

provides several benefits.

BAT

V

- V

BATHYS

BAT

FIGURE 13. BATTERY SWITCHOVER WHEN V

< V

TRIP

BAT

• It prevents the system microprocessor from starting to

operate with insufficient voltage.

BATTERY BACKUP

MODE

• It prevents the processor from operating prior to

stabilization of the oscillator.

V

DD

V

• It allows time for an FPGA to download its configuration

prior to initialization of the circuit.

BAT

3.0V

2.2V

V

TRIP

• It prevents communication to the EEPROM, greatly

reducing the likelihood of data corruption on power-up.

V

TRIP

V

+ V

TRIP

TRIPHYS

When V

exceeds the device V

threshold value for

RESET

DD

typically 250ms the circuit releases RESET, allowing the

system to begin operation. Recommended slew rate is

between 0.2V/ms and 50V/ms.

FIGURE 14. BATTERY SWITCHOVER WHEN V

> V

TRIP

BAT

OPTION 2 -LEGACY POWER CONTROL MODE

(ISL12027 DEFAULT)

NOTE: If the V

voltage drops below the data sheet

BAT

minimum of 1.8V and the V power cycles to 0V then back

DD

The Legacy Mode follows conditions set in X1226 products.

In this mode, switching from V to V is simply done by

comparing the voltages and the device operates from

to V voltage, then the RESET output may stay low and the

DD

BAT

I²C communications will not operate. The V

and V

DD

BAT

power will need to be cycled to 0V together to allow normal

operation again.

whichever is the higher voltage. Care should be taken when

changing from Normal to Legacy Mode. If the V

voltage is

BAT

higher than V , then the device will enter battery back up

DD

and unless the battery is disconnected or the voltage

FN8232 Rev 9.00

Page 16 of 29

September 23, 2015

ISL12027, ISL12027A

threshold. The RESET signal output will not return HIGH

until the device is back to VDD mode even if the VDD

Watchdog Timer Operation

The Watchdog timer timeout period is selectable. By writing

a value to WD1 and WD0, the Watchdog timer can be set to

3 different time out periods or off. When the Watchdog timer

is set to off, the watchdog circuit is configured for low power

operation (see Table 7).

voltage is above V

threshold.

RESET

Serial Communication

Interface Conventions

The device supports the I²C Protocol.

TABLE 7.

Clock and Data

WD1

WD0

DURATION

Data states on the SDA line can change only during SCL

LOW. SDA state changes during SCL HIGH are reserved for

indicating start and stop conditions. (see Figure 16).

1

0

1

0

1

0

disabled

250ms

750ms

1.75s

Start Condition

All commands are preceded by the start condition, which is a

HIGH to LOW transition of SDA when SCL is HIGH. The

device continuously monitors the SDA and SCL lines for the

start condition and will not respond to any command until

this condition has been met. (see Figure 17).

Watchdog Timer Restart

The Watchdog Timer is started by a falling edge of SDA

when the SCL line is high (START condition). The start

signal restarts the watchdog timer counter, resetting the

period of the counter back to the maximum. If another

START fails to be detected prior to the Watchdog timer

expiration, then the RESET pin becomes active for one reset

time out period. In the event that the start signal occurs

during a reset time out period, the start will have no effect.

When using a single START to refresh Watchdog timer, a

STOP condition should be followed to reset the device back

to stand-by mode.(see Figure 3).

Stop Condition

All communications must be terminated by a stop condition,

which is a LOW to HIGH transition of SDA when SCL is

HIGH. The stop condition is also used to place the device

into the Standby power mode after a read sequence. A stop

condition can only be issued after the transmitting device

has released the bus. (see Figure 17).

Acknowledge

In battery mode, the Watchdog timer function is disabled.

Acknowledge is a software convention used to indicate

successful data transfer. The transmitting device, either

master or slave, will release the bus after transmitting 8-bits.

During the ninth clock cycle, the receiver will pull the SDA

line LOW to acknowledge that it received the 8-bits of data.

Refer to Figure 18.

Low Voltage Reset (LVR) Operation

When a power failure occurs, a voltage comparator

compares the level of the V line versus a preset threshold

DD

voltage (V

), then generates a RESET pulse if it is

RESET

below V

. The reset pulse will timeout 250ms after the

RESET

V

line rises above V

. If the V remains below

RESET DD

DD

The device will respond with an acknowledge after

recognition of a start condition and if the correct Device

Identifier and Select bits are contained in the Slave Address

Byte. If a write operation is selected, the device will respond

with an acknowledge after the receipt of each subsequent

8-bit word. The device will not acknowledge if the slave

address byte is incorrect.

, then the RESET output will remain asserted low.

RESET

Power-up and power-down waveforms are shown in

Figure 4. The LVR circuit is to be designed so the RESET

signal is valid down to V = 1.0V.

DD

When the LVR signal is active, unless the part has been

switched into the battery mode, the completion of an

in-progress non-volatile write cycle is unaffected, allowing a

non-volatile write to continue as long as possible (down to

the Reset Valid Voltage). The LVR signal, when active, will

terminate any in-progress communications to the device and

prevents new commands from disrupting any current write

operations. See “I²C Communications During Battery

Backup and LVR Operation” on page 24.

In the read mode, the device will transmit 8-bits of data,

release the SDA line, then monitor the line for an

acknowledge. If an acknowledge is detected and no stop

condition is generated by the master, the device will continue

to transmit data. The device will terminate further data

transmissions if an acknowledge is not detected. The master

must then issue a stop condition to return the device to

Standby mode and place the device into a known state.

In battery mode, the RESET signal output is asserted LOW

when the VDD voltage supply has dipped below the V

RESET

FN8232 Rev 9.00

Page 17 of 29

September 23, 2015

ISL12027, ISL12027A

SCL

SDA

DATA STABLE

DATA CHANGE

DATA STABLE

FIGURE 16. VALID DATA CHANGES ON THE SDA BUS

SCL

SDA

START

STOP

FIGURE 17. VALID START AND STOP CONDITIONS

SCL FROM

MASTER

8

9

1

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER

DEVICE IDENTIFIER

SLAVE ADDRESS BYTE

BYTE 0

ARRAY

CCR

1

0

1

0

1

0

1

R/W

A8

WORD ADDRESS 1

BYTE 1

0

WORD ADDRESS 0

BYTE 2

A7

D7

A6

D6

A5

D5

A4

D4

A3

D3

A2

D2

A1

D1

A0

D0

DATA BYTE

BYTE 3

FIGURE 19. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (64 BYTE PAGES)

FN8232 Rev 9.00

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September 23, 2015

ISL12027, ISL12027A

A write to a protected block of memory is ignored, but will still

receive an acknowledge. At the end of the write command, the

ISL12027 will not initiate an internal write cycle, and will

continue to ACK commands.

Device Addressing

Following a start condition, the master must output a Slave

Address Byte. The first 4 bits of the Slave Address Byte specify

access to either the EEPROM array or to the CCR. Slave bits

‘1010’ access the EEPROM array. Slave bits ‘1101’ access the

CCR.

Byte writes to all of the non-volatile registers are allowed,

except the DWAn registers which require multiple byte writes

or page writes to trigger non-volatile writes. See “Device

Operation” on page 14 for more information.

When shipped from the factory, EEPROM array is

UNDEFINED, and should be programmed by the customer to a

known state.

Page Write

The ISL12027 has a page write operation. It is initiated in the

same manner as the byte write operation; but instead of

terminating the write cycle after the first data byte is

transferred, the master can transmit up to 15 more bytes to the

memory array and up to 7 more bytes to the clock/control

registers. The RTC registers require a page write (8 bytes),

individual register writes are not allowed. (Note: Prior to writing

to the CCR, the master must write a 02h, then 06h to the status

register in two preceding operations to enable the write

operation. See “Writing to the Clock/Control Registers” on

page 14”)

Bit 3 through Bit 1 of the slave byte specify the device select

bits. These are set to ‘111’.

The last bit of the Slave Address Byte defines the operation to

be performed. When this R/W bit is a one, then a read

operation is selected. A zero selects a write operation. Refer to

Figure 19.

After loading the entire Slave Address Byte from the SDA bus,

the ISL12027 compares the device identifier and device select

bits with ‘1010111’ or ‘1101111’. Upon a correct compare, the

device outputs an acknowledge on the SDA line.

After the receipt of each byte, the ISL12027 responds with an

acknowledge, and the address is internally incremented by

one. The address pointer remains at the last address byte

written. When the counter reaches the end of the page, it “rolls

over” and goes back to the first address on the same page.

This means that the master can write 16 bytes to a memory

array page or 8 bytes to a CCR section starting at any location

on that page. For example, if the master begins writing at

location 10 of the memory and loads 15 bytes, then the first 6

bytes are written to addresses 10 through 15, and the last 6

bytes are written to columns 0 through 5. Afterwards, the

address counter would point to location 6 on the page that was

just written. If the master supplies more than the maximum

bytes in a page, then the previously loaded data is over-written

by the new data, one byte at a time. Refer to Figure 21.The

master terminates the Data Byte loading by issuing a stop

condition, which causes the ISL12027 to begin the non-volatile

write cycle. As with the byte write operation, all inputs are

disabled until completion of the internal write cycle. Refer to

Figure 22 for the address, acknowledge and data transfer

sequence.

Following the Slave Byte is a 2 byte word address. The word

address is either supplied by the master device or obtained

from an internal counter. On power-up the internal address

counter is set to address 0h, so a current address read of the

EEPROM array starts at address 0. When required, as part of

a random read, the master must supply the 2 Word Address

Bytes as shown in Figure 19.

In a random read operation, the slave byte in the “dummy

write” portion must match the slave byte in the “read” section.

That is if the random read is from the array the slave byte must

be 1010111x in both instances. Similarly, for a random read of

the Clock/Control Registers, the slave byte must be 1101111x

in both places.

Write Operations

Byte Write

For a write operation, the device requires the Slave Address

Byte and the Word Address Bytes. This gives the master

access to any one of the words in the array or CCR. (Note:

Prior to writing to the CCR, the master must write a 02h, then

06h to the status register in two preceding operations to enable

the write operation. See “Writing to the Clock/Control

Registers”). Upon receipt of each address byte, the ISL12027

responds with an acknowledge. After receiving both address

bytes the ISL12027 awaits the 8-bits of data. After receiving

the 8-data bits, the ISL12027 again responds with an

acknowledge. The master then terminates the transfer by

generating a stop condition. The ISL12027 then begins an

internal write cycle of the data to the non-volatile memory.

During the internal write cycle, the device inputs are disabled,

so the device will not respond to any requests from the master.

The SDA output is at high impedance (see Figure 20).

Stops and Write Modes

Stop conditions that terminate write operations must be sent by

the master after sending at least 1 full data byte and it’s

associated ACK signal. If a stop is issued in the middle of a

data byte, or before 1 full data byte + ACK is sent, then the

ISL12027 resets itself without performing the write. The

contents of the array are not affected.

FN8232 Rev 9.00

Page 19 of 29

September 23, 2015

ISL12027, ISL12027A

S

T

A

R

T

SIGNALS FROM

THE MASTER

S

T

O

P

SLAVE

ADDRESS

WORD

ADDRESS 1

WORD

ADDRESS 0

DATA

SDA BUS

1

1 1 1 0

0 0 0 0 0 0 0

A

C

K

A

C

K

A

C

K

A

C

K

SIGNALS FROM

THE SLAVE

FIGURE 20. BYTE WRITE SEQUENCE

6 BYTES

ADDRESS

10

ADDRESS = 5

ADDRESS

15

ADDRESS POINTER ENDS

AT ADDR = 5

FIGURE 21. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10

1  n  16 FOR EEPROM ARRAY

S

T

1  n  8 FOR CCR

SIGNALS FROM

THE MASTER

S

T

O

P

A

R

T

WORD

ADDRESS 1

SLAVE

ADDRESS

WORD

ADDRESS 0

DATA

(1)

DATA

(n)

SDA BUS

1

1 1 1 0

0 0 0 0 0 0 0

A

C

K

A

C

K

A

C

K

A

C

K

SIGNALS FROM

THE SLAVE

FIGURE 22. PAGE WRITE SEQUENCE

Acknowledge Polling

Current Address Read

Disabling of the inputs during non-volatile write cycles can be

used to take advantage of the typical 5ms write cycle time.

Once the stop condition is issued to indicate the end of the

master’s byte load operation, the ISL12027 initiates the

internal non-volatile write cycle. Acknowledge polling can

begin immediately. To do this, the master issues a start

condition followed by the Memory Array Slave Address Byte for

a write or read operation (AEh or AFh). If the ISL12027 is still

busy with the non-volatile write cycle, then no ACK will be

returned. When the ISL12027 has completed the write

operation, an ACK is returned and the host can proceed with

the read or write operation. Refer to the flow chart in Figure 24.

Note: Do not use the CCR Slave byte (DEh or DFh) for

Acknowledge Polling.

Internally the ISL12027 contains an address counter that

maintains the address of the last word read incremented by

one. Therefore, if the last read was to address n, the next read

operation would access data from address n + 1. On power-up,

the 16 bit address is initialized to 0h. In this way, a current

address read immediately after the power on reset can

download the entire contents of memory starting at the first

location. Upon receipt of the Slave Address Byte with the R/W

bit set to one, the ISL12027 issues an acknowledge, then

transmits 8 data bits. The master terminates the read operation

by not responding with an acknowledge during the ninth clock

and issuing a stop condition. Refer to Figure 23 for the

address, acknowledge, and data transfer sequence.

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read operation,

the master must either issue a stop condition during the ninth

cycle or hold SDA HIGH during the ninth clock cycle and then

issue a stop condition.

Read Operations

There are three basic read operations: Current Address Read,

Random Read and Sequential Read.

FN8232 Rev 9.00

Page 20 of 29

September 23, 2015

ISL12027, ISL12027A

Random Read

S

T

S

T

O

P

Random read operations allow the master to access any

location in the ISL12027. Prior to issuing the Slave Address

Byte with the R/W bit set to zero, the master must first perform

a “dummy” write operation.

SIGNALS FROM

A

SLAVE

ADDRESS

THE MASTER

R

T

SDA BUS

1

1 1 1 1

The master issues the start condition and the slave address

byte, receives an acknowledge, then issues the word address

bytes. After acknowledging receipt of each word address byte,

the master immediately issues another start condition and the

slave address byte with the R/W bit set to one. This is followed

by an acknowledge from the device and then by the 8 bit data

word. The master terminates the read operation by not

responding with an acknowledge and then issuing a stop

condition. Refer to Figure 25 for the address, acknowledge,

and data transfer sequence.

A

C

K

SIGNALS FROM

THE SLAVE

DATA

FIGURE 23. CURRENT ADDRESS READ SEQUENCE

BYTE LOAD

COMPLETED BY

ISSUING STOP.

ENTER ACK POLLING

In a similar operation called “Set Current Address,” the device

sets the address if a stop is issued instead of the second start

shown in Figure 25. The ISL12027 then goes into standby

mode after the stop and all bus activity will be ignored until a

start is detected. This operation loads the new address into the

address counter. The next Current Address Read operation will

read from the newly loaded address. This operation could be

useful if the master knows the next address it needs to read,

but is not ready for the data.

ISSUE START

ISSUE MEMORY ARRAY SLAVE

ADDRESS BYTE

AFH (READ) OR AEH (WRITE)

ISSUE STOP

NO

ACK

RETURNED?

Sequential Read

Sequential reads can be initiated as either a current address

read or random address read. The first data byte is transmitted

as with the other modes; however, the master now responds

with an acknowledge, indicating it requires additional data. The

device continues to output data for each acknowledge received.

The master terminates the read operation by not responding

with an acknowledge and then issuing a stop condition.

YES

NO

NON-VOLATILE WRITE

CYCLE COMPLETE. CONTINUE

COMMAND SEQUENCE?

ISSUE STOP

YES

The data output is sequential, with the data from address n

followed by the data from address n + 1. The address counter

for read operations increments through all page and column

addresses, allowing the entire memory contents to be serially

read during one operation. At the end of the address space the

counter “rolls over” to the start of the address space and the

ISL12027 continues to output data for each acknowledge

received. Refer to Figure 26 for the acknowledge and data

transfer sequence.

CONTINUE

NORMAL READ OR

WRITE COMMAND

SEQUENCE

PROCEED

FIGURE 24. ACKNOWLEDGE POLLING SEQUENCE

FN8232 Rev 9.00

September 23, 2015

Page 21 of 29

ISL12027, ISL12027A

S

T

A

R

T

S

T

A

R

T

S

T

O

P

SIGNALS FROM

THE MASTER

SLAVE

ADDRESS

WORD

ADDRESS 0

SLAVE

ADDRESS

WORD

ADDRESS 1

SDA BUS

1

1 1 1 1

1

1 1 1 0

0 0 0 0 0 0 0

A

C

K

A

C

K

A

C

K

A

C

K

SIGNALS FROM

THE SLAVE

DATA

FIGURE 25. RANDOM ADDRESS READ SEQUENCE

S

T

O

P

SLAVE

ADDRESS

A

C

K

A

C

K

A

C

K

SIGNALS

FROM

THE MASTER

SDA BUS

1

A

C

K

SIGNALS FROM

THE SLAVE

DATA

(2)

DATA

(n - 1)

DATA

(1)

DATA

(n)

(n IS ANY INTEGER GREATER THAN 1)

FIGURE 26. SEQUENTIAL READ SEQUENCE

that actual capacitance would also include about 2pF of

package related capacitance. In-circuit tests with commercially

available crystals demonstrate that this range of capacitance

allows frequency control from +116ppm to -37ppm, using a

12.5pF load crystal.

Application Section

Crystal Oscillator and Temperature Compensation

Intersil has now integrated the oscillator compensation circuity

on-chip, to eliminate the need for external components and

adjust for crystal drift over-temperature and enable very high

accuracy time keeping (<5ppm drift).

In addition to the analog compensation afforded by the

adjustable load capacitance, a digital compensation feature is

available for the Intersil RTC family. There are 3-bits known as

the Digital Trimming Register or DTR, and they operate by

adding or skipping pulses in the clock signal. The range

provided is ±30ppm in increments of 10ppm. The default

setting is 0ppm. The DTR control can be used for coarse

adjustments of frequency drift over-temperature or for crystal

initial accuracy correction.

The Intersil RTC family uses an oscillator circuit with on-chip

crystal compensation network, including adjustable

load-capacitance. The only external component required is the

crystal. The compensation network is optimized for operation

with certain crystal parameters which are common in many of

the surface mount or tuning-fork crystals available today. Table

8 summarizes these parameters.

Table 9 contains some crystal manufacturers and part numbers

that meet the requirements for the Intersil RTC products.

A final application for the ATR control is in-circuit calibration for

high accuracy applications, along with a temperature sensor chip.

Once the RTC circuit is powered up with battery backup, and

frequency drift is measured. The ATR control is then adjusted to a

setting, which minimizes drift. Once adjusted at a particular

temperature, it is possible to adjust at other discrete temperatures

for minimal overall drift, and store the resulting settings in the

EEPROM. Extremely low overall temperature drift is possible with

this method. The Intersil evaluation board contains the circuitry

necessary to implement this control.

The turnover temperature in Table 8 describes the temperature

where the apex of the of the drift vs temperature curve occurs.

This curve is parabolic with the drift increasing as (T - T0)². For

an Epson MC-405 device, for example, the turnover

temperature is typically +25°C, and a peak drift of >110ppm

occurs at the temperature extremes of -40°C and +85°C. It is

possible to address this variable drift by adjusting the load

capacitance of the crystal, which will result in predictable

change to the crystal frequency. The Intersil RTC family allows

this adjustment over temperature since the devices include on-

chip load capacitor trimming. This control is handled by the

Analog Trimming Register, or ATR, which has 6-bits of control.

The load capacitance range covered by the ATR circuit is

approximately 3.25pF to 18.75pF, in 0.25pF increments. Note

Layout Considerations

The crystal input at X1 has a very high impedance and will pick up

high frequency signals from other circuits on the board. Since the

X2 pin is tied to the other side of the crystal, it is also a sensitive

node. These signals can couple into the oscillator circuit and

FN8232 Rev 9.00

Page 22 of 29

September 23, 2015

ISL12027, ISL12027A

produce double clocking or mis-clocking, seriously affecting the

accuracy of the RTC. Care needs to be taken in layout of the RTC

circuit to avoid noise pickup. Figure 27 shows a suggested layout

for the ISL12027 or ISL12026 devices.

advised to minimize noise intrusion, but ground near the X1

and X2 pins should be avoided as it will add to the load

capacitance at those pins. Keep in mind these guidelines for

other PCB layers in the vicinity of the RTC device. A small

decoupling capacitor at the V

with a solid connection to ground (see Figure 27).

pin of the chip is mandatory,

DD

The X1 and X2 connections to the crystal are to be kept as

short as possible. A thick ground trace around the crystal is

TABLE 8. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL RTC’S

PARAMETER

MIN

TYP

32.768

MAX

UNITS

kHz

NOTES

Frequency

Frequency Tolerance

±100

30

ppm

°C

Down to 20ppm if desired

Turnover Temperature

20

25

Typically the value used for most crystals

Operating Temperature Range

Parallel Load Capacitance

Equivalent Series Resistance

-40

85

°C

12.5

pF

50

k

For best oscillator performance

TABLE 9. CRYSTAL MANUFACTURERS

MANUFACTURER

PART NUMBER

CM201, CM202, CM200S

TEMP RANGE (°C)

-40 to +85

+25°C FREQUENCY TOLERANCE (ppm)

Citizen

Epson

Raltron

SaRonix

Ecliptek

ECS

±20

MC-405, MC-406

RSM-200S-A or B

32S12A or B

-40 to +85

ECPSM29T-32.768K

ECX-306/ECX-306I

FSM-327

-10 to +60

Fox

-40 to +85

the circuit at the X2 pin (oscillator output) and observe the

waveform. DO NOT DO THIS! Although in some cases you may

see a usable waveform, due to the parasitics (usually 10pF to

ground) applied with the scope probe, there will be no useful

information in that waveform other than the fact that the circuit is

oscillating. The X2 output is sensitive to capacitive impedance so

the voltage levels and the frequency will be affected by the

parasitic elements in the scope probe. Applying a scope probe

can possibly cause a faulty oscillator to start-up, hiding other

issues (although in the Intersil RTC’s, the internal circuitry assures

startup when using the proper crystal and layout).

XTAL1

32.768kH

Z

C

01µF

1

U

1

ISL12027

The best way to analyze the RTC circuit is to power it up and read

the real time clock as time advances. Alternatively the frequency

can be checked by setting an alarm for each minute. Using the

pulse interrupt mode setting, the once-per-minute interrupt

functions as an indication of proper oscillation.

R

10k

1

FIGURE 27. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-8

Backup Battery Operation

Many types of batteries can be used with the Intersil RTC

products. 3.0V or 3.6V Lithium batteries are appropriate, and

sizes are available that can power a Intersil RTC device for up

to 10 years. Another option is to use a supercapacitor for

Oscillator Measurements

When a proper crystal is selected and the layout guidelines above

are observed, the oscillator should start up in most circuits in less

than one second. Some circuits may take slightly longer, but start-

up should definitely occur in less than 5s. When testing RTC

circuits, the most common impulse is to apply a scope probe to

applications where V

may disappear intermittently for short

DD

periods of time. Depending on the value of supercapacitor

used, backup time can last from a few days to two weeks (with

FN8232 Rev 9.00

Page 23 of 29

September 23, 2015

ISL12027, ISL12027A

>1F). A simple silicon or Schottky barrier diode can be used in

series with V to charge the supercapacitor, which is

DD

• Mode B - In this mode, the selection bits indicate switchover

to battery backup at V <V , and I²C communications in

DD BAT

battery backup. In order to communicate in battery backup

connected to the V

pin. Try to use Schottky diodes with

BAT

mode, the V

voltage must be less than the V

RESET

BAT

very low leakages, <1µA desirable. Do not use the diode to

charge a battery (especially lithium batteries!).

voltage AND V

must be greater than V

. Also, pull-

RESET

DD

ups on the I²C bus pins must go to V

to communicate.

BAT

Note that whether a battery or supercap is used, if the V

This mode is the same as the normal operating mode of the

BAT

X1228 device.

voltage drops below the data sheet minimum of 1.8V and the

power cycles to 0V then back to V voltage, then the

V

DD

• Mode C - In this mode, the selection bits indicate a low V

switchover combined with no communications in battery

backup. Operation is actually identical to Mode A with I²C

DD

RESET output may stay low and the I²C communications will

not operate. The V and V power will need to be cycled to

BAT

DD

0V together to allow normal operation again.

communications down to V

= V

, then no

DD

RESET

communications (see Figure 28).

There are two possible modes for battery backup operation,

Standard and Legacy mode. In Standard mode, there are no

operational concerns when switching over to battery backup

since all other devices functions are disabled. Battery drain is

• Mode D - In this mode, the selection bits indicate switchover

to battery backup at V < V , and no I²C

DD

BAT

communications in battery backup. This mode is unique in

that there is I²C communication as long as V

is higher

DD

minimal in Standard mode, and return to Normal V powered

DD

than V

or V , whichever is greater. This mode is the

RESET

BAT

operations predictable. In Legacy modes the V

pin can

BAT

safest for guaranteeing I²C communications only when there

is a Valid V (see Figure 29).

power the chip if the voltage is above V and V

. This

TRIP

DD

makes it possible to generate alarms and communicate with

the device under battery backup, but the supply current drain is

much higher than the Standard mode and backup time is

reduced. During initial power-up, the default mode is the

Legacy mode.

V

BAT

2.7V TO 5.5V

DD

SUPERCAPACITOR

V

SS

FIGURE 28. SUPERCAPACITOR CHARGING CIRCUIT

I²C Communications During Battery Backup and

LVR Operation

Operation in Battery Backup mode and LVR is affected by the

BSW and SBIB bits as described earlier. These bits allow

flexible operation of the serial bus and EEPROM in battery

backup mode, but certain operational details need to be clear

before utilizing the different modes. The most significant detail

is that once V

goes below V

, then I²C

DD

RESET

communications cease regardless of whether the device is

programmed for I²C operation in battery backup mode.

Table 10 describes 4 different modes possible with using the

BSW and SBIB bits, and how they are affect LVR and battery

backup operation.

• Mode A - In this mode, selection bits indicate a low V

DD

switchover combined with I²C operation in battery backup

mode. In actuality the V will go below V

before

DD

RESET

switching to battery backup, which will disable I²C ANYTIME

the device goes into battery backup mode. Regardless of the

battery voltage, the I²C will work down to the V

(see Figure 29).

voltage

RESET

FN8232 Rev 9.00

Page 24 of 29

September 23, 2015

ISL12027, ISL12027A

.

TABLE 10. I²C, LV RESET, AND BATTERY BACKUP OPERATION SUMMARY (Shaded Row is same as X12028 operation)

V

I²C ACTIVE IN

BATTERY

EE PROM WRITE/

READ IN BATTERY FREQ/IRQ

BAT

SBIB

BIT

BSW SWITCHOVER

MODE

BIT

VOLTAGE

BACKUP?

ACTIVE?

NOTES

A

0

StandardMode,

NO

N/A

Operation of I²C bus down to V =V

then below that no communications. Battery

,

RESET

DD

V

= 2.2V

TRIP

typ

Default for

ISL12027A

switchover at V

.

TRIP

B

1

Legacy Mode,

YES, only if

> V

BAT RESET

YES

Yes

Operation of I²C bus into battery backup

mode, but only for

(X12028

mode)

V

< V

V

DD

BAT

Default for

ISL12027

V

> V > V

.

BAT

DD

RESET

Bus must have pull-ups to V . No

BAT

non-volatile writes with V

> V

BAT

DD

C

D

1

0

1

StandardMode,

NO

YES

Operation of I²C bus down to V = V

then below that no communications. Battery

,

RESET

DD

V

= 2.2V

TRIP

typ

switchover at V

.

TRIP

Legacy Mode,

Operation of I²C busdown to V

or

RESET

V

< V

V

, whichever is higher.

BAT

DD

BAT

.

V

(3.0V)

BAT

(2.63V)

V

DD

V

RESET

V

TRIP

(2.2V)

tPURST

RESET

I²C Bus Active

(VDD POWER, V

NOT CONNECTED)

I

(BATTERY BACKUP MODE)

BAT

FIGURE 29. EXAMPLE RESET OPERATION IN MODE A OR C

V

(3.0V)

BAT

(2.63V)

V

DD

V

RESET

V

TRIP

(2.2V)

tPURST

RESET

I²C BUS ACTIVE

I

(BATTERY BACKUP MODE)

BAT

FIGURE 30. RESET OPERATION IN MODE D

FN8232 Rev 9.00

September 23, 2015

Page 25 of 29

ISL12027, ISL12027A

seconds changes from 59 to 00) by setting the AL0 bit in the

status register to “1”.

Alarm Operation Examples

Following are examples of both Single Event and periodic

Interrupt Mode alarms.

EXAMPLE 2

EXAMPLE 1

Pulsed interrupt once per minute (IM = ”1”)

Alarm 0 set with single interrupt (IM=”0”)

Interrupts at one minute intervals when the seconds register is

at 30s.

A single alarm will occur on January 1 at 11:30am.

A. Set Alarm 0 registers as follows:

BIT

ALARM0

REGISTER 7

6

5

4

3

2

1

0 HEX

DESCRIPTION

6

0

5

0

1

4

0

1

3

0

2

0

1

0

HEX

DESCRIPTION

SCA0

1

0

1

0

B0h Seconds set to 30,

enabled

SCA0

MNA0

0

1

00h Seconds disabled

B0h Minutes set to 30,

enabled

MNA0

HRA0

DTA0

MOA0

DWA0

0

00h Minutes disabled

00h Hours disabled

00h Date disabled

HRA0

DTA0

MOA0

DWA0

1

0

1

0

1

0

91h Hours set to 11,

enabled

81h Date set to 1,

enabled

00h Month disabled

00h Day of week disabled

81h Month set to 1,

enabled

B. Set the Interrupt register as follows:

00h Day of week

disabled

BIT

CONTROL

REGISTER 7

6

5

4

3

2

1

0 HEX

DESCRIPTION

B. Also the AL0E bit must be set as follows:

INT

1

0

1

0

x0h Enable Alarm and Int

Mode

BIT

CONTROL

REGISTER

7

6

5

4

3

2

1

0

HEX DESCRIPTION

Note that the status register AL0 bit will be set each time the

alarm is triggered, but does not need to be read or cleared.

INT

0

1

0

x0h Enable Alarm

After these registers are set, an alarm will be generated when

the RTC advances to exactly 11:30am on January 1 (after

FN8232 Rev 9.00

Page 26 of 29

September 23, 2015

ISL12027, ISL12027A

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make

sure that you have the latest revision.

DATE

REVISION

CHANGE

September 23, 2015

FN8232.9 - Updated Ordering Information Table on page 2.

- Added Revision History.

- Added About Intersil Verbiage.

- Updated POD M8.15 to latest revision changes are as follows:

-Revision 1 to Revision 2 Changes:

Updated to new POD format by removing table and moving dimensions onto drawing and adding land

pattern

-Revision 2 to Revision 3 Changes:

Changed in Typical Recommended Land Pattern the following:

2.41(0.095) to 2.20(0.087)

0.76 (0.030) to 0.60(0.023)

0.200 to 5.20(0.205)

-Revision 3 to Revision 4 Changes:

Changed Note 1 "1982" to "1994"

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products

address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com.

You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.

Reliability reports are also available from our website at www.intersil.com/support.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8232 Rev 9.00

Page 27 of 29

September 23, 2015

ISL12027, ISL12027A

Package Outline Drawing

M8.173

8 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 2, 01/10

A

2

4

3.0 ±0.5

SEE DETAIL "X"

8

5

6.40

C

4.40 ±0.10

L

3

4

PIN 1

ID MARK

1

4

0.20 CBA

B

0.09-0.20

0.65

TOP VIEW

END VIEW

1.00 REF

0.05

H

C

0.90 +0.15/-0.10

1.20 MAX

6

SEATING

PLANE

GAUGE

PLANE

0.25

0.25 +0.05/-0.06

0.10 C B A

0.10 C

0°-8°

0.60 ±0.15

0.05 MIN

0.15 MAX

DETAIL "X"

SIDE VIEW

(1.45)

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimension does not include mold flash, protrusions or

gate burrs. Mold flash, protrusions or gate burrs shall

not exceed 0.15 per side.

(5.65)

PACKAGE BODY

OUTLINE

3. Dimension does not include interlead flash or protrusion.

Interlead flash or protrusion shall not exceed 0.15 per side.

4. Dimensions are measured at datum plane H.

5. Dimensioning and tolerancing per ASME Y14.5M-1994.

6. Dimension on lead width does not include dambar protrusion.

Allowable protrusion shall be 0.08 mm total in excess of

dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm.

(0.35 TYP)

(0.65 TYP)

TYPICAL RECOMMENDED LAND PATTERN

7. Conforms to JEDEC MO-153, variation AC. Issue E

FN8232 Rev 9.00

Page 28 of 29

September 23, 2015

ISL12027, ISL12027A

Package Outline Drawing

M8.15

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 4, 1/12

DETAIL "A"

1.27 (0.050)

0.40 (0.016)

INDEX

AREA

6.20 (0.244)

5.80 (0.228)

0.50 (0.20)

x 45°

0.25 (0.01)

4.00 (0.157)

3.80 (0.150)

8°

0°

1

2

3

0.25 (0.010)

0.19 (0.008)

SIDE VIEW “B”

TOP VIEW

2.20 (0.087)

1

8

SEATING PLANE

0.60 (0.023)

1.27 (0.050)

1.75 (0.069)

5.00 (0.197)

4.80 (0.189)

2

3

7

6

1.35 (0.053)

-C-

4

5

0.25(0.010)

0.10(0.004)

1.27 (0.050)

0.51(0.020)

0.33(0.013)

5.20(0.205)

SIDE VIEW “A

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensioning and tolerancing per ANSI Y14.5M-1994.

2. Package length does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

3. Package width does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

4. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

5. Terminal numbers are shown for reference only.

6. The lead width as measured 0.36mm (0.014 inch) or greater above the

seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).

7. Controlling dimension: MILLIMETER. Converted inch dimensions are not

necessarily exact.

8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.

FN8232 Rev 9.00

Page 29 of 29

September 23, 2015


型号：	ISL12027IB27Z-T
厂家：	RENESAS TECHNOLOGY CORP
描述：	Real Time Clock/Calendar with EEPROM; SOIC8, TSSOP8; Temp Range: -40° to 85°C 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管外围集成电路
文件：	总29页 (文件大小：1136K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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