ISL14010IRZ-T [RENESAS]
54MHz, OTHER CLOCK GENERATOR, PQCC16, 3 X 3 MM, ROHS COMPLIANT, PLASTIC, MO-220VEED-2, MLF-16;
| 型号： | ISL14010IRZ-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 54MHz, OTHER CLOCK GENERATOR, PQCC16, 3 X 3 MM, ROHS COMPLIANT, PLASTIC, MO-220VEED-2, MLF-16 时钟 外围集成电路 晶体 |
| 文件： | 总5页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL14010, ISL14017
®
Data Sheet
April 16, 2007
FN6407.1
Low Jitter Clock Generators for Set-Top
Box
Features
• LVTTL Outputs
The ISL14010 series of devices are general purpose
integrated Clock Synthesizers and Generators suited for
consumer applications such as Set-top Box, and various
other consumer applications.
• Selectable Crystal or Ref. Clock for Inputs
• Period Jitter ~50ps RMS
• Single Supply; 3.3V nominal
The selectable reference input accepts 30MHz signal either
from crystal or an external source. It is specified to operate
with a nominal 3.3V supply and is offered in 16 Ld QFN
package.
• Extended Temperature Range: -40ºC to +85ºC
• Available in small foot print package
- 16 Ld QFN 3mmx3mm
• Pb-Free plus anneal available (RoHS Compliant)
Contact Factory for other output frequency options.
Applications
Ordering Information
• Set-Top Boxes
PART
PART
TEMP.
PKG.
NUMBER
MARKING RANGE (°C) PACKAGE DWG. #
Pinout
ISL14010IRZ* 10IZ
-40 to +85 16 LD QFN L16.3x3
-40 to +85 16 LD QFN L16.3x3
ISL14010, ISL14017
(16 LD QFN)
ISL14017IRZ* 17IZ
*Add "-T" suffix for tape and reel.
TOP VIEW
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
16 15 14 13
VCC
X1
1
2
3
4
12 NC
11 CLK3
Selection Table
10
9
X2
CLK2
NC
PART
INPUT
NUMBER OF
OUTPUT
GND
OPTIONS FREQUENCY OUTPUTS FREQUENCY PACKAGE
5
6
7
8
ISL14010
ISL14017
30MHz
30MHz
4 LVTTL
4 LVTTL
25, 30, 48, 54 16 LD QFN
25, 30, 40, 50 16 LD QFN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL14010, ISL14017
Functional Block Diagram
CLK1
CLK2
M1
PHASE FREQ DET.
VCO1
OSC.
30MHz
CRYSTAL
N1
CLK3
CLK4
M2
PHASE FREQ DET.
VCO2
N2
Pin Description
16 LD QFN
SYMBOLS
VCC
X1
PIN DESCRIPTION
1,14,16
Supply Voltage
2
The X1 pin is the terminal 1 of an external 30MHz crystal. This pin is grounded for external CK input.
3
X2
The X2 pin is the terminal 2 of external 30MHz crystal, or external clock input.
4, 5, 7
GND
CLK1
CLK2
CLK3
CLK4
NC
Ground
8
CLK1 Output: 25MHz
10
11
CLK2 Output: 30MHz
CLK3 Output: 48MHz (40MHz for ISL14017)
CLK4 Output: 54MHz (50MHz for ISL14017)
No Connect
13
6, 9, 12, 15
FN6407.1
April 16, 2007
2
ISL14010, ISL14017
Absolute Maximum Ratings
Thermal Information
Voltage on VCC, CLK pins (respect to Gnd) . . . . . . . . -0.3V to 4.0V
Voltage on X1, X2 pins (respect to Gnd) . . . . . . . . . . . -0.3V to 2.5V
ESD Rating
MIL STD-883, Method 3014. . . . . . . . . . . . . . . . . . . . . . . . .>±5kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
Thermal Resistance (Typical, Note 1)
16 Ld QFN Package. . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65ºC to +150ºC
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
θ
(°C/W)
58
θ
(°C/W)
11
JA
JC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
DC Electrical Specifications
V
= 3.3V ±10%, T = -40ºC to +85ºC, Typical values are at T = +25ºC and V
= 3.3V,
CC
A
A
CC
Unless otherwise noted
SYMBOL
Supply Voltage
SYMBOL
CONDITIONS
Supply Voltage
Supply Current C = 5pF on all outputs
MIN
TYP
3.3
11
MAX
3.6
UNIT
V
V
3.0
CC
Supply Current
I
15
mA
CC
L
CLOCK INPUT X (X GROUNDED) FOR EXTERNAL CLOCK MODE
2
1
Input High Level
Input Level Low
Input Current
V
1.5
2.4
0.5
V
V
IH
V
IL
IIL, IIH
V
to Ground
0.5
mA
X2
CLOCK OUTPUTS (CLK)
Output High Level
V
I
I
I
I
I
I
= -100µA
= -4mA
= -6mA
= 100µA
= 4mA
V - 0.2
CC
V
V
OH
OH
OH
OH
OL
OL
OL
2.4
2.1
V
Output Low Level
V
0.2
0.4
0.75
30
V
OL
V
= 6mA
V
Output Short Circuit Current
IOSC
CLK = V
or Gnd
6
13
mA
CC
AC Electrical Specifications
SYMBOL
C = 5pF on all outputs
L
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Crystal Frequency
CLOCK OUTPUTS
Rise Time
f
30
MHz
IN
t
20% to 80% V
1.8
1.8
ns
ns
%
R
CC
CC
Fall Time
t
80% to 20% V
F
Duty Cycle
40
60
Period Jitter
J
RMS
50
2
ps
ms
P
Power Up Time
t
V
>2.7V
CC
PO
FN6407.1
April 16, 2007
3
ISL14010, ISL14017
Typical Performance Curves (Period Jitter)
70
65
60
55
50
45
40
35
30
25
20
V
= 3.3V
SUPPLY
TEMPERATURE +23ºC
CK1
CK2
CK4
CK3
0
2
4
6
8
10
12
14
LOAD CAPACITANCE (pF)
FIGURE 1. STANDARD DEVIATION vs LOAD CAPACITANCE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6407.1
April 16, 2007
4
ISL14010, ISL14017
Package Outline Drawing
L16.3x3
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 4/07
4X
1.5
3.00
0.50
12X
A
6
B
PIN #1 INDEX AREA
16
13
6
PIN 1
INDEX AREA
1
12
1 .50 ± 0 . 15
9
4
(4X)
0.15
5
8
0.10 M C A B
+ 0.07
4
TOP VIEW
16X 0.23
- 0.05
16X 0.40 ± 0.10
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
C
0 . 90 ± 0.1
BASE PLANE
( 2. 80 TYP )
(
SEATING PLANE
0.08 C
SIDE VIEW
1. 50 )
( 12X 0 . 5 )
( 16X 0 . 23 )
( 16X 0 . 60)
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6407.1
April 16, 2007
5
相关型号：
ISL14017IRZ
50MHz, OTHER CLOCK GENERATOR, PQCC16, 3 X 3 MM, ROHS COMPLIANT, PLASTIC, MO-220VEED-2, MLF-16
RENESAS
ISL1532AIRZ
Dual Channel Fixed Gain Differential DSL Line Driver; QFN24, TSSOP20; Temp Range: -40° to 85°C
RENESAS
©2020 ICPDF网 联系我们和版权申明