ISL22414UFU10Z-T [RENESAS]
50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, ROHS COMPLIANT, PLASTIC, MO-187BA, MSOP-10;
| 型号： | ISL22414UFU10Z-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, ROHS COMPLIANT, PLASTIC, MO-187BA, MSOP-10 光电二极管 转换器 电阻器 |
| 文件： | 总16页 (文件大小：835K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL22414
®
Single Digitally Controlled Potentiometer (XDCP™)
Data Sheet
December 16, 2010
FN6424.1
®
Low Noise, Low Power, SPI Bus, 256 Taps
Features
The ISL22414 integrates a single digitally controlled
potentiometer (DCP), control logic and non-volatile memory
on a monolithic CMOS integrated circuit.
• 256 resistor taps
• SPI serial interface with write/read capability
• Daisy Chain Configuration
• Shutdown mode
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wiper is controlled by the user through the SPI
serial interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR control the position of the
wiper. At power-up the device recalls the contents of the
DCP’s IVR to the WR.
• Non-volatile EEPROM storage of wiper position
• 14 General Purpose non-volatile registers
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T ≤ +55°C
• Wiper resistance: 70Ω typical @ 1mA
• Standby current <2.5µA max
The ISL22414 also has 14 General Purpose non-volatile
registers that can be used as storage of lookup table for
multiple wiper position or any other valuable information.
• Shutdown current <2.5µA max
• Dual power supply
The ISL22414 features a dual supply that is beneficial for
applications requiring a bipolar range for DCP terminals
between V- and VCC.
- VCC = 2.25V to 5.5V
- V- = -2.25V to -5.5V
The DCP can be used as three-terminal potentiometer or as
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.
• 10kΩ, 50kΩ or 100kΩ total resistance
• Extended industrial temperature range: -40°C to +125°C
• Military temperature range: -55 to +125°C
• 10 Lead MSOP
Pinout
ISL22414
(10 LD MSOP)
TOP VIEW
• Pb-free (RoHS compliant)
O
10
9
SCK
SDO
SDI
CS
Vcc
1
2
3
4
5
RH
RW
8
7
RL
V-
GND
6
Ordering Information
PART NUMBER
(NOTES 1, 2)
PART
RESISTANCE OPTION
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
MARKING
414TZ
414UZ
(kΩ)
ISL22414TFU10Z
ISL22414UFU10Z
ISL22414WFU10Z
ISL22414WMU10Z
NOTES:
100
50
-40 to +125
-40 to +125
-40 to +125
-55 to +125
10 Ld MSOP
M10.118
10 Ld MSOP
10 Ld MSOP
10 Ld MSOP
M10.118
M10.118
M10.118
414WZ
414WM
10
10
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
2. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
Copyright Intersil Americas Inc. 2007, 2010. All Rights Reserved
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCPis a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL22414
Block Diagram
VCC
V-
RH
SCK
SDO
SDI
POWER UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC
SPI
INTERFACE
WR
VOLATILE
REGISTER
AND
CS
WIPER
CONTROL
CIRCUITRY
NON-VOLATILE
REGISTERS
RL
RW
GND
Pin Descriptions
MSOP PIN
SYMBOL
DESCRIPTION
1
2
SCK
SDO
SDI
CS
SPI interface clock input
Data Output of the SPI serial interface
Data Input of the SPI serial interface
Chip Select active low input
Negative power supply pin
Device ground pin
3
4
5
V-
6
GND
RL
7
“Low” terminal of DCP
8
RW
RH
“Wiper” terminal of DCP
“High” terminal of DCP
9
10
VCC
Power supply pin
FN6424.1
December 16, 2010
2
ISL22414
Absolute Maximum Ratings
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any Digital Interface Pin
Thermal Resistance (Typical, Note 3)
θ
(°C/W)
JA
10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3
CC
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V
CC
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0.3V
Voltage at any DCP pin with Respect to GND . . . . . . . . . . V- to V
CC
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
I
W
Recommended Operating Conditions
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A @ +125°C
ESD
Temperature Range
Full Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V
CC
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.25V to -5.5V
Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Analog Specifications Over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating
temperature range.
MIN
TYP
MAX
SYMBOL
PARAMETER
RH to RL Resistance
TEST CONDITIONS
(Note 18) (Note 4) (Note 18)
UNIT
kΩ
R
W option
U option
T option
10
50
TOTAL
kΩ
100
kΩ
RH to RL Resistance Tolerance
-20
V-
+20
%
End-to-End Temperature
Coefficient
W option
±150
±50
ppm/°C
ppm/°C
V
U, T option
V
, V
RH RL
DCP Terminal Voltage
Wiper Resistance
V
and V to GND
RL
V
CC
RH
R
RH - floating, V = V-, force Iw current to the
RL
70
250
Ω
W
wiper, I = (V
- V )/R
W
CC
RL TOTAL
C /C /C
W
Potentiometer Capacitance
Leakage on DCP Pins
See “DCP Macro Model” on page 7
Voltage at pin from V- to V
10/10/25
0.1
pF
µA
H
L
I
-1
1
LkgDCP
CC
VOLTAGE DIVIDER MODE (V- @ RL; V
@ RH; measured at RW, unloaded)
CC
INL
(Note 9)
Integral Non-linearity
Monotonic Over All Tap Positions
W option
-1.5
-1.0
-1.0
-0.5
±0.5
±0.2
1.5
1.0
1.0
0.5
LSB
(Note 5)
U, T option
W option
LSB
(Note 5)
DNL
(Note 8)
Differential Non-linearity
Monotonic Over All Tap Positions
±0.4
LSB
(Note 5)
U, T option
±0.15
LSB
(Note 5)
ZSerror
(Note 6)
Zero-scale Error
Full-scale Error
W option
0
0
1
0.5
-1
5
2
0
0
LSB
(Note 5)
U, T option
FSerror
(Note 7)
W option
-5
-2
LSB
(Note 5)
U, T option
-1
TC
(Note 10)
Ratiometric Temperature
Coefficient
DCP register set to 80 hex
±4
ppm/°C
V
FN6424.1
December 16, 2010
3
ISL22414
Analog Specifications Over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating
temperature range. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 18) (Note 4) (Note 18)
UNIT
kHz
kHz
kHz
f
-3dB Cut Off Frequency
Wiper at midpoint (80hex) W option (10k)
Wiper at midpoint (80hex) U option (50k)
Wiper at midpoint (80hex) T option (100k)
1000
250
cutoff
120
RESISTOR MODE (Measurements between R and R with R not connected, or between R and R with R not connected)
W
L
H
W
H
L
RINL
(Note 14)
Integral Non-linearity
Differential Non-linearity
Offset
W option
-3
±1.5
±0.3
±0.4
±0.15
1
3
MI
(Note 11)
U, T option
W option
-1
1
MI
(Note 11)
RDNL
(Note 13)
-1.5
-0.5
0
1.5
0.5
5
MI
(Note 11)
U, T option
W option
MI
(Note 11)
Roffset
MI
(Note 12)
(Note 11)
U, T option
0
0.5
2
MI
(Note 11)
TC
(Notes 15)
Resistance Temperature
Coefficient
DCP register set between 32 hex and FF hex
±50
ppm/°C
R
Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits apply over the
operating temperature range.
MIN
TYP
MAX
SYMBOL
PARAMETER
Supply Current
TEST CONDITIONS
= 5.5V, V- = 5.5V, f = 5MHz; (for SPI
(Note 18) (Note 4) (Note 18)
UNIT
I
V
V
0.36
0.13
-0.18
-0.06
1
1
mA
CC1
CC
CC
SCK
(volatile write/read)
Active, Read and Volatile Write states only)
V
= 2.25V, V- = -2.25V, f = 5MHz; (for SPI
0.4
mA
mA
mA
mA
mA
mA
mA
µA
CC
SCK
Active, Read and Volatile Write states only)
I
V- Supply Current
(volatile write/read)
V- = -5.5V, V = 5.5V, f = 5MHz; (for SPI
-1
V-1
CC SCK
Active, Read and Volatile Write states only)
V- = -2.25V, V = 2.25V, f = 5MHz; (for SPI
-0.4
CC
SCK
Active, Read and Volatile Write states only)
I
V
Supply Current
(non-volatile write/read)
V
= 5.5V, V- = 5.5V, f
= 5MHz; (for SPI
2
CC2
CC
CC
SCK
Active, Read and Non-volatile Write states only)
V
= 2.25V, V- = -2.25V, f = 5MHz; (for SPI
0.3
0.7
CC
SCK
Active, Read and Non-volatile Write states only)
I
V- Supply Current
(non-volatile write/read)
V- = -5.5V, V = 5.5V, f = 5MHz; (for SPI
-2
-1.2
-0.4
0.2
V-2
CC SCK
Active, Read and Non-volatile Write states only)
V- Supply Current
(non-volatile write/read)
V- = -2.25V, V = 2.25V, f = 5MHz; (for SPI
-0.7
CC
SCK
Active, Read and Non-volatile Write states only)
I
V
Current (standby)
V
= +5.5V, V- = -5.5V @ +85°C, SPI interface
1.5
2.5
1
SB
CC
CC
in standby state
V
= +5.5V, V- = -5.5V @ +125°C, SPI
1
µA
CC
interface in standby state
V
= +2.25V, V- = -2.25V @ +85°C, SPI
0.1
µA
CC
interface in standby state
V
= +2.25V, V- = -2.25V @ +125°C, SPI
0.5
2
µA
CC
interface in standby state
FN6424.1
December 16, 2010
4
ISL22414
Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits apply over the
operating temperature range. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
V- Current (Standby)
TEST CONDITIONS
(Note 18) (Note 4) (Note 18)
UNIT
I
V- = -5.5V, V = +5.5V @ +85°C, SPI interface
CC
in standby state
-2.5
-4
-0.7
-3
µA
V-SB
V- = -5.5V, V
CC
= +5.5V @ +125°C, SPI
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
interface in standby state
V- = -2.25V, V = +2.25V @ +85°C, SPI
-1.5
-3
-0.3
-1
CC
interface in standby state
V- = -2.25V, V
= +2.25V @ +125°C, SPI
CC
interface in standby state
I
V
Current (Shutdown)
V
= +5.5V, V- = -5.5V @ +85°C, SPI interface
0.2
1
1.5
2.5
1
SD
CC
CC
in standby state
V
= +5.5V, V- = -5.5V @ +125°C, SPI
CC
interface in standby state
V
= +2.25V, V- = -2.25V @ +85°C, SPI
0.1
0.5
-0.7
-3
CC
interface in standby state
V
= +2.25V, V- = -2.25V @ +125°C, SPI
2
CC
interface in standby state
I
V- Current (Shutdown)
V- = -5.5V, V = +5.5V @ +85°C, SPI interface
CC
in standby state
-2.5
-4
V-SD
V- = -5.5V, V
CC
= +5.5V @ +125°C, SPI
interface in standby state
V- = -2.25V, V = +2.25V @ +85°C, SPI
-1.5
-3
-0.3
-1
CC
interface in standby state
V- = -2.25V, V
= +2.25V @ +125°C, SPI
CC
interface in standby state
I
Leakage Current, at Pins SCK, SDI, Voltage at pin from GND to V
SDO and CS
-0.5
0.5
LkgDig
CC
t
DCP Wiper Response Time
CS rising edge to wiper new position
1.5
1.5
µs
µs
WRT
t
DCP Recall Time From Shutdown
Mode
CS rising edge to wiper stored position and RH
connection
ShdnRec
Vpor
Power-on Recall Voltage
Minimum V
at which memory recall occurs
1.9
0.2
2.1
5
V
CC
VccRamp
V
Ramp Rate
V/ms
ms
CC
t
Power-up Delay
V
above Vpor, to DCP Initial Value Register
CC
D
recall completed, and SPI Interface in standby
state
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
Cycles
Years
ms
EEPROM Retention
Temperature T ≤ +55ºC
50
t
Non-volatile Write Cycle Time
12
20
WC
(Note 16)
SERIAL INTERFACE SPECIFICATIONS
V
SCK, SDI, and CS Input Buffer LOW
voltage
-0.3
0.3*V
V
V
V
V
IL
CC
V
SCK, SDI, and CS Input Buffer HIGH
Voltage
0.7*V
V
+0.3
CC
IH
CC
Hysteresis SCK, SDI, and CS Input Buffer
Hysteresis
0.05*V
0
CC
V
SDO Output Buffer LOW Voltage
I
= 4mA for Open Drain output, pull-up
0.4
OL
OL
voltage Vpu = V
CC
FN6424.1
December 16, 2010
5
ISL22414
Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits apply over the
operating temperature range. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 18) (Note 4) (Note 18)
UNIT
R
SDO Pull-up Resistor Off-chip
Maximum is determined by t
maximum bus load Cb = 30pF, f
and t
with
= 5MHz
2
kΩ
pu
RO
FO
(Note 17)
SCK
Cpin
SCK, SDI, SDO and CS Pin
Capacitance
10
pF
f
SPI Frequency
5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
SCK
t
SPI Clock Cycle Time
SPI Clock High Time
200
100
100
250
250
50
CYC
t
WH
t
SPI Clock Low Time
WL
t
Lead Time
LEAD
t
Lag Time
LAG
t
SDI, SCK and CS Input Setup Time
SDI, SCK and CS Input Hold Time
SDI, SCK and CS Input Rise Time
SDI, SCK and CS Input Fall Time
SDO output Disable Time
SDO Output Setup Time
SDO Output Valid Time
SDO Output Hold Time
SDO Output Rise Time
SDO Output Fall Time
CS Deselect Time
SU
t
50
H
t
10
RI
t
10
0
20
FI
t
100
DIS
t
50
150
0
SO
t
V
t
HO
RO
t
R
R
= 2k, Cbus = 30pF
= 2k, Cbus = 30pF
60
60
pu
t
t
FO
CS
pu
2
NOTES:
4. Typical values are for T = +25°C and 3.3V supply voltage.
A
5. LSB: [V(RW)
– V(RW) ]/255. V(RW) and V(RW) are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
255 0
255
0
incremental voltage when changing from one tap to an adjacent tap.
6. ZS error = V(RW) /LSB.
0
7. FS error = [V(RW)
– V ]/LSB.
CC
255
8. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 255. i is the DCP register setting.
i-1
i
9. INL = [V(RW) – i • LSB – V(RW)]/LSB for i = 1 to 255
i
6
Max(V(RW) ) – Min(V(RW) )
10
i
i
10.
for i = 16 to 255 decimal, T = -40°C to +125°C or T = -55°C to +125°C. Max( ) is the
maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage
over the temperature range.
--------------------------------------------------------------------------------------------- --------------
TC
=
×
V
ΔT°C
[Max(V(RW) ) + Min(V(RW) )] ⁄ 2
i
i
11. MI = |RW
– RW |/255. MI is a minimum increment. RW
and RW are the measured resistances for the DCP register set to FF hex and
255 0
255
0
00 hex respectively.
12. Roffset = RW /MI, when measuring between RW and RL.
0
Roffset = RW
/MI, when measuring between RW and RH.
255
13. RDNL = (RW – RW )/MI -1, for i = 1 to 255.
i-1
i
14. RINL = [RW – (MI • i) – RW ]/MI, for i = 1 to 255.
i
0
6
[Max(Ri) – Min(Ri)]
10
15.
for i = 16 to 255, T = -40°C to +125°C or T = -55°C to +125°C. Max( ) is the maximum value of the
resistance and Min( ) is the minimum value of the resistance over the temperature range.
--------------------------------------------------------------- --------------
TC
=
×
R
ΔT°C
[Max(Ri) + Min(Ri)] ⁄ 2
16. t
is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle.
WC
17. R is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates.
pu
18. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN6424.1
December 16, 2010
6
ISL22414
DCP Macro Model
R
TOTAL
RH
RL
C
L
C
H
C
W
10pF
10pF
25pF
RW
Timing Diagrams
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
CYC
SCK
...
t
t
t
RI
FI
t
t
t
WL
SU
H
WH
...
MSB
LSB
SDI
HIGH IMPEDANCE
SDO
Output Timing
CS
SCK
SDO
SDI
...
...
t
t
t
SO
HO
DIS
MSB
LSB
t
V
ADDR
XDCP Timing (for All Load Instructions)
CS
t
WRT
SCK
...
...
MSB
LSB
SDI
V
W
HIGH IMPEDANCE
SDO
FN6424.1
December 16, 2010
7
ISL22414
Typical Performance Curves
80
2.0
1.5
1.0
0.5
0
T = +125ºC
70
60
50
40
30
20
10
0
T = +25ºC
T = -40ºC
I
CC
-0.5
-1.0
-1.5
-2.0
I
V-
0
50
100
150
200
250
-40
0
40
TEMPERATURE (°C)
80
120
TAP POSITION (DECIMAL)
FIGURE 2. STANDBY I
AND I vs TEMPERATURE
V-
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[ I(RW) = V /R ] FOR 10kΩ (W)
CC
CC TOTAL
0.50
0.50
0.25
0
V
= 5.5V
CC
T = +25ºC
T = +25ºC
V
= 2.25V
CC
0.25
0
-0.25
-0.50
-0.25
-0.50
V
= 5.5V
V
= 2.25V
100
CC
100
TAP POSITION (DECIMAL)
CC
0
50
150
200
250
0
50
150
200
250
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
MODE FOR 10kΩ (W)
2.0
0
10k
1.6
1.2
-1
V
= 2.25V
CC
50k
V
= 5.5V
CC
-2
0.8
-3
-4
50k
10k
V
= 2.25V
V
= 5.5V
CC
CC
0.4
0
-5
-40
0
40
80
120
-40
0
40
TEMPERATURE (ºC)
80
120
TEMPERATURE (ºC)
FIGURE 6. FS ERROR vs TEMPERATURE
FIGURE 5. ZS ERROR vs TEMPERATURE
FN6424.1
December 16, 2010
8
ISL22414
Typical Performance Curves (Continued)
0.5
2.0
T = +25ºC
T = +25ºC
V
= 5.5V
1.5
1.0
CC
V
= 2.25V
0.25
0
CC
0.5
0
-0.25
-0.50
V
= 2.25V
100
CC
V
= 5.5V
CC
-0.5
0
50
150
200
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR
10kΩ (W)
10kΩ (W)
200
1.60
10k
160
1.20
10k
120
80
0.80
5.5V
0.40
0.00
50k
40
50k
2.25V
0
16
-0.40
66
116
166
216
266
-40
0
40
80
120
TAP POSITION (DECIMAL)
TEMPERATURE (ºC)
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
FIGURE 9. END TO END R
% CHANGE vs
TOTAL
TEMPERATURE
500
400
300
INPUT
OUTPUT
10k
200
100
50k
WIPER AT MID POINT (POSITION 80h)
R
= 10kΩ
TOTAL
0
16
66
116
166
216
TAP POSITION (DECIMAL)
FIGURE 12. FREQUENCY RESPONSE (1MHz)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FN6424.1
December 16, 2010
9
ISL22414
Typical Performance Curves (Continued)
CS
SCL
WIPER UNLOADED,
MOVEMENT FROM 0h to FFh
WIPER
FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h
FIGURE 14. LARGE SIGNAL SETTLING TIME
shifted in at the rising edge of the serial clock SCK, while the
CS input is low.
Pin Description
Potentiometer Pins
RH AND RL
CHIP SELECT (CS)
CS LOW enables the ISL22414, placing it in the active
power mode. A HIGH to LOW transition on CS is required
prior to the start of any operation after power up. When CS is
HIGH, the ISL22414 is deselected and the SDO pin is at
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state.
The high (RH) and low (RL) terminals of the ISL22414 are
equivalent to the fixed terminals of a mechanical
potentiometer. RH and RL are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WR set to 255 decimal, the wiper will be
closest to RH, and with the WR set to 0, the wiper is closest
to RL.
Principles of Operation
The ISL22414 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory and the
SPI serial interface providing direct communication between
host and potentiometer and memory. The resistor array is
comprised of individual resistors connected in a series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to
the wiper.
RW
RW is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.
Bus Interface Pins
SERIAL CLOCK (SCK)
This is the serial clock input of the SPI serial interface.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
SERIAL DATA OUTPUT (SDO)
The SDO is a serial data output pin. During a read cycle, the
data bits are shifted out on the falling edge of the serial clock
SCK and will be available to the master on the following
rising edge of SCK.
When the device is powered down, the last value stored in
IVR will be maintained in the non-volatile memory. When
power is restored, the content of the IVR is recalled and
loaded into the WR to set the wiper to the initial position.
The output type is configured through ACR[1] bit for Push-
Pull or Open Drain operation. Default setting for this pin is
Push-Pull. An external pull up resistor is required for Open
Drain output operation. Note, the external pull up voltage not
allowed beyond VCC.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). When the WR of a DCP
contains all zeroes (WR[7:0]= 00h), its wiper terminal (RW)
SERIAL DATA INPUT (SDI)
The SDI is the serial data input pin for the SPI interface. It
receives device address, operation code, wiper address and
data from the SPI remote host device. The data bits are
FN6424.1
December 16, 2010
10
ISL22414
is closest to its “Low” terminal (RL). When the WR register of
The register at address 0Fh is a read-only reserved register.
Information read from this register should be ignored.
a DCP contains all ones (WR[7:0]= FFh), its wiper terminal
(RW) is closest to its “High” terminal (RH). As the value of
the WR increases from all zeroes (0) to all ones (255
decimal), the wiper moves monotonically from the position
closest to RL to the closest to RH. At the same time, the
resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
The non-volatile IVR and volatile WR registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
The VOL bit (ACR[7]) determines whether the access to
wiper registers WR or initial value registers IVR.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
While the ISL22414 is being powered up, the WR is reset to
80h (128 decimal), which locates RW roughly at the center
between RL and RH. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WR will be reloaded with the value stored in a
non-volatile Initial Value Register (IVR).
BIT #
7
6
5
4
0
3
0
2
0
1
0
0
BIT
VOL SHDN WIP
SDO
NAME
If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.
The WR and IVR can be read or written to directly using the
SPI serial interface as described in the following sections.
Memory Description
The SHDN bit (ACR[6]) disables or enables Shutdown
mode. When this bit is 0, DCP is in Shutdown mode, i.e.
DCP is forced to end-to-end open circuit and RW is shorted
to RL as shown on Figure 15. Default value of SHDN bit is 1.
The ISL22414 contains one non-volatile 8-bit Initial Value
Register (IVR), fourteen non-volatile 8-bit General Purpose
(GP) registers, volatile 8-bit Wiper Register (WR), and
volatile 8-bit Access Control Register (ACR). The memory
map of ISL22414 is in Table 1.
RH
TABLE 1. MEMORY MAP
ADDRESS
RW
(hex)
10
F
NON-VOLATILE
VOLATILE
N/A
ACR
Reserved
RL
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
E
D
C
B
A
9
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
IVR
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
WR
Setting SHDN bit to 1 is returned wiper to prior to Shutdown
Mode position.
The WIP bit (ACR[5]) is a read-only bit. It indicates that non-
volatile write operation is in progress. The WIP bit can be
read repeatedly after a non-volatile write to determine if the
write has been completed. It is impossible to write or read to
the WR or ACR while WIP bit is 1.
8
7
The SDO bit (ACR[1]) configures type of SDO output pin.
The default value of SDO bit is 0 for Push - Pull output. SDO
pin can be configured as Open Drain output for some
application. In this case, an external pull up resistor is
required. See “Applications Information” on page 13.
6
5
4
3
SPI Serial Interface
2
The ISL22414 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with
data clocked in on the rising edge of SCK, and clocked out
on the falling edge of SCK. CS must be LOW during
communication with the ISL22414. SCK and CS lines are
controlled by the host or master. The ISL22414 operates
only as a slave device.
1
0
The non-volatile register (IVR) at address 0, contains initial
wiper position and volatile register (WR) contains current
wiper position.
FN6424.1
December 16, 2010
11
ISL22414
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
LOW. Then host send a valid Instruction Byte, followed by
one or more Data Bytes to SDI pin. The host terminates the
write operation by pulling the CS pin from LOW to HIGH.
Instruction is executed on rising edge of CS. For a write to
address 0, the MSB of the byte at address 10h (ACR[7])
determines if the Data Byte is to be written to volatile or both
volatile and non-volatile registers. Refer to “Memory
Description” and Figure 16. Note, the internal non-volatile
write cycle starts with the rising edge of CS and requires up
to 20ms. During non-volatile write cycle the read operation to
ACR register is allowed to check WIP bit.
Protocol Conventions
The SPI protocol contains Instruction Byte followed by one
or more Data Bytes. A valid Instruction Byte contains
instruction as the three MSBs, with the following five register
address bits (see Table 3).
The next byte sent to the ISL22414 is the Data Byte.
TABLE 3. INSTRUCTION BYTE FORMAT
Read Operation
BIT #
7
6
5
4
3
2
1
0
A Read operation to the ISL22414 is a four byte operation. It
requires first, the CS transition from HIGH to LOW. Then
host send a valid Instruction Byte, followed by “dummy” Data
Byte, NOP Instruction Byte and another “dummy” Data Byte
to SDI pin. The SPI host receives the Instruction Byte
(instruction code + register address) and requested Data
Byte from SDO pin on the rising edge of SCK during third
and fourth bytes respectively. The host terminates the read
operation by pulling the CS pin from LOW to HIGH (see
Figure 17). Reading from the IVR will not change the WR, if
its contents are different.
I2
I1
I0
R4
R3
R2
R1
R0
Table 4 contains a valid instruction set for ISL22414.
There are only sixteen register addresses possible for this
DCP. If the [R4:R0] bits are zero, then the read or write is to
either the IVR or the WR register (depends of VOL bit at
ACR). If the [R4:R0] are 10000, then the operation is on the
ACR.
Write Operation
A Write operation to the ISL22414 is a two or more bytes
operation. It requires first, the CS transition from HIGH to
TABLE 4. INSTRUCTION SET
INSTRUCTION SET
I2
0
I1
0
I0
0
R4
X
R3
X
R2
X
R1
X
R0
X
OPERATION
NOP
0
0
1
X
X
X
X
X
ACR READ
ACR WRITE
0
1
1
X
X
X
X
X
1
0
0
R4
R4
R3
R3
R2
R2
R1
R1
R0
R0
WR, IVR, GP or ACR READ
WR, IVR, GP or ACR WRITE
1
1
0
where X means “do not care”
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
DATA BYTE
WR INSTRUCTION
ADDR
SDI
SDO
FIGURE 16. TWO BYTE WRITE SEQUENCE
FN6424.1
December 16, 2010
12
ISL22414
1
8
16
24
32
CS
SCK
NOP
RD
RD
ADDR
SDI
ADDR
READ DATA
SDO
FIGURE 17. FOUR BYTE READ SEQUENCE
to DCP(N-1) as follow: DCP0 --> DCP1 --> DCP2 --> ... -->
DCP(N-1). The write instruction is executed on the rising
edge of CS for all N DCPs simultaneously.
Applications Information
Communicating with ISL22414
Communication with ISL22414 proceeds using SPI interface
through the ACR (address 10000b), IVR (address 00000b),
WR (addresses 00000b) and General Purpose registers
(addresses from 00001b to 01110b).
Daisy Chain Read Operation
The read operation consists two parts: first, send read
instructions (N two bytes operation) with valid address;
second, read the requested data while sending NOP
instructions (N two bytes operation) as shown on Figure 20,
and Figure 21.
The wiper of the potentiometer is controlled by the WR
register. Writes and reads can be made directly to these
register to control and monitor the wiper position without any
non-volatile memory changes. This is done by setting MSB
bit at address 10000b to 1 (ACR[7] = 1).
The first part starts by HIGH to LOW transition on CS line,
followed by N two bytes read instruction on SDI line with
reversed chain access sequence: the instruction byte +
dummy data byte for the last DCP in chain is going first,
followed by LOW to HIGH transition on CS line. The read
instructions are executed during second part of read
sequence. It also starts by HIGH to LOW transition on CS
line, followed by N number of two bytes NOP instructions on
SDI line and LOW to HIGH transition of CS. The data is read
on every even byte during second part of read sequence
while every odd byte contains instruction code + address
from which the data is being read.
The non-volatile IVR stores the power up position of the
wiper. IVR is accessible when MSB bit at address 10000b is
set to 0 (ACR[7] = 0). Writing a new value to the IVR register
will set a new power up position for the wiper. Also, writing to
this register will load the same value into the corresponding
WR as the IVR. Reading from the IVR will not change the
WR, if its contents are different.
Daisy Chain Configuration
When application needs more then one ISL22414, it can
communicate with all of them without additional CS lines by
daisy chaining the DCPs as shown on Figure 18. In Daisy
Chain configuration the SDO pin of previous chip is
connected to SDI pin of the following chip, and each CS and
SCK pins are connected to the corresponding
microcontroller pins in parallel, like regular SPI interface
implementation. The Daisy Chain configuration can also be
used for simultaneous setting of multiple DCPs. Note, the
number of daisy chained DCPs is limited only by the driving
capabilities of SCK and CS pins of microcontroller; for larger
number of SPI devices buffering of SCK and CS lines is
required.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the
sudden transition from a very low impedance “make” to a
much higher impedance “break within an extremely short
period of time (<50ns). Two such code transitions are EFh to
F0h, and 0Fh to 10h. Note, that all switching transients will
settle well within the settling time as stated in the datasheet.
A small capacitor can be added externally to reduce the
amplitude of these voltage transients, but that will also
reduce the useful bandwidth of the circuit, thus may not be a
good solution for some applications. It may be a good idea,
in that case, to use fast amplifiers in a signal chain for fast
recovery.
Daisy Chain Write Operation
The write operation starts by HIGH to LOW transition on CS
line, followed by N number of two bytes write instructions on
SDI line with reversed chain access sequence: the
instruction byte + data byte for the last DCP in chain is going
first, as shown on Figure 19, where N is a number of DCPs
in chain. The serial data is going through DCPs from DCP0
FN6424.1
December 16, 2010
13
ISL22414
N DCP IN A CHAIN
CS
SCK
DCP0
DCP1
DCP2
DCP(N-1)
CS
MOSI
MISO
CS
CS
CS
SCK
SDI
SCK
SDI
SCK
SDI
SCK
SDI
µC
SDO
SDO
SDO
SDO
FIGURE 18. DAISY CHAIN CONFIGURATION
CS
SCK
16 CLKS
C P0
16 CLKLS
C P2
16 CLKS
WR
D
WR
D
D
C P1
WR
WR
D
SDI
D
C P1
C P2
SDO 0
WR
C P2
WR
D
SDO 1
SDO 2
FIGURE 19. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
SDI
INSTRUCTION
ADDR
DATA IN
SDO
DATA OUT
FIGURE 20. TWO BYTE OPERATION
FN6424.1
December 16, 2010
14
ISL22414
CS
SCK
SDI
16 CLKS
RD DCP2
16 CLKS
RD DCP1
16 CLKS
RD DCP0
16 CLKS
NOP
16 CLKS
NOP
16 CLKS
NOP
DCP0 OUT
DCP2 OUT
DCP1 OUT
SDO
FIGURE 21. DAISY CHAIN READ SEQUENCE OF N = 3 DCP
FN6424.1
December 16, 2010
15
ISL22414
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
E
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.18
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.27
0.20
3.05
3.05
NOTES
-B-
0.20 (0.008)
INDEX
AREA
A
A1
A2
b
0.037
0.002
0.030
0.007
0.004
0.116
0.116
0.043
0.006
0.037
0.011
0.008
0.120
0.120
-
1 2
A
B
C
-
TOP VIEW
-
4X θ
0.25
(0.010)
R1
9
R
GAUGE
PLANE
c
-
D
3
SEATING
PLANE
E1
e
4
L
-C-
4X θ
0.020 BSC
0.50 BSC
-
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
SEATING
PLANE
L
6
0.10 (0.004)
-A-
C
C
L1
N
0.037 REF
10
0.95 REF
10
-
b
-H-
A1
7
e
D
R
0.003
0.003
-
-
0.07
-
-
-
0.20 (0.008)
C
R1
θ
0.07
-
a
SIDE VIEW
o
o
o
o
C
L
5
15
5
15
-
o
o
o
o
E
1
0
6
0
6
-
α
-B-
0.20 (0.008)
C
D
END VIEW
Rev. 0 12/02
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
-A -
10. Datums
and
to be determined at Datum plane
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6424.1
December 16, 2010
16
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