ISL23315UFUZ-T7A [RENESAS]
Single, Low Voltage Digitally Controlled Potentiometer (XDCP™); MSOP10, uTQFN10; Temp Range: -40° to 125°C;型号: | ISL23315UFUZ-T7A |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | Single, Low Voltage Digitally Controlled Potentiometer (XDCP™); MSOP10, uTQFN10; Temp Range: -40° to 125°C 光电二极管 转换器 |
文件: | 总20页 (文件大小:1096K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATASHEET
ISL23315
FN7778
Rev 2.00
August 12, 2015
Single, Low Voltage Digitally Controlled Potentiometer (XDCP™)
2
The ISL23315 is a volatile, low voltage, low noise, low power, I C
Features
™
Bus , 256 Taps, single digitally controlled potentiometer (DCP),
which integrates DCP core, wiper switches and control logic on
a monolithic CMOS integrated circuit.
• 256 resistor taps
2
• I C serial interface
- No additional level translator for low bus supply
- Two address pins allow up to four devices per bus
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
• Power supply
2
I C bus interface. The potentiometer has an associated
- V = 1.7V to 5.5V analog power supply
CC
volatile Wiper Register (WR) that can be directly written to and
read by the user. The contents of the WR controls the position
of the wiper. When powered on, the ISL23315’s wiper will
always commence at mid-scale (128 tap position).
2
- V
LOGIC
= 1.2V to 5.5V I C bus/logic power supply
• Wiper resistance: 70 typical @ V = 3.3V
CC
• Shutdown Mode - forces the DCP into an end-to-end open
The low voltage, low power consumption, and small package
of the ISL23315 make it an ideal choice for use in battery
circuit and R is shorted to R internally
W
L
• Power-on preset to mid-scale (128 tap position)
• Shutdown and standby current <2.8µA max
operated equipment. In addition, the ISL23315 has a V
LOGIC
pin allowing down to 1.2V bus operation, independent from the
value. This allows for low logic levels to be connected
V
CC
directly to the ISL23315 without passing through a voltage
level shifter.
• DCP terminal voltage from 0V to V
CC
• 10k 50kor 100k total resistance
• Extended industrial temperature range: -40°C to +125°C
• 10 Ld MSOP or 10 Ld µTQFN packages
• Pb-free (RoHS compliant)
The DCP can be used as a three-terminal potentiometer or as a
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal processing.
Applications
• Power supply margining
• RF power amplifier bias compensation
• LCD bias compensation
• Laser diode bias compensation
10000
8000
6000
4000
2000
0
0
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 2. V
ADJUSTMENT
REF
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP
POSITION, 10k DCP
FN7778 Rev 2.00
August 12, 2015
Page 1 of 20
ISL23315
Block Diagram
V
V
CC
LOGIC
R
SCL
SDA
A1
H
POWER-UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC
I/O
BLOCK
LEVEL
SHIFTER
WR
VOLATILE
REGISTER
AND
A0
WIPER
CONTROL
CIRCUITRY
R
L
R
W
GND
Pin Configurations
Pin Descriptions
MSOP
µTQFN
SYMBOL
DESCRIPTION
ISL23315
(10 LD MSOP)
TOP VIEW
2
1
10
V
I C bus /logic supply. Range 1.2V to
5.5V
LOGIC
10
9
GND
V
1
2
3
4
5
2
3
1
2
SCL
SDA
Logic Pin - Serial bus clock input
LOGIC
SCL
V
CC
Logic Pin - Serial bus data
input/open drain output
8
RH
RW
RL
SDA
A0
7
4
5
3
4
A0
A1
Logic Pin - Hardwire slave address
2
A1
6
pin for I C serial bus.
Range: V
or GND
LOGIC
ISL23315
Logic Pin - Hardwire slave address
2
(10 LD µTQFN)
TOP VIEW
pin for I C serial bus.
Range: V
or GND
LOGIC
6
7
8
9
5
6
7
8
RL
RW
RH
DCP “low” terminal
DCP wiper terminal
DCP “high” terminal
GND
SCL
1
2
3
4
9
8
7
6
V
Analog power supply.
Range 1.7V to 5.5V
CC
V
SDA
A0
CC
RH
10
9
GND
Ground pin
A1
RW
FN7778 Rev 2.00
August 12, 2015
Page 2 of 20
ISL23315
Ordering Information
RESISTANCE
OPTION
(kΩ)
TEMP
RANGE
(°C)
PART NUMBER
(Note 5)
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL23315TFUZ (Notes 1, 3)
3315T
3315U
100
50
-40 to +125 10 Ld MSOP
-40 to +125 10 Ld MSOP
M10.118
M10.118
ISL23315UFUZ (Notes 1, 3)
(No longer available, recommended replacement: ISL23315TFUZ-TK)
ISL23315WFUZ (Notes 1, 3)
3315W
HB
10
100
100
50
-40 to +125 10 Ld MSOP
M10.118
ISL23315TFRUZ-T7A (Notes 2, 4)
ISL23315TFRUZ-TK (Notes 2, 4)
-40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A
-40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A
-40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A
HB
ISL23315UFRUZ-T7A (Notes 2, 4)
HA
(No longer available, recommended replacement: ISL23315TFUZ-TK)
ISL23315UFRUZ-TK (Notes 2, 4)
(No longer available, recommended replacement: ISL23315TFUZ-TK)
HA
GZ
GZ
50
10
10
-40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A
-40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A
-40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A
ISL23315WFRUZ-T7A (Notes 2, 4)
(No longer available, recommended replacement: ISL23315TFUZ-TK)
ISL23315WFRUZ-TK (Notes 2, 4)
(No longer available, recommended replacement: ISL23315TFUZ-TK)
NOTES:
1. Add “-TK” or “-T7A” suffix for Tape and Reel option. Please refer to TB347 for details on reel specifications.
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL23315. For more information on MSL please see techbrief TB363.
FN7778 Rev 2.00
August 12, 2015
Page 3 of 20
ISL23315
Absolute Maximum Ratings
Thermal Information
Supply Voltage Range
Thermal Resistance (Typical)
10 Ld MSOP Package (Notes 6, 7). . . . . . .
10 Ld µTQFN Package (Notes 6, 7) . . . . . .
JA (°C/W)
170
JC (°C/W)
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
70
90
CC
LOGIC
145
Voltage on Any DCP Terminal Pin. . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Wiper current I (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
W
ESD Rating
Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . .6.5kV
CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 200V
Latch Up
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
(Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . 100mA @ +125°C
V
V
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V
CC
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V
LOGIC
DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to V
CC
Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
7. For , the “case temp” location is the center top of the package.
JC
Analog Specifications
V
= 2.7V to 5.5V, V
= 1.2V to 5.5V over recommended operating conditions unless otherwise
LOGIC
CC
stated. Boldface limits apply over the operating temperature range, -40°C to +125°C.
MIN
TYP
MAX
SYMBOL
PARAMETER
to R Resistance
TEST CONDITIONS
(Note 20)
(Note 8)
(Note 20)
UNITS
k
R
R
W option
U option
T option
10
50
TOTAL
H
L
k
100
±2
k
R
to R Resistance Tolerance
-20
+20
%
H
L
End-to-End Temperature Coefficient
W option
U option
T option
175
85
ppm/°C
ppm/°C
ppm/°C
V
70
V
, V
RH RL
DCP Terminal Voltage
Wiper Resistance
V
or V to GND
RL
0
V
RH
CC
R
R
- floating, V = 0V, force I current
RL
70
200
W
H
W
to the wiper,
= (V - V )/R
TOTAL,
I
W
CC RL
V
= 2.7V to 5.5V
CC
V
= 1.7V
580
32
pF
CC
C /C /C
W
Terminal Capacitance
Leakage on DCP Pins
Resistor Noise Density
See “DCP Macro Model” on page 9
Voltage at pin from GND to V
H
L
I
-0.4
< 0.1
16
0.4
µA
LkgDCP
Noise
CC
Wiper at middle point, W option
Wiper at middle point, U option
Wiper at middle point, T option
nV Hz
nV Hz
nV Hz
dB
49
61
Feed Thru Digital Feed-through from Bus to Wiper Wiper at middle point
-65
PSRR
Power Supply Reject Ratio
Wiper output change if V change
CC
-75
dB
±10%; wiper at middle point
FN7778 Rev 2.00
August 12, 2015
Page 4 of 20
ISL23315
Analog Specifications
V
= 2.7V to 5.5V, V
= 1.2V to 5.5V over recommended operating conditions unless otherwise
LOGIC
CC
stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 20)
(Note 8)
(Note 20)
UNITS
VOLTAGE DIVIDER MODE (0V @ RL; V @ RH; measured at RW, unloaded)
CC
Integral Non-linearity, Guaranteed
(Note 13) Monotonic
INL
W option
U, T option
W option
U, T option
W option
U, T option
W option
U, T option
-1.0
-0.5
-1
±0.5
±0.15
±0.4
±0.1
-2
+1.0
+0.5
+1
LSB
(Note 9)
LSB
(Note 9)
DNL
Differential Non-linearity, Guaranteed
LSB
(Note 9)
(Note 12) Monotonic
-0.4
-3.5
-2
+0.4
0
LSB
(Note 9)
FSerror
Full-scale Error
LSB
(Note 9)
(Note 11)
-0.5
2
0
LSB
(Note 9)
ZSerror
Zero-scale Error
0
3.5
2
LSB
(Note 9)
(Note 10)
0
0.4
LSB
(Note 9)
TC
Ratiometric Temperature Coefficient
W option, Wiper Register set to 80 hex
U option, Wiper Register set to 80 hex
T option, Wiper Register set to 80 hex
From code 0 to FF hex
8
4
ppm/°C
ppm/°C
ppm/°C
ns
V
(Notes 14)
2.3
Large Signal Wiper Settling Time
-3dB Cutoff Frequency
300
1200
250
120
f
Wiper at middle point W option
Wiper at middle point U option
Wiper at middle point T option
kHz
cutoff
kHz
kHz
RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected)
R
Integral Non-linearity, Guaranteed
W option; V = 2.7V to 5.5V
CC
-2.0
-1.0
-1
±1
10.5
±0.3
2.1
+2.0
+1.0
+1
MI
(Note 15)
INL
(Note 18) Monotonic
W option; V = 1.7V
CC
MI
(Note 15)
U, T option; V = 2.7V to 5.5V
CC
MI
(Note 15)
U, T option; V = 1.7V
CC
MI
(Note 15)
R
Differential Non-linearity, Guaranteed
W option; V = 2.7V to 5.5V
CC
±0.4
±0.6
±0.15
±0.35
MI
(Note 15)
DNL
(Note 17) Monotonic
W option; V = 1.7V
CC
MI
(Note 15)
U, T option; V = 2.7V to 5.5V
CC
-0.5
+0.5
MI
(Note 15)
U, T option; V = 1.7V
CC
MI
(Note 15)
FN7778 Rev 2.00
August 12, 2015
Page 5 of 20
ISL23315
Analog Specifications
V
= 2.7V to 5.5V, V
= 1.2V to 5.5V over recommended operating conditions unless otherwise
LOGIC
CC
stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
W option; V = 2.7V to 5.5V
(Note 20)
(Note 8)
(Note 20)
UNITS
R
Offset, Wiper at 0 Position
0
0
3
5.5
2
MI
(Note 15)
offset
CC
(Note 16)
W option; V = 1.7V
CC
6.3
0.5
1.1
220
100
75
MI
(Note 15)
U, T option; V = 2.7V to 5.5V
CC
MI
(Note 15)
U, T option; V = 1.7V
CC
MI
(Note 15)
TCR
(Note 19)
Resistance Temperature Coefficient
W option; Wiper register set between
32 hex and FF hex
ppm/°C
ppm/°C
ppm/°C
U option; Wiper register set between 32
hex and FF hex
T option; Wiper register set between 32
hex and FF hex
Operating Specifications V = 2.7V to 5.5V, V
= 1.2V to 5.5V over recommended operating conditions unless otherwise
LOGIC
CC
stated. Boldface limits apply over the operating temperature range, -40°C to +125°C.
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 20)
(Note 8)
(Note 20)
UNITS
µA
I
V
Supply Current (Write/Read)
V
= 5.5V, V = 5.5V,
CC
200
LOGIC
LOGIC
LOGIC
2
f
= 400 kHz (for I C active read and
SCL
write)
V
= 1.2V, V = 1.7V,
CC
= 400 kHz (for I C active read and
5
µA
LOGIC
2
f
SCL
write)
I
V
V
Supply Current (Write/Read)
V
V
V
= 5.5V, V = 5.5V
CC
18
10
µA
µA
µA
CC
CC
LOGIC
LOGIC
LOGIC
= 1.2V, V = 1.7V
CC
I
Standby Current
= V = 5.5V,
CC
1.3
LOGIC SB
LOGIC
2
I C interface in standby
V
= 1.2V, V = 1.7V,
0.4
1.5
1
µA
µA
µA
µA
µA
µA
µA
LOGIC
CC
2
I C interface in standby
I
I
V
V
V
Standby Current
V = V = 5.5V,
LOGIC CC
CC SB
CC
2
I C interface in standby
V
= 1.2V, V = 1.7V,
LOGIC
CC
2
I C interface in standby
Shutdown Current
V
= V = 5.5V,
LOGIC CC
1.3
0.4
1.5
1
LOGIC
LOGIC
2
I C interface in standby
SHDN
V
= 1.2V, V = 1.7V,
LOGIC
CC
2
I C interface in standby
I
Shutdown Current
V = V = 5.5V,
LOGIC CC
CC SHDN
CC
2
I C interface in standby
V
= 1.2V, V = 1.7V,
LOGIC
CC
2
I C interface in standby
FN7778 Rev 2.00
August 12, 2015
Page 6 of 20
ISL23315
Operating Specifications V = 2.7V to 5.5V, V
= 1.2V to 5.5V over recommended operating conditions unless otherwise
LOGIC
CC
stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
Wiper Response Time
TEST CONDITIONS
(Note 20)
(Note 8)
(Note 20)
UNITS
µs
t
W option; SCL rising edge of the
acknowledge bit after data byte to wiper
new position from 10% to 90% of the
final value.
0.4
1.5
3.5
DCP
U option; SCL rising edge of the
acknowledge bit after data byte to wiper
new position from 10% to 90% of the
final value.
µs
µs
T option; SCL rising edge of the
acknowledge bit after data byte to wiper
new position from 10% to 90% of the
final value.
I
Leakage Current, at Pins A0, A1, SDA,
SCL
Voltage at pin from GND to V
LOGIC
-0.4
<0.1
1.5
0.4
50
µA
µs
LkgDig
tShdnRec DCP Recall Time from Shutdown Mode SCL rising edge of the acknowledge bit
after ACR data byte to wiper recalled
position and RH connection
V
V
V
V Ramp Rate
Ramp monotonic at any level
0.01
V/ms
CC, LOGIC
CC , LOGIC
Ramp
(Note 21)
Serial Interface Specification for SCL, SDA, A0, A1 Unless Otherwise Noted.
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
SYMBOL
PARAMETER
Input LOW Voltage
TEST CONDITIONS
UNITS
V
-0.3
0.3 x V
V
V
V
IL
LOGIC
+ 0.3
V
Input HIGH Voltage
0.7 x V
LOGIC
V
LOGIC
IH
Hysteresis
SDA and SCL Input Buffer
Hysteresis
V
V
> 2V
<2V
0.05 x V
LOGIC
LOGIC
LOGIC
LOGIC
0.1 x V
0
V
SDA Output Buffer LOW Voltage
I
I
= 3mA, V
> 2V
LOGIC
0.4
V
V
OL
OL
= 1.5mA,
0.2 x V
OL
LOGIC
V
<2V
LOGIC
C
SDA, SCL Pin Capacitance
SCL Frequency
10
pF
kHz
ns
pin
f
400
SCL
t
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the
max spec is suppressed
50
sp
t
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30%
900
ns
ns
AA
of V
, until SDA exits the
LOGIC
30% to 70% of V
window
LOGIC
LOGIC
t
Time the Bus Must be Free Before SDA crossing 70% of V
1300
BUF
the Start of a New Transmission
during a STOP condition, to
SDA crossing 70% of V
LOGIC
during the following START
condition
t
Clock LOW Time
Measured at the 30% of
1300
600
ns
ns
ns
LOW
V
crossing
LOGIC
Measured at the 70% of
crossing
t
Clock HIGH Time
HIGH
V
LOGIC
t
START Condition Set-up Time
SCL rising edge to SDA falling
edge; both crossing 70% of
600
SU:STA
V
LOGIC
FN7778 Rev 2.00
August 12, 2015
Page 7 of 20
ISL23315
Serial Interface Specification for SCL, SDA, A0, A1 Unless Otherwise Noted. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 20)
(Note 8)
(Note 20)
UNITS
ns
t
START Condition Hold Time
From SDA falling edge
600
HD:STA
crossing 30% of V
to SCL
LOGIC
falling edge crossing 70% of
V
LOGIC
From SDA exiting the 30% to
70% of V window, to SCL
t
Input Data Set-up Time
100
ns
SU:DAT
HD:DAT
LOGIC
rising edge crossing 30% of
V
LOGIC
From SCL falling edge crossing
70% of V to SDA entering
t
Input Data Hold Time
0
600
1300
0
ns
ns
ns
ns
CC
the 30% to 70% of V window
CC
t
STOP Condition Set-up Time
From SCL rising edge crossing
SU:STO
HD:STO
70% of V
, to SDA rising
LOGIC
edge crossing 30% of V
LOGIC
t
STOP Condition Hold Time for Read From SDA rising edge to SCL
or Write
falling edge; both crossing
70% of V (Note 11)
CC
t
Output Data Hold Time
From SCL falling edge crossing
DH
30% of V
, until SDA
LOGIC
enters the 30% to 70% of
window.
V
LOGIC
I
I
= 3mA, V
= 0.5mA, V
> 2V.
< 2V
OL
OL
LOGIC
LOGIC
t
SDA and SCL Rise Time
SDA and SCL Fall Time
From 30% to 70% of V
From 70% to 30% of V
20 + 0.1 x Cb
20 + 0.1 x Cb
10
250
250
400
ns
ns
pF
R
LOGIC
LOGIC
t
F
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
(Note 11)
t
A1, A0 Setup Time
A1, A0 Hold Time
Before START condition
After STOP condition
600
600
ns
ns
SU:A
t
HD:A
NOTES:
8. Typical values are for T = +25°C and 3.3V supply voltages.
A
9. LSB = [V(RW)
255
– V(RW) ]/255. V(RW)
and V(RW) are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental
255 0
0
voltage when changing from one tap to an adjacent tap.
10. ZS error = V(RW) /LSB.
0
11. FS error = [V(RW)
255
– V ]/LSB.
CC
12. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 255. i is the DCP register setting.
i-1
i
13. INL = [V(RW) – i • LSB – V(RW) ]/LSB for i = 1 to 255
i
0
14.
MaxVRW – MinVRW
for i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
voltage and Min( ) is the minimum value of the wiper voltage over the temperature range.
6
10
i
i
----------------------------------------------------------------------------- ---------------------
TC
=
V
VRW +25°C
+165°C
– RW |/255. MI is a minimum increment. RW
i
15. MI = |RW
and RW are the measured resistances for the DCP register set to FF hex and 00
0
255
hex respectively.
0
255
16. Roffset = RW /MI, when measuring between RW and RL.
0
Roffset = RW
/MI, when measuring between RW and RH.
255
17. RDNL = (RW – RW )/MI -1, for i = 16 to 255.
i-1
i
18. RINL = [RW – (MI • i) – RW ]/MI, for i = 16 to 255.
i
0
6
19.
for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the
minimum value of the resistance over the temperature range.
MaxRi – MinRi
10
+165°C
------------------------------------------------------ ---------------------
TC
=
R
Ri+25°C
20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
21. It is preferable to ramp up both the V and the V supplies at the same time. If this is not possible it is recommended to ramp-up the V
LOGIC
CC LOGIC
first followed by the V
.
CC
FN7778 Rev 2.00
August 12, 2015
Page 8 of 20
ISL23315
DCP Macro Model
R
TOTAL
RH
RL
C
L
C
H
C
W
32pF
32pF
32pF
RW
Timing Diagrams
SDA vs SCL Timing
t
sp
t
t
t
t
R
F
HIGH
LOW
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA
(INPUT TIMING)
t
t
t
BUF
AA
DH
SDA
(OUTPUT TIMING)
A0 and A1 Pin Timing
STOP
START
SCL
CLK 1
SDA
t
t
HD:A
SU:A
A0, A1
FN7778 Rev 2.00
August 12, 2015
Page 9 of 20
ISL23315
Typical Performance Curves
0.4
0.30
0.15
0
0.2
0
-0.2
-0.4
-0.15
-0.30
0
50
100
150
200
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 4. 50k DNL vs TAP POSITION, V = 5V
CC
FIGURE 3. 10k DNL vs TAP POSITION, V = 5V
CC
0.4
0.2
0
0.30
0.15
0
-0.2
-0.4
-0.15
-0.30
0
50
100
150
200
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 6. 50k INL vs TAP POSITION, V = 5V
CC
FIGURE 5. 10k INL vs TAP POSITION, V = 5V
CC
0.4
0.2
0
0.30
0.15
0
-0.2
-0.4
-0.15
-0.30
0
50
100
150
200
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 8. 50k RDNL vs TAP POSITION, V = 5V
CC
FIGURE 7. 10k RDNL vs TAP POSITION, V = 5V
CC
FN7778 Rev 2.00
August 12, 2015
Page 10 of 20
ISL23315
Typical Performance Curves (Continued)
0.6
0.30
0.15
0
0.4
0.2
0
-0.2
-0.4
-0.6
-0.15
-0.30
0
50
100
150
200
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 9. 10k RINL vs TAP POSITION, V = 5V
CC
FIGURE 10. 50k RINL vs TAP POSITION, V = 5V
CC
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
+125°C
+125°C
+25°C
+25°C
-40°C
-40°C
0
50
100
150
200
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 12. 50k WIPER RESISTANCE vs TAP POSITION, V = 5V
CC
FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, V = 5V
CC
300
250
200
150
100
50
70
60
50
40
30
20
10
0
0
15
65
115
165
215
15
65
115
165
215
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 13. 10k TCv vs TAP POSITION
FIGURE 14. 50k TCv vs TAP POSITION
FN7778 Rev 2.00
August 12, 2015
Page 11 of 20
ISL23315
Typical Performance Curves (Continued)
600
200
150
100
50
500
400
300
200
100
0
0
15
15
65
115
165
215
65
115
165
215
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 15. 10k TCr vs TAP POSITION
FIGURE 16. 50k TCr vs TAP POSITION
35
30
25
20
15
10
5
120
90
60
30
0
0
15
65
115
165
215
15
65
115
165
215
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 17. 100k TCv vs TAP POSITION
FIGURE 18. 100k TCr vs TAP POSITION
SCL CLOCK
RW PIN
10mV/DIV
1µs/DIV
20mV/DIV
5µs/DIV
FIGURE 20. WIPER TRANSITION GLITCH
FIGURE 19. WIPER DIGITAL FEED-THROUGH
FN7778 Rev 2.00
August 12, 2015
Page 12 of 20
ISL23315
Typical Performance Curves (Continued)
1V/DIV
1V/DIV
0.1s/DIV
1µs/DIV
WIPER
SCL 9TH CLOCK OF THE
DATA BYTE (ACK)
FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME
FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE
1.2
1.0
0.8
CH1: 0.5V/DIV, 0.2µs/DIV RH PIN
CH2: 0.2V/DIV, 0.2µs/DIV RW PIN
V
= 5.5V, V
= 5.5V
LOGIC
CC
0.6
0.4
0.2
0
V
= 1.7V, V
= 1.2V
LOGIC
CC
R
= 10k
TOTAL
-40
-15
10
35
60
85
110
-3dB FREQUENCY = 1.4MHz AT MIDDLE TAP
TEMPERATURE (°C)
FIGURE 24. STANDBY CURRENT vs TEMPERATURE
FIGURE 23. 10k -3dB CUT OFF FREQUENCY
Bus Interface Pins
Functional Pin Descriptions
Potentiometers Pins
SERIAL DATA INPUT/OUTPUT (SDA)
2
The SDA is a bidirectional serial data input/output pin for I C
interface. It receives device address, operation code, wiper
address and data from an I C external master device at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.
RH AND RL
2
The high (R ) and low (R ) terminals of the ISL23315 are
H
L
equivalent to the fixed terminals of a mechanical potentiometer.
R and R are referenced to the relative position of the wiper and
H
L
not the voltage potential on the terminals. With WR set to 255
decimal, the wiper will be closest to R , and with the WR set to 0,
the wiper is closest to R .
SDA requires an external pull-up resistor, since it is an open drain
input/output.
H
L
SERIAL CLOCK (SCL)
RW
2
This input is the serial clock of the I C serial interface. SCL
requires an external pull-up resistor, since a master is an open
drain output.
RW is the wiper terminal, and it is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.
FN7778 Rev 2.00
August 12, 2015
Page 13 of 20
ISL23315
DEVICE ADDRESS (A1, A0)
Memory Description
The address inputs are used to set the least significant 2 bits of
The ISL23315 contains two volatile 8-bit registers: Wiper Register
(WR) and Access Control Register (ACR). The memory map of
ISL23315 is shown in Table 1. The Wiper Register (WR) at address 0
contains current wiper position. The Access Control Register (ACR)
at address 10h contains information and control bits described
in Table 2.
2
the 7-bit I C interface slave address. A match in the slave
address serial data stream must match with the Address input
pins in order to initiate communication with the ISL23315. A
maximum of four ISL23315 devices may occupy the I C serial
2
bus (see Table 3).
V
TABLE 1. MEMORY MAP
LOGIC
This is an input pin, that supplies internal level translator for
serial bus operation from 1.2V to 5.5V.
ADDRESS
(hex)
VOLATILE
REGISTER NAME
DEFAULT SETTING
(hex)
10
0
ACR
WR
40
40
Principles of Operation
The ISL23315 is an integrated circuit incorporating one DCP with
2
its associated registers and an I C serial interface providing
TABLE 2. ACCESS CONTROL REGISTER (ACR)
direct communication between a host and the potentiometer.
The resistor array is comprised of individual resistors connected
in series. At either end of the array and between each resistor is
an electronic switch that transfers the potential at that point to
the wiper.
BIT #
7
0
6
5
0
4
0
3
0
2
0
1
0
0
0
NAME/
VALUE
SHDN
Shutdown Function
The electronic switches on the device operate in a “make before
break” mode when the wiper changes tap positions.
The SHDN bit (ACR[6]) disables or enables shutdown mode for all
DCP channels simultaneously. When this bit is 0, i.e., DCP is forced
to end-to-end open circuit and RW is connected to RL through a
2kΩ serial resistor, as shown in Figure 25. Default value of the
SHDN bit is 1.
Voltage at any DCP pins, R , R or R , should not exceed V
CC
H
L
W
level at any conditions during power-up and normal operation.
2
The V
pin needs to be connected to the I C bus supply
LOGIC
which allows reliable communication with the wide range of
RH
microcontrollers and independent of the V level. This is
CC
extremely important in systems where the master supply has
lower levels than DCP analog supply.
DCP Description
RW
The DCP is implemented with a combination of resistor elements
and CMOS switches. The physical ends of each DCP are
2kΩ
equivalent to the fixed terminals of a mechanical potentiometer
(RH and RL pins). The RW pin of the DCP is connected to
intermediate nodes, and is equivalent to the wiper terminal of a
mechanical potentiometer. The position of the wiper terminal
within the DCP is controlled by an 8-bit volatile Wiper Register
(WR). When the WR of a DCP contains all zeroes (WR[7:0]= 00h),
its wiper terminal (RW) is closest to its “Low” terminal (RL). When
the WR register of a DCP contains all ones (WR[7:0]= FFh), its
wiper terminal (RW) is closest to its “High” terminal (RH). As the
value of the WR increases from all zeroes (0) to all ones (255
decimal), the wiper moves monotonically from the position
closest to RL to the position closest to RH. At the same time, the
resistance between RW and RL increases monotonically, while
the resistance between RH and RW decreases monotonically.
RL
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
In the shutdown mode, the RW terminal is shorted to the RL
terminal with around 2kΩ resistance, as shown in Figure 25. When
the device enters shutdown, all current DCP WR settings are
maintained. When the device exits shutdown, the wipers will return
to the previous WR settings after a short settling time (see
Figure 26).
In shutdown mode, if there is a glitch on the power supply which
causes it to drop below 1.3V for more than 0.2µs to 0.4µs, the
wipers will be RESET to their mid position. This is done to avoid
an undefined state at the wiper outputs.
While the ISL23315 is being powered up, the WR is reset to 80h
(128 decimal), which locates RW roughly at the center between
R and R .
L
H
2
The WR can be read or written to directly using the I C serial
interface as described in the following sections.
FN7778 Rev 2.00
August 12, 2015
Page 14 of 20
ISL23315
2
All I C interface operations must begin with a START condition,
which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The
ISL23315 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 27). A START condition is ignored
during the power-up of the device.
POWER-UP
USER PROGRAMMED
MID SCALE = 80H
AFTER SHDN
2
All I C interface operations must be terminated by a STOP
SHDN RELEASED
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 27). A STOP condition at the end of a read
operation or at the end of a write operation places the device in
its standby mode.
SHDN ACTIVATED
WIPER RESTORE TO
THE ORIGINAL POSITION
SHDN MODE
TIME (s)
0
An ACK (Acknowledge) is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data
(see Figure 28).
FIGURE 26. SHUTDOWN MODE WIPER RESPONSE
2
I C Serial Interface
2
The ISL23315 supports an I C bidirectional bus oriented
protocol. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the device
being controlled is the slave. The master always initiates data
transfers and provides the clock for both transmit and receive
operations. Therefore, the ISL23315 operates as a slave device
in all applications.
The ISL23315 responds with an ACK after recognition of a START
condition followed by a valid Identification Byte, and once again
after successful receipt of an Address Byte. The ISL23315 also
responds with an ACK after receiving a Data Byte of a write
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
2
All communication over the I C interface is conducted by sending
A valid Identification Byte contains 10100 as the five MSBs, and
the following two bits matching the logic values present at pins
A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a
Read operation and “0” for a Write operation (see Table 3).
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 27). On
power-up of the ISL23315, the SDA pin is in the input mode.
TABLE 3. IDENTIFICATION BYTE FORMAT
LOGIC VALUES AT PINS A1 AND A0, RESPECTIVELY
1
0
1
0
0
A1
A0
R/W
(MSB)
(LSB)
SCL
SDA
START
DATA
DATA
DATA
STOP
STABLE
CHANGE STABLE
FIGURE 27. VALID DATA CHANGES, START AND STOP CONDITIONS
FN7778 Rev 2.00
August 12, 2015
Page 15 of 20
ISL23315
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
S
T
A
R
T
SIGNALS FROM
THE MASTER
S
T
O
P
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
SIGNAL AT SDA
1 0 1 0 0 A1A0 0
0 0 0
SIGNALS FROM
THE SLAVE
A
C
K
A
C
K
A
C
K
FIGURE 29. BYTE WRITE SEQUENCE
READ
S
T
A
R
T
S
T
A
R
T
SIGNALS
FROM THE
MASTER
S
T
O
P
A
C
K
A
C
K
IDENTIFICATION
BYTE WITH
R/W = 0
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
ADDRESS
BYTE
SIGNAL AT SDA
1 0 1 0 0A1A0 0
0 0 0
1 0 1
0 A1A0 1
0
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 30. READ SEQUENCE
FN7778 Rev 2.00
August 12, 2015
Page 16 of 20
ISL23315
Write Operation
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition. After each of the three bytes, the ISL23315 responds
with an ACK. The data is transferred from I C block to the
corresponding register at the 9th clock of the data byte and
device enters its standby state (see Figures 28 and 29).
Applications Information
V
Requirements
LOGIC
It is recommended to keep V
normal operation. In a case where turning V
LOGIC
powered all the time during
OFF is
necessary, it is recommended to ground the V pin of the
LOGIC
LOGIC
2
ISL23315. Grounding the V
pin or both V and V does
LOGIC
LOGIC
CC
not affect other devices on the same bus. It is good practice to
Read Operation
put a 1µF cap in parallel to 0.1µF as close to the V
possible.
pin as
LOGIC
A Read operation consists of a three byte instruction followed by
one or more Data Bytes (see Figure 30). The master initiates the
operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte, a
second START, and a second Identification byte with the R/W bit
set to “1”. After each of the three bytes, the ISL23315 responds
with an ACK; then the ISL23315 transmits Data Byte. The master
terminates the read operation issuing a NACK (ACK) and a STOP
condition following the last bit of the last Data Byte (see
Figure 30).
V
Requirements and Placement
CC
It is recommended to put a 1µF capacitor in parallel with 0.1µF
decoupling capacitor close to the V pin.
CC
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time (<1µs). There
are several code transitions such as 0Fh to 10h, 1Fh to 20h,...,
EFh to FFh, which have higher transient glitch. Note, that all
switching transients will settle well within the settling time as
stated in the datasheet. A small capacitor can be added
externally to reduce the amplitude of these voltage transients.
However, that will also reduce the useful bandwidth of the circuit,
thus may not be a good solution for some applications. It may be
a good idea, in that case, to use fast amplifiers in a signal chain
for fast recovery.
FN7778 Rev 2.00
August 12, 2015
Page 17 of 20
ISL23315
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
FN7778.2
CHANGE
8/12/15
Updated Ordering Information table on page 3
Changed Products section to About Intersil.
Updated POD M10.118 from rev 0 to rev 1. Changes since rev0: Updated to new POD template. Added land
pattern
7/29/11
FN7778.1
On page 7, “Wiper Response Time” changed text in each option
From: CS rising edge to wiper new position, from 10% to 90% of final value.
To: SCL rising edge of the acknowledge bit after data byte to wiper new position from 10% to 90% of the final
value.
07/28/11
12/15/10
Added “Shutdown Function” section and revised “VLOGIC Standby Current” and “VCC Shutdown Current” limits
on page 6.
On page 7, split “Wiper Response Time” up into 3 separate conditions for each option (W, U, T).
FN7778.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2010-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7778 Rev 2.00
August 12, 2015
Page 18 of 20
ISL23315
Package Outline Drawing
M10.118
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 4/12
5
3.0±0.05
A
DETAIL "X"
D
10
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
0.50 BSC
B
GAUGE
PLANE
TOP VIEW
0.25
3°±3°
0.55 ± 0.15
DETAIL "X"
0.85±010
H
C
SEATING PLANE
0.10 C
0.18 - 0.27
0.10 ± 0.05
0.08
C A-B D
M
SIDE VIEW 1
(5.80)
NOTES:
1. Dimensions are in millimeters.
(4.40)
(3.00)
2. Dimensioning and tolerancing conform to JEDEC MO-187-BA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.50)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
(0.29)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
FN7778 Rev 2.00
August 12, 2015
Page 19 of 20
ISL23315
Package Outline Drawing
L10.2.1x1.6A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 3/10
8.
PIN 1
INDEX AREA
2.10
A
PIN #1 ID
8.
0.05 MIN.
B
1
4
1
4X 0.20 MIN.
0.10 MIN.
10
5
0.80
10X 0.40
10 X 0.20
0.10
9
6
2X
6X 0.50
4
TOP VIEW
(10 X 0.20)
0.10 M C A B
M C
BOTTOM VIEW
SEE DETAIL "X"
(0.05 MIN)
(0.10 MIN.)
MAX. 0.55
PACKAGE
OUTLINE
1
0.10 C
C
(10X 0.60)
SEATING PLANE
0.08 C
(2.00)
SIDE VIEW
0 . 125 REF
(0.80)
(1.30)
C
(6X 0.50 )
(2.50)
TYPICAL RECOMMENDED LAND PATTERN
0-0.05
DETAIL "X"
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2. All Dimensions are in millimeters. Angles are in degrees.
Dimensions in ( ) for Reference Only.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Maximum package warpage is 0.05mm.
6. Maximum allowable burrs is 0.076mm in all directions.
7. Same as JEDEC MO-255UABD except:
No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm
Lead Length dim. = 0.45mm max. not 0.42mm.
8. The configuration of the pin #1 identifier is optional, but must be located within
the zone indicated. The pin #1 identifier may be either a mold or mark feature.
FN7778 Rev 2.00
August 12, 2015
Page 20 of 20
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