ISL28114FEV1Z-T7A [RENESAS]
OP-AMP, 6000uV OFFSET-MAX, 5MHz BAND WIDTH, PDSO5, ROHS COMPLIANT, PLASTIC, MO-203AA, EIAJ, SC-70, 5 PIN;
| 型号： | ISL28114FEV1Z-T7A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | OP-AMP, 6000uV OFFSET-MAX, 5MHz BAND WIDTH, PDSO5, ROHS COMPLIANT, PLASTIC, MO-203AA, EIAJ, SC-70, 5 PIN 放大器 光电二极管 |
| 文件： | 总22页 (文件大小：1544K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single, Dual, Quad General Purpose Micropower, RRIO
Operational Amplifiers
ISL28114, ISL28214, ISL28414
Features
The ISL28114, ISL28214, and ISL28414 are single, dual, and
quad channel general purpose micropower, rail-to-rail input
and output operational amplifiers with supply voltage range of
1.8V to 5.5V. Key features are a low supply current of 360µA
maximum per channel at room temperature, a low bias
current and a wide input voltage range, which enables the
ISL28x14 devices to be excellent general purpose op-amps for
a wide range of applications.
• Low Current Consumption . . . . . . . . . . . . . . . . . . . . . . . 360µA
• Wide Supply Range . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V
• Gain Bandwidth Product . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz
• Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20pA, Max.
• Operating Temperature Range. . . . . . . . . . .-40°C to +125°C
• Packages
- ISL28114 (Single) . . . . . . . . . . . . . . . . . . . SC70-5, SOT23-5
- ISL28214 (Dual). . . . . . . . . . . . . . . . . . . . . . . . .MSOP8, SO8
- ISL28414 (Quad) . . . . . . . . . . . . . . . . . . . SOIC14, TSSOP14
The ISL28114 is available in the SC70-5 and SOT23-5
packages, the ISL28214 is in the MSOP8, SO8 packages, and
the ISL28414 is in the TSSOP14, SOIC14 packages. All devices
operate over the extended temperature range of -40°C to
+125°C.
Applications
• Power Supply Control/Regulation
Related Literature
• See AN1519 for “ISL28213/14SOICEVAL2Z Evaluation
Board User’s Guide”
• Process Control
• Signal Ban/Buffers
• Active Filters
• See AN1520 for “ISL28113/14SOT23EVAL1Z Evaluation
Board User’s Guide”
• Current Shunt Sensing
• Trans-impedance Amp
• See AN1542 for “ISL28213/14MSOPEVAL2Z Evaluation
Board User’s Guide”
• See AN1547 for “ISL28414TSSOPEVAL1Z Evaluation Board
User’s Guide”
R
F
100kΩ
LOAD
+5V
R
-
IN
IN-
-
V
OUT
V+
R
SENSE
10kΩ
ISL28x14
R
+
V-
IN
IN+
+
10kΩ
GAIN = 10
R
+
REF
100kΩ
VREF
SINGLE-SUPPLY, LOW-SIDE CURRENT SENSE AMPLIFIER
FIGURE 1. TYPICAL APPLICATION
January 12, 2012
FN6800.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2009-2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL28114, ISL28214, ISL28414
Ordering Information
PART NUMBER
PART
PACKAGE
PKG.
(Notes 2, 3)
MARKING
(Pb-Free)
DWG. #
ISL28114FEZ-T7 (Note 1)
BKA (Note 4)
BKA (Note 4)
BMA (Note 4)
5 Ld SC-70
5 Ld SC-70
5 Ld SC-70
P5.049
P5.049
P5.049
ISL28114FEZ-T7A (Note 1)
Coming Soon
ISL28114FEV1Z-T7 (Note 1)
Coming Soon
BMA (Note 4)
5 Ld SC-70
P5.049
ISL28114FEV1Z-T7A (Note 1)
ISL28114FHZ-T7 (Note 1)
ISL28114FHZ-T7A (Note 1)
ISL28214FUZ
BDBA (Note 4)
BDBA (Note 4)
8214Z
5 Ld SOT-23
5 Ld SOT-23
8 Ld MSOP
8 Ld MSOP
8 Ld SOIC
P5.064A
P5.064A
M8.118A
M8.118A
M8.15E
ISL28214FUZ-T7 (Note 1)
ISL28214FBZ
8214Z
28214 FBZ
ISL28214FBZ-T7 (Note 1)
ISL28214FBZ-T13 (Note 1)
ISL28414FVZ
28214 FBZ
8 Ld SOIC
M8.15E
28214 FBZ
8 Ld SOIC
M8.15E
28414 FVZ
14 Ld TSSOP
14 Ld TSSOP
14 Ld TSSOP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
MDP0044
MDP0044
MDP0044
MDP0027
MDP0027
MDP0027
ISL28414FVZ-T7 (Note 1)
ISL28414FVZ-T13 (Note 1)
ISL28414FBZ
28414 FVZ
28414 FVZ
28414 FBZ
ISL28414FBZ-T7 (Note 1)
ISL28414FBZ-T13 (Note 1)
ISL28114SOT23EVAL1Z
ISL28214MSOPEVAL2Z
ISL28214SOICEVAL2Z
ISL28414TSSOPEVAL1Z
NOTES:
28414 FBZ
28414 FBZ
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28114, ISL28214, ISL28414. For more information on MSL please
see Tech Brief TB363.
4. The part marking is located on the bottom of the part.
Pin Configurations
ISL28114FEZ
(5 LD SC-70)
TOP VIEW
ISL28114FEV1Z
(5 LD SC-70)
TOP VIEW
ISL28114
(5 LD SOT-23)
TOP VIEW
ISL28214
(8 LD MSOP, 8 LD SOIC)
TOP VIEW
1
2
8
7
V +
S
OUT_A
IN-_A
V +
S
V +
S
V +
S
IN+
1
2
3
5
OUT
1
2
3
5
OUT
1
2
3
5
OUT_B
IN-_B
V -
S
V -
S
V -
S
IN+_A
3
4
6
5
OUT
IN-
IN-
IN-
4
IN+
4
IN+
4
IN+_B
V -
S
FN6800.6
January 12, 2012
2
ISL28114, ISL28214, ISL28414
Pin Configurations(Continued)
ISL28414
(14 LD TSSOP, 14 LD SOIC)
TOP VIEW
OUT_A
1
2
3
4
5
6
7
14 OUT_D
IN-_A
IN+_A
13 IN-_D
12 IN+_D
V +
S
11 V -
S
IN+_B
IN-_B
10 IN+_C
9
8
IN-_C
OUT_C
OUT_B
Pin Descriptions
PIN NO.
PIN
NAME
ISL28114FEZ
SC70-5
ISL28114FEV1Z
SC70-5
SOT23-5
MSOP8
SO8
TSSOP14
14 LD SOIC
DESCRIPTION
Output
V+
OUT
V-
OUT
4
1
1
OUT_A
OUT_B
OUT_C
OUT_D
1
7
1
7
8
14
CIRCUIT 1
V -
S
2
2
2
4
11
Negative supply
voltage
V+
V-
CAPACITIVELY
TRIGGERED
ESD CLAMP
CIRCUIT 2
IN+
1
3
5
3
4
5
3
4
5
Positive Input
Negative Input
V+
IN+
V-
IN+_A
IN+_B
IN+_C
IN+_D
3
5
3
5
10
12
IN-
IN-
IN-_A
IN-_B
IN-_C
IN-_D
2
6
2
6
9
CIRCUIT 3
13
V +
8
4
Positive supply
voltage
See “CIRCUIT 2”
S
FN6800.6
January 12, 2012
3
ISL28114, ISL28214, ISL28414
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V
Supply Turn-on Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . .V - 0.5V to V + 0.5V
Thermal Resistance (Typical)
θ
JA (°C/W)
250
θ
JC (°C/W)
N/A
N/A
100
90
5 Ld SC-70 (Notes 5, 6) . . . . . . . . . . . . . . . .
5 Ld SOT-23 (Notes 5, 6) . . . . . . . . . . . . . . .
8 Ld MSOP (Notes 5, 6) . . . . . . . . . . . . . . . .
8 Ld SOIC Package (Notes 5, 6) . . . . . . . . .
14 Ld TSSOP Package (Notes 5, 6) . . . . . .
14 Ld SOIC Package (Notes 5, 6) . . . . . . . .
Ambient Operating Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
225
180
126
120
-
+
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V - 0.5V to V + 0.5V
-
+
ESD Rating
40
50
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V
Machine Model (ISL28114, ISL28214) . . . . . . . . . . . . . . . . . . . . . . . 350V
Machine Model (ISL28414). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2000V
90
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
6. For θ , the “case temp” location is taken at the package top center.
JC
Electrical Specifications V + = 5V, V - = 0V, R = Open, V = V /2, T = +25°C, unless otherwise specified. Boldface limits apply over
S
S
L
CM
S
A
the operating temperature range, -40°C to +125°C, unless otherwise specified.
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 7)
TYP
0.5
2
(Note 7)
UNIT
DC SPECIFICATIONS
V
Input Offset Voltage
-5
-6
5
6
mV
mV
OS
-40°C to +125°C
TCV
OS
Input Offset Voltage Temperature
Coefficient
-40°C to +125°C
10
µV/°C
I
I
Input Offset Current
Input Bias Current
1
3
30
20
pA
pA
pA
pA
pA
V
OS
ISL28114
-20
-100
-20
B
100
20
ISL28214, ISL28414
3
-50
50
Common Mode Input
Voltage Range
- 0.1
5.1
CMRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Output Voltage Swing, High
Output Voltage Swing, Low
VCM = -0.1V to 5.1V
-40°C to +125°C
72
70
dB
dB
dB
dB
V
PSRR
V
= 1.8V to 5.5V
71
S
-40°C to +125°C
R = 10kΩ
70
V
V
V
4.985
4.98
4.993
OH
OL
+
L
V
R = 10kΩ
13
15
20
mV
mV
V
L
Supply Voltage
1.8
5.5
360
400
I
Supply Current per Amplifier
R = OPEN
300
µA
µA
mA
mA
S
L
I
I
Output Source Short Circuit Current R = 10Ω to V-
-31
26
SC+
L
Output Sink Short Circuit Current
R = 10Ω to V+
L
SC-
FN6800.6
January 12, 2012
4
ISL28114, ISL28214, ISL28414
Electrical Specifications V + = 5V, V - = 0V, R = Open, V = V /2, T = +25°C, unless otherwise specified. Boldface limits apply over
S
S
L
CM
S
A
the operating temperature range, -40°C to +125°C, unless otherwise specified. (Continued)
MIN
MAX
PARAMETER
AC SPECIFICATIONS
GBWP
DESCRIPTION
CONDITIONS
(Note 7)
TYP
5
(Note 7)
UNIT
MHz
Gain Bandwidth Product
V = ±2.5V
S
A = 100, R = 100kΩ,
V
F
R
= 1kΩ, R = 10kΩ to V
G
L
CM
e
e
i
V
Peak-to-Peak Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
V
= ±2.5V
12
40
8
µV
P-P
N
N
P-P
S
f = 0.1Hz to 10Hz
V
= ±2.5V
nV/√(Hz)
fA/√(Hz)
S
f = 1kHz
V
= ±2.5V
N
S
f = 1kHz
12
10
Z
Input Impedance
Ω
IN
C
Differential Input Capacitance
Common Mode Input Capacitance
V
= ±2.5V
1.0
pF
pF
in
S
f = 1MHz
1.3
TRANSIENT RESPONSE
SR
Slew Rate
V
V
= 0.5V to 4.5V
2.5
37
42
V/µs
ns
OUT
t , t , Small Signal
Rise Time, t 10% to 90%
r
= ±2.5V
r
f
S
A = +1, V
R = 0Ω, R = 10kΩ, C = 15pF
= 0.05V
,
P-P
V
OUT
Fall Time, t 10% to 90%
f
ns
F
L
L
t
Settling Time to 0.1%, 4V
Step
P-P
V
= ±2.5V
5.6
µs
s
S
A = +1, R = 0Ω, R = 10kΩ,
V
F
L
C = 1.2pF
L
NOTE:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN6800.6
January 12, 2012
5
ISL28114, ISL28214, ISL28414
Typical Performance Curves
V
= ±2.5V, V
CM
= 0V, R = Open, unless otherwise specified.
L
S
50
40
30
20
10
0
10,000
V+ = ±2.5V
A
= 1
V
1000
100
10
-10
-20
-30
-40
SIMULATION
-50
-40
-20
0
20
40
60
80
100 120 140
1
10
100
1k
10k
100k
TEMPERATURE (°C)
FREQUENCY (Hz)
FIGURE 3. INPUT NOISE VOLTAGE SPECTRAL DENSITY
FIGURE 2. INPUT BIAS CURRENT vs TEMPERATURE
120
100
80
20
120
100
80
20
0
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-20
GAIN
GAIN
60
60
-40
40
40
-60
20
20
-80
0
0
-100
-120
-140
-160
-180
V
= ±0.9V
= 100k
= 10pF
V
= ±0.9V
= 100k
= 10pF
+
+
-20
-40
-60
-80
-20
-40
-60
-80
PHASE
PHASE
R
C
R
C
L
L
L
L
SIMULATION
SIMULATION
0.1
1
10
100
1k
10k 100k 1M 10M 100M
0.1
1
10
100
1k
10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
= 100kΩ, C = 10pF, V = ±2.5V
FIGURE 4. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
= 100kΩ, C = 10pF, V = ±0.9V
R
R
L
L
S
L
L
S
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
PSRR+ V = ±0.9V
S
PSRR+ V = ±2.5V
S
PSRR- V = ±2.5V
S
PSRR- V = ±0.9V
S
R
C
= INF
= 4pF
= +1
L
L
A
V
SIMULATION
V
= 100mV
1k
CM
P-P
0.01 0.1
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
100
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 6. CMRR vs FREQUENCY (SIMULATED DATA)
FIGURE 7. PSRR vs FREQUENCY, V = ±0.9V, ±2.5V
S
FN6800.6
January 12, 2012
6
ISL28114, ISL28214, ISL28414
Typical Performance Curves
V
= ±2.5V, V
CM
= 0V, R = Open, unless otherwise specified. (Continued)
L
S
70
1
0
R
= 100, R = 100k
f
g
A
= 1000
V
60
50
40
30
20
10
0
-1
-2
-3
R
= 1k, R = 100k
f
g
A
= 100
V
= ±2.5V
V
+
C
= 4pF
= 10k
L
L
R
-4
-5
V
= 10mV
= 50mV
V
= 50mV
OUT
P-P
OUT
P-P
A
= 10
R
V
V
V
OUT
P-P
= 100mV
= 200mV
-6 V = ±2.5V
S
OUT
P-P
= 10k, R = 100k
g
f
V
C
= 4pF
= +1
OUT
OUT
P-P
L
-7
-8
A
= 1
V
A
V
= 500mV
P-P
V
R
= OPEN, R = 0
R
= 10k
g
f
L
V
= 1V
P-P
OUT
100k
FREQUENCY (Hz)
-9
-10
10
100
1k
10k
1M
10M
100M
100
1k
10k
FREQUENCY (Hz)
100k
1M
10M
100M
FIGURE 9. FREQUENCY RESPONSE vs V
FIGURE 8. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
OUT
7
1
0
V
R
= ±2.5V
= 10k
= +1
S
6
5
L
A
V
-1
-2
-3
-4
C
= 1004pF
V
= 50mV
P-P
L
OUT
4
C
= 474pF
L
3
C
= 224pF
= 104pF
L
2
R
= 4.99k
L
C
L
1
-5
-6
-7
-8
-9
R
R
= 1k
V
= ±2.5V
= 4pF
= +1
0
L
L
+
C
L
-1
-2
-3
C
= 26pF
= 4pF
= 499
L
A
V
V
= 50mV
C
L
R
= 100
OUT
P-P
10k
FREQUENCY (Hz)
L
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100
1k
100k
1M
10M
100M
FIGURE 11. GAIN vs FREQUENCY vs C
FIGURE 10. GAIN vs FREQUENCY vs R
L
L
1
0
140
120
100
80
C
R
= 4pF
= 10k
= +1
-1
-2
-3
-4
-5
-6
-7
-8
-9
L
L
A
V
V
= 50mV
P-P
OUT
V
= ±2.5V
S
60
R -DRIVER = INF
L
V
= ±2.5V
S
R -RECEIVER = 10k
L
40
C
= 4pF
= +1
V
= ±1.75V
= ±1.25V
L
S
A
V
V
20
S
V
= 1V
P-P
SOURCE
V
= ±0.9V
1M
S
0
10
10k
100k
10M
100M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 12. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
FIGURE 13. CROSSTALK, V = ±2.5V
S
FN6800.6
January 12, 2012
7
ISL28114, ISL28214, ISL28414
Typical Performance Curves
V
= ±2.5V, V
CM
= 0V, R = Open, unless otherwise specified. (Continued)
L
S
30
3
20
10
V
= ±2.5V
2
1
S
V
= ±2.5V
S
V
= ±0.9V
0
-10
-20
-30
-40
S
R
C
A
= 10k
= 15pF
= +1
L
L
0
R
C
= 10k
= 15pF
= +1
V
V
L
L
= 50mV
OUT
P-P
-1
-2
-3
A
V
OUT
V
= RAIL
0
1
2
3
4
5
6
7
8
9
10
0
80 160 240 320 400 480 560 640 720 800
TIME (ns)
TIME (µs)
FIGURE 15. LARGE SIGNAL TRANSIENT RESPONSE vs
= ±0.9V, ±2.5V
FIGURE 14. SMALL SIGNAL TRANSIENT RESPONSE, V = ±2.5V
S
R
V
S
L
0.6
0.5
0.4
0.3
0.2
0.1
0
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5
0.1
0
INPUT
OUTPUT @ V = ±2.5V
S
0
R
C
= INF
= 15pF
=10
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
L
L
OUTPUT @ V =±0.9V
S
A
V
R = 9.09k, R = 1k
R
C
= INF
= 15pF
f
g
L
L
AV =10
R = 9.09k, R = 1k
OUTPUT @ V = ±0.9V
S
f
g
OUTPUT @ V = ±2.5V
S
INPUT
-0.1
-0.5
0
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.3 3.6 4.0
TIME (ms)
0
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.3 3.6 4.0
TIME (ms)
FIGURE 17. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
FIGURE 16. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
= ±0.9V, ±2.5V
V
= ±0.9V, ±2.5V
V
S
S
80
70
60
50
40
30
20
10
0
V
= ±2.5V
= 10k
= 1
S
L
R
A
V
V
= 50mV
P-P
OUT
10
100
1k
10k
CAPACITANCE (pF)
FIGURE 18. % OVERSHOOT vs LOAD CAPACITANCE, V = ±2.5V
S
FN6800.6
January 12, 2012
8
ISL28114, ISL28214, ISL28414
Power Dissipation
It is possible to exceed the +125°C maximum junction
temperatures under certain load, power supply conditions and
ambient temperature conditions. It is therefore important to
Applications Information
Functional Description
The ISL28114, ISL28214 and ISL28414 are single dual and
quad, CMOS rail-to-rail input, output (RRIO) micropower
calculate the maximum junction temperature (T
) for all
JMAX
operational amplifiers. They are designed to operate from single
supply (1.8V to 5.5V) or dual supply (±0.9V to ±2.75V). The parts
have an input common mode range that extends 100mV above
and below the power supply voltage rails. The output stage can
swing to within 15mV of the supply rails with a 10kΩ load.
applications to determine if power supply voltages, load
conditions, or package type need to be modified to remain in the
safe operating area. These parameters are related using
Equation 1:
(EQ. 1)
T
= T
+ θ xPD
MAX JA MAXTOTAL
JMAX
Input ESD Diode Protection
where:
• P
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. For applications where
the input differential voltage is expected to exceed 0.5V, an
external series resistor must be used to ensure the input currents
never exceed 20mA (see Figure 19).
is the sum of the maximum power dissipation of
DMAXTOTAL
each amplifier in the package (PD
)
MAX
• PD
PD
for each amplifier can be calculated using Equation 2:
MAX
V
OUTMAX
R
L
------------------------
= V × I
+ (V - V
) ×
MAX
S
qMAX
S
OUTMAX
(EQ. 2)
where:
R
F
• T
= Maximum ambient temperature
V+
MAX
• θ = Thermal resistance of the package
JA
R
R
-
IN
-
V
-
IN
• PD
= Maximum power dissipation of 1 amplifier
• V = Total supply voltage
MAX
+
IN
+
S
R
L
• I
qMAX
= Maximum quiescent supply current of 1 amplifier
= Maximum output voltage swing of the application
R
G
V-
• V
OUTMAX
• R = Load resistance
L
FIGURE 19. INPUT ESD DIODE CURRENT LIMITING
ISL28114, ISL28214 and ISL28414 SPICE
Model
Output Phase Reversal
Figure 21 shows the SPICE model schematic and Figure 22 shows
the net list for the SPICE model. The model is a simplified version
of the actual device and simulates important AC and DC
parameters. AC parameters incorporated into the model are: 1/f
and flatband noise, Slew Rate, CMRR, Gain and Phase. The DC
parameters are IOS, total supply current and output voltage swing.
The model uses typical parameters given in the “Electrical
Specifications” Table beginning on page 4. The AVOL is adjusted
for 90dB with the dominate pole at 125Hz. The CMRR is set 72dB,
f = 80kHz). The input stage models the actual device to present an
accurate AC representation. The model is configured for ambient
temperature of +25°C.
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28114, ISL28214 and ISL28414 are immune to
output phase reversal, even when the input voltage is 1V beyond
the supplies.
Unused Channels
If the application requires less than all amplifiers one channel,
the user must configure the unused channel(s) to prevent it from
oscillating. The unused channel(s) will oscillate if the input and
output pins are floating. This will result in higher than expected
supply currents and possible noise injection into the channel
being used. The proper way to prevent this oscillation is to short
the output to the inverting input and ground the positive input (as
shown in Figure 20).
Figures 23 through 30 show the characterization vs simulation
results for the Noise Voltage, Closed Loop Gain vs Frequency,
Large Signal 5V Step Response and CMRR and Open Loop Gain
Phase.
-
+
FIGURE 20. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
FN6800.6
January 12, 2012
9
ISL28114, ISL28214, ISL28414
LICENSE STATEMENT
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as “Licensee”, a
nonexclusive, nontransferable licence to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the macro-
model, in whole, in part, or in modified form, to anyone outside
the Licensee’s company. The Licensee may modify the macro-
model to suit his/her specific applications, and the Licensee may
make copies of this macro-model for use within their company
only.
This macro-model is provided “AS IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral, incidental,
or consequential damages in connection with or arising out of
the use of this macro-model. Intersil reserves the right to make
changes to the product and the macro-model without prior
notice.
FN6800.6
January 12, 2012
10
.
V1
1e-6
D3
D1
R10
1e9
G1A
+
2
I2
5e-3
G1
+
-
-
R1
4.0004
R2
4.0004
GAIN = 351
RA1
R11
1
GAIN = 334.753e-3
1
R9
17
V3
15
.61
IN+
Vin+
En
100
D2
R5
10
14
3
4
8R6
En
GAIN = 1
M15
16
NCHANNELMOSFET
9
10
10
12
IN-
R21
30
PMOSISIL
M16 PMOSISIL
M17
M14
NCHANNELMOSFET
28
R22
R23
EOS
5e11
+
-
+
-
D13
GAIN = 1e-3
5
6
11
CinDif
1.02E-12
0
IOS1
25e-12
.61
1
V4
V9
0
29
5e11
Vcm
R24
10
R25
10
R7
4
R8
4
7
0.425
G2A
-
RA2
G2
-
R12
18
1
Vin-
13
+
+
GAIN = 351
GAIN = 334.753e-3
V2
I1
5e-3
1e-6
Voltage Noise Stage
D4
Cin2
Cin1
1.26e-12
1.26e-12
Input Stage
1st Gain Stage
V+
E2
+
-
+
-
GAIN = 1
0
V++
L1
G11
-
D5
D9
D10
+
G7
+
-
C2
2E-9
15.9159E-3
R17
1591.596
C4
R19
50
G3
+
-
G5
+
-
GAIN = 0.02
10e-12
19
R13
21
R15
GAIN = 6.283e-4
V7
GAIN = 24.89e-3
D7
DX
.604
636.6588k
GAIN = 2.5118E-08
24
25
V5
10e3
.08
VOUT
Vg
Vc
23
26
27
Vmid
ISY
300e-6
V8
D8
.604
D X
V6
E4
+
-
+
.08
-
R16
20
R14
G8
-
+
10e3
R18
G4
-
+
636.6588k
C5
G6
-
+
22
1591.596
G12
-
+
R20
50
G9
+
-
G10
+
-
GAIN = 6.283e-4
10e-12
D6
L2
D11
D12
GAIN = 24.89e-3
C3
2E-9
GAIN = 2.5118E-08
15.9159E-3
GAIN = 0.02
GAIN = 0.02
GAIN = 0.02
V--
V-
Correction Current
Sources
E3
+
-
+
-
Common Mode
Gain Stage
with Zero
Output Stage
2nd Gain Stage
Mid Supply ref
V
Pole Stage
GAIN = 1
0
FIGURE 21. SPICE SCHEMATIC
ISL28114, ISL28214, ISL28414
*ISL28114 Macromodel - covers following
*products
*
R_R15 VC 21 10e3
R_R16 22 VC 10e3
*Voltage Noise
*ISL28114
*ISL28214
*ISL28414
**
E_En VIN+ EN 28 0 1
D_D13 29 28 DN
V_V9 29 0 0.425
R_R21 28 0 30
*
R_R22 EN VCM 5e11
R_R23 VCM VIN- 5e11
L_L1 21 V++ 15.9159e-3
L_L2 22 V-- 15.9159e-3
*
*Revision History:
*Revision C, LaFontaine October 20th 2011
*Model for Noise to match measured part,
* quiescent supply currents,
*CMRR 72dB
*fcm=100kHz, AVOL 90dB f=125Hz, SR =
*2.5V/us, GBWP 5MHz, 2nd pole 10Mhz
output voltage clamp and short ckt current
*limit.
*Input Stage
*Pole Stage
M_M14 3 1 5 5 NCHANNELMOSFET
M_M15 4 VIN- 6 6 NCHANNELMOSFET
M_M16 11 VIN- 9 9 PMOSISIL
M_M17 12 1 10 10 PMOSISIL
I_I1 7 V-- DC 5e-3
I_I2 V++ 8 DC 5e-3
I_IOS VIN- 1 DC 25e-12
G_G1A V++ 14 4 3 351
G_G2A V-- 14 11 12 351
V_V1 V++ 2 1e-6
G_G7 V++ 23 VG VMID 6.283e-4
G_G8 V-- 23 VG VMID 6.283e-4
R_R17 23 V++ 1591.596
R_R18 V-- 23 1591.596
C_C4 23 V++ 10e-12
C_C5 V-- 23 10e-12
*
**
*Output Stage with Correction Current
Sources
*Copyright 2011 by Intersil Corporation
*Refer to data sheet "LICENSE
*STATEMENT" Use of this model indicates
*your acceptance with the terms and
*provisions in the License Statement.
*
G_G9 26 V-- VOUT 23 0.02
G_G10 27 V-- 23 VOUT 0.02
G_G11 VOUT V++ V++ 23 0.02
G_G12 V-- VOUT 23 V-- 0.02
V_V7 24 VOUT .08
V_V2 13 V-- 1e-6
R_R1 3 2 4.0004
R_R2 4 2 4.0004
R_R3 5 7 10
*Intended use:
R_R4 7 6 10
V_V8 VOUT 25 .08
*This Pspice Macromodel is intended to give
*typical DC and AC performance
*characteristics under a wide range of
*external circuit configurations using
*compatible simulation platforms - such as
*iSim PE.
R_R5 9 8 10
R_R6 8 10 10
R_R7 13 11 4
R_R8 13 12 4
R_RA1 14 V++ 1
R_RA2 V-- 14 1
D_D7 23 24 DX
D_D8 25 23 DX
D_D9 V++ 26 DX
D_D10 V++ 27 DX
D_D11 V-- 26 DY
D_D12 V-- 27 DY
*
C_CinDif VIN- EN 1.02E-12
C_Cin1 V-- EN 1.26e-12
C_Cin2 V-- VIN- 1.26e-12
*
R_R19 VOUT V++ 50
R_R20 V-- VOUT 50
.model pmosisil pmos (kp=16e-3 vto=-0.6)
.model NCHANNELMOSFET nmos (kp=3e-3
vto=0.6)
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28114
*Device performance features supported by
*this model:
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances
*Open loop gain and phase
*Closed loop bandwidth and frequency
*response
*Loading effects on closed loop frequency
*response
*1st Gain Stage
G_G1 V++ 16 15 VMID 334.753e-3
G_G2 V-- 16 15 VMID 334.753e-3
V_V3 17 16 .61
V_V4 16 18 .61
D_D1 15 VMID DX
D_D2 VMID 15 DX
D_D3 17 V++ DX
*Input noise terms including 1/f effects
*Slew rate
D_D4 V-- 18 DX
R_R9 15 14 100
*Input and Output Headroom limits to I/O
*voltage swing
R_R10 15 VMID 1e9
R_R11 16 V++ 1
*Supply current at nominal specified supply
*voltages
R_R12 V-- 16 1
*
**
*2nd Gain Stage
*Device performance features NOT
*supported by this model
*Harmonic distortion effects
*Disable operation (if any)
*Thermal effects and/or over temperature
*parameter variation
G_G3 V++ VG 16 VMID 24.893e-3
G_G4 V-- VG 16 VMID 24.893e-3
V_V5 19 VG .604
V_V6 VG 20 .604
D_D5 19 V++ DX
D_D6 V-- 20 DX
*Limited performance variation vs. supply
*voltage is modeled
*Part to part performance variation due to
*normal process parameter spread
*Any performance difference arising from
*different packaging
R_R13 VG V++ 636.658e3
R_R14 V-- VG 636.658e3
C_C2 VG V++ 2E-09
C_C3 V-- VG 2E-09
*
*Mid supply Ref
* source
* Connections: +input
E_E4 VMID V-- V++ V-- 0.5
E_E2 V++ 0 V+ 0 1
E_E3 V-- 0 V- 0 1
I_ISY V+ V- DC 300e-6
*
*Common Mode Gain Stage with Zero
G_G5 V++ VC VCM VMID 2.5118E-8
G_G6 V-- VC VCM VMID 2.5118E-8
E_EOS 1 EN VC VMID 1e-3
*
*
*
*
*
|
|
|
|
|
-input
|
|
|
|
+Vsupply
|
|
|
-Vsupply
|
|
output
|
.subckt ISL28114 Vin+ Vin- V+ V- VOUT
* source ISL28114_DS rev2
FIGURE 22. SPICE NET LIST
FN6800.6
January 12, 2012
12
ISL28114, ISL28214, ISL28414
Characterization vs Simulation Results
10,000
10,000
V
= ±2.5V
= 1
V
= ±2.5V
A = 1
V
+
+
A
V
1000
1000
100
10
100
10
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 23. CHARACTERIZED INPUT NOISE VOLTAGE
FIGURE 24. SIMULATED INPUT NOISE VOLTAGE
(A) AC sims.dat (active)
70
60
70
R
= 100, R = 100k
R = 100, R = 100k
g f
g
f
A
= 1000
A
= 1000
= 100
= 10
V
V
60
50
40
30
20
10
0
R
= 1k, R = 100k
f
R
= 1k, R = 100k
f
g
g
A
= 100
= 10
V
A
V
C
R
V
= ±2.5V
= 4pF
= 10k
V
+
L
L
40
20
= 50mV
A
OUT
P-P
V
A
V
R
= 10k, R = 100k
f
R
= 10k, R = 100k
f
g
g
A
= 1
0
V
R
= 100k, R = 100k
f
g
R
= OPEN, R = 0
f
-10
g
-10
10
100
1k
10k
100k
1M
10M
100M
10
100
1.0k
10k
100k
1.0M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 25. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY
FIGURE 26. SIMULATED CLOSED LOOP GAIN vs FREQUENCY
(A) AC sims.dat (active)
3
3
V
= ±2.5V
V
S
OUT
2
1
V
= ±2.5V
2
1
S
V
IN
V
= ±0.9V
S
V(VIN+)/VOUT)
-0
-1
-2
-3
0
R
C
= 10k
= 15pF
= +1
L
L
-1
-2
-3
R
C
= 10k
= 15pF
= +10
L
L
A
V
OUT
V
= RAIL
A
V
OUT
V
= RAIL
0
1
2
3
4
5
6
7
8
9
10
0
5
10
15
TIME (µs)
20
25
30
TIME (µs)
FIGURE 27. CHARACTERIZED LARGE SIGNAL TRANSIENT
RESPONSE vs R , V = ±0.9V, ±2.5V
FIGURE 28. SIMULATED LARGE SIGNAL TRANSIENT RESPONSE vs
R , V = ±0.9V, ±2.5V
L
S
L
S
FN6800.6
January 12, 2012
13
ISL28114, ISL28214, ISL28414
Characterization vs Simulation Results(Continued)
(A) AC2.dat (active)
200
160
120
80
120
100
80
20
0
PHASE
-20
-40
-60
-80
-100
-120
-140
-160
-180
GAIN
60
40
20
0
GAIN
V
= ±0.9V
= 100k
= 10pF
-20
-40
-60
-80
+
PHASE
R
C
= 10k
= 10pF
L
L
40
R
C
L
L
MODEL VOS SET TO ZERO
FOR THIS TEST
SIMULATION
0
0.01 0.1 1.0
10 100 1.0k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
0.1
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 30. SIMULATED (SPICE) OPEN-LOOP GAIN, PHASE vs
FREQUENCY
FIGURE 29. SIMULATED (DESIGN) OPEN-LOOP GAIN, PHASE vs
FREQUENCY
(A) AC sims.dat (active)
80
80
70
60
50
40
30
20
70
60
50
40
30
20
10
0
10
SIMULATION
0
0.01 0.1
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
0.01 0.1
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 31. SIMULATED (DESIGN) CMRR
FIGURE 32. SIMULATED (SPICE) CMRR
FN6800.6
January 12, 2012
14
ISL28114, ISL28214, ISL28414
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to Web to make sure you
have the latest Rev.
DATE
REVISION
FN6800.6
FN6800.5
CHANGE
January 3, 2012
May 18, 2011
Revised “SPICE SCHEMATIC” on page 11 and “SPICE NET LIST” on page 12.
- On page 3, Pin Descriptions: Circuit 3 diagram, removed anti-parallel diodes from the IN+ to IN-
terminals.
- On page 4, Absolute Maximum Ratings: changed Differential Input Voltage from "0.5V" to "V- -
0.5V to V+ + 0.5V"
- On page 4, updated CMRR and PSRR parameters in Electrical Specifications table with test
condition specifying -40°C to 125°C typical parameter.
- On page 5, updated Note 7, referenced in MIN and MAX column headings of Electrical
Specifications table, from "Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not
production tested." to new standard "Compliance to datasheet limits is assured by one or more
methods: production test, characterization and/or design."
- On page 9, under “Input ESD Diode Protection,” removed “They also contain back to-back
diodes across the input terminals.” Removed “Although the amplifier is fully protected, high
input slew rates that exceed the amplifier slew rate (±2.5V/µs) may cause output distortion.”
- On page 9, Figure 19: updated circuit schematic by removing back-to-back input protection
diodes.
- On page 11 replaced SPICE schematic (Figure 21)
- On page 12 replaced SPICE Netlist (Figure 22)
- On page 13 replaced Figure 24
- On page 14 replaced Figure 32
September 23, 2010
FN6800.4
Added new SC70 pinout package extension as follows:
Added to Related Literature on page 1 “See AN1547 for “ISL28414TSSOPEVAL1Z Evaluation
Board User’s Guide”.
Added to ordering information ISL28114FEV1Z-T7 and ISL28114FEV1Z-T7A and Evaluation
boards.
Added to Pin Configurations new pinout for ISL28114FEV1Z.
Added in Pin Descriptions ISL28114FEV1Z SC70 pin description column.
July 28, 2010
May 13, 2010
Changed Note 6 on page page 4 from “For θ , the “case temp” location is the center of the
exposed metal pad on the package underside.” to
JC
“For θ , the “case temp” location is taken at the package top center.”
JC
Added “Related Literature” on page 1.
Changed package outline drawing from MDP0038 to P5.064A on page 2 and page 18.
MDP0038 package contained 2 packages for both the 5 and 6 Ld SOT-23. MDP0038 was
obsoleted and the packages were separated and made into 2 separate package outline
drawings; P5.064A and P6.064A. Changes to the 5 Ld SOT-23 were to move dimensions from
table onto drawing, add land pattern and add JEDEC reference number.
Added Note 4 to “Ordering Information” on page 2.
December 16, 2009
November 17, 2009
November 12, 2009
October 23, 2009
FN6800.3
FN6800.2
FN6800.1
FN6800.0
Removed “Coming Soon” from MSOP package options in the “Ordering Information” on page 2.
Updated the Theta JA for the MSOP package option from 170°C/W to 180°C/W on page 4.
Removed “Coming Soon” from SC70 and SOT-23 package options in the “Ordering Information”
on page 2.
Changed theta Ja to 250 from 300. Added license statement (page 10) and reference in spice
model (page 12).
Initial Release
FN6800.6
January 12, 2012
15
ISL28114, ISL28214, ISL28414
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL28114, ISL28214, ISL28414
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For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
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FN6800.6
January 12, 2012
16
ISL28114, ISL28214, ISL28414
Small Outline Transistor Plastic Packages (SC70-5)
D
P5.049
VIEW C
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
e1
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.043
0.004
0.039
0.012
0.010
0.009
0.009
0.085
0.094
0.053
MIN
0.80
0.00
0.80
0.15
0.15
0.08
0.08
1.85
1.80
1.15
MAX
1.10
0.10
1.00
0.30
0.25
0.22
0.20
2.15
2.40
1.35
NOTES
5
1
4
A
A1
A2
b
0.031
0.000
0.031
0.006
0.006
0.003
0.003
0.073
0.071
0.045
-
-
-
-
E
C
L
C
E1
L
2
3
b
b1
c
e
6
6
3
-
C
L
c1
D
0.20 (0.008) M
C
C
C
L
E
E1
e
3
-
SEATING
PLANE
0.0256 Ref
0.0512 Ref
0.010 0.018
0.65 Ref
1.30 Ref
0.26 0.46
A2
A1
A
e1
L
-
-C-
4
-
L1
L2
0.017 Ref.
0.420 Ref.
0.10 (0.004)
C
0.006 BSC
o
0.15 BSC
o
o
o
0
8
0
8
-
α
N
b
WITH
5
5
5
PLATING
b1
R
0.004
0.004
-
0.10
0.15
-
R1
0.010
0.25
c
c1
Rev. 3 7/07
NOTES:
BASE METAL
1. Dimensioning and tolerances per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO-203AA.
4X θ1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
GAUGE PLANE
SEATING
PLANE
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
L
C
α
L2
L1
4X θ1
VIEW C
0.4mm
0.75mm
2.1mm
0.65mm
TYPICAL RECOMMENDED LAND PATTERN
FN6800.6
January 12, 2012
17
ISL28114, ISL28214, ISL28414
Package Outline Drawing
P5.064A
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
0.08-0.20
D
A
5
4
PIN 1
INDEX AREA
2.80
3
1.60
5
3
0.15 C D
2x
(0.60)
2
0.20 C
2x
0.95
SEE DETAIL X
END VIEW
B
0.40 ±0.05
3
0.20 M C A-B D
TOP VIEW
10° TYP
(2 PLCS)
H
5
0.15 C A-B
2x
2.90
1.45 MAX
C
1.14 ±0.15
GAUGE
PLANE
(0.25)
SEATING PLANE
0.10
C
0.45±0.1
4
SIDE VIEW
0.05-0.15
(0.60)
DETAIL "X"
(1.20)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
(2.40)
2. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3. Dimension is exclusive of mold flash, protrusions or gate burrs.
4. Foot length is measured at reference to guage plane.
This dimension is measured at Datum “H”.
Package conforms to JEDEC MO-178AA.
5.
6.
(0.95)
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
FN6800.6
January 12, 2012
18
ISL28114, ISL28214, ISL28414
Package Outline Drawing
M8.118A
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
A
3.0±0.1
8
0.25 CAB
4.9±0.15
DETAIL "X"
0.18 ± 0.05
3.0±0.1
1.10 Max
PIN# 1 ID
B
SIDE VIEW 2
1
2
0.65 BSC
TOP VIEW
0.95 BSC
0.86±0.09
GAUGE
PLANE
H
C
0.25
SEATING PLANE
0.10 ± 0.05
0.33 +0.07/ -0.08
0.08 C AB
3°±3°
0.10 C
0.55 ± 0.15
DETAIL "X"
SIDE VIEW 1
5.80
NOTES:
1. Dimensions are in millimeters.
4.40
3.00
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSE Y14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
0.65
0.40
4. Plastic interlead protrusions of 0.25mm max per side are not
included.
1.40
5. Dimensions “D” and “E1” are measured at Datum Plane “H”.
6. This replaces existing drawing # MDP0043 MSOP 8L.
TYPICAL RECOMMENDED LAND PATTERN
FN6800.6
January 12, 2012
19
ISL28114, ISL28214, ISL28414
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
FN6800.6
January 12, 2012
20
ISL28114, ISL28214, ISL28414
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN6800.6
January 12, 2012
21
ISL28114, ISL28214, ISL28414
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
0.25 M C A B
D
A
(N/2)+1
MILLIMETERS
N
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
A
A1
A2
b
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
6.50
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
7.80
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
9.70
6.40
4.40
0.65
0.60
1.00
Max
±0.05
PIN #1 I.D.
E
E1
±0.05
+0.05/-0.06
+0.05/-0.06
±0.10
0.20 C B A
2X
1
(N/2)
c
N/2 LEAD TIPS
B
D
TOP VIEW
E
Basic
E1
e
±0.10
Basic
0.05
H
e
L
±0.15
C
L1
Reference
Rev. F 2/07
SEATING
PLANE
NOTES:
0.10 M C A B
b
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
0.10 C
N LEADS
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
FN6800.6
January 12, 2012
22
相关型号：
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