ISL28177FBZ-T7A [RENESAS]

40V General Purpose Precision Operational Amplifier; SOIC8; Temp Range: -40° to 125°C;


型号：	ISL28177FBZ-T7A
厂家：	RENESAS TECHNOLOGY CORP
描述：	40V General Purpose Precision Operational Amplifier; SOIC8; Temp Range: -40° to 125°C 放大器光电二极管
文件：	总16页 (文件大小：1469K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATASHEET

ISL28177

FN7859

Rev 2.00

April 5, 2012

40V General Purpose Precision Operational Amplifier

The ISL28177 is an OP07 replacement featuring low input

offset voltage, low input bias current, and competitive noise

and AC performance. The ESD ratings are best among

competitive parts at 5kV HBM, 300V MM, and 2.2kV CDM. The

amplifier operates over the 6V (±3V) to 40V (±20V) range.

Features

• Wide Supply Range . . . . . . . . . . . . . . . . 6V (±3V) to 40V (±20V)

• Low Input Offset Voltage. . . . . . . . . . . . . . . . . . . . 150µV, Max

• Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . . . .1nA, Max

• Low Noise . . . . . . . . . . . . . . . . . . . . . . . . . . .9.5nV/Hz @ 1kHz

• Gain Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600kHz

Applications include precision active filters, medical and

analytical instrumentation, precision power supply controls,

and industrial sensors.

• Exceptional ESD Performance . . . . . . . . . 5kV HBM, 300V MM,

2.2kV CDM

The ISL28177 is available in the SOT23-5 and SOIC-8

packages and operates over the extended temperature range

to -40°C to +125°C.

• Operating Temperature Range. . . . . . . . . . .-40°C to +125°C

• Packages

- ISL28177 (Single) . . . . . . . . . . . . . . . . . . . SOT23-5, SOIC-8

Applications

• Precision Active Filters

• Medical and Analytical Instrumentation

• Precision Power Supply Controls

• Industrial Sensors

10000

1000

= ±18V

8.2nF

1000

100

INPUT NOISE CURRENT

INPUT NOISE VOLTAGE

100

OUTPUT

1.84k

4.93k

3.3nF

0.1

100

10k

100k

SALLEN-KEY LOW PASS FILTER (10kHz)

FREQUENCY (Hz)

FIGURE 1. TYPICAL APPLICATION

FIGURE 2. INPUT NOISE PERFORMANCE

FN7859 Rev 2.00

April 5, 2012

Page 1 of 15

ISL28177

Ordering Information

PART NUMBER

TEMP RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

(Note 2, 3)

PART MARKING

28177 FBZ

ISL28177FBZ

-40 to +125

8 Ld SOIC

M8.15E

ISL28177FBZ-T13 (Note 1)

ISL28177FBZ-T7 (Note 1)

ISL28177FBZ-T7A (Note 1)

28177 FBZ

TBD

8 Ld SOIC

SOT23-5

M8.15E

P5.064A

Coming Soon

ISL28177FHZ

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28177. For more information on MSL please see techbrief TB363.

Pin Configurations

ISL28177

(8 LD SOIC)

TOP VIEW

ISL28177

(5 LD SOT-23)

TOP VIEW

V+

IN-

OUT

V-

IN-

IN+

V -

V+

OUT

IN+

Pin Descriptions

ISL28177

(8 LD SOIC)

(5 LD SOT-23)

PIN NAME

EQUIVALENT CIRCUIT

Circuit 1

Circuit 3

Circuit 1

Circuit 3

Circuit 2

DESCRIPTION

IN+

V-

Amplifier non-inverting input

Negative power supply

Amplifier inverting input

Positive power supply

Amplifier output

IN-

V+

OUT

1, 5, 8

No internal connection

V+

V-

V+

500Ω

CAPACITIVELY

COUPLED

IN-

IN+

OUT

ESD CLAMP

V-

CIRCUIT 1

CIRCUIT 2

CIRCUIT 3

FN7859 Rev 2.00

April 5, 2012

Page 2 of 15

ISL28177

Absolute Maximum Ratings

Thermal Information

Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V

Maximum Differential Input Voltage . . . . . . . 44V or V - 0.5V to V + 0.5V

Thermal Resistance (Typical)

5 Ld SOT-23 Package (Notes 4, 5). . . . . . . .

8 Ld SOIC Package (Notes 4, 5) . . . . . . . . . .



_JA(°C/W)

TBD



_JC(°C/W)

TBD

Min/Max Input Voltage . . . . . . . . . . . . . . . . . . 44V or V - 0.5V to V + 0.5V

125

Min/Max Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA

Output Short-Circuit Duration (1 output at a time) . . . . . . . . . . . . . . Indefinite

ESD Ratings

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Human Body Model (Tested per JESD22-A114F). . . . . . . . . . . . . . . . 5kV

Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . . 300V

Charged Device Model (Tested per CDM-22CI0ID). . . . . . . . . . . . . .2.2kV

Operating Conditions

Ambient Operating Temperature Range . . . . . . . . . . . . . .-40°C to +125°C

Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 6V (±3V) to 40V (±20V)

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4.  is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

5. For  , the “case temp” location is taken at the package top center.

Electrical Specifications V = ±5V to ±15V, R = Open, V = 0V, T = +25°C, unless otherwise specified. Boldface limits apply over the

operating temperature range, -40°C to +125°C.

MIN

(Note 6)

MAX

(Note 6)

PARAMETER

DESCRIPTION

Input Offset Voltage

CONDITIONS

TYP

UNIT

µV

150

250

350

1.4

-40°C to +85°C

-40°C to +125°C

µV

TCV

Input Offset Voltage Temperature

Coefficient

0.5

µV/°C

V /Time

Long Term V Stability

0.4

0.2

µV/mo

Input Bias Current

-40°C to +125°C

Input Offset Current

0.2

-40°C to +125°C

f = 0.1Hz to 10Hz

f = 10Hz

Input Noise Voltage

0.38

µV

P-P

Input Noise Voltage Density

Input Noise Current Density

Common Mode Input Voltage Range

nV/Hz

fA/Hz

f = 100Hz

9.6

9.5

f = 1kHz

Guaranteed by CMRR test

V +2

V -2

CMIR

CMRR

Common Mode Rejection Ratio

Power Supply Rejection Ratio

Output Voltage Low,

= V +2V to V - 2V

120

115

140

130

1.2

PSRR

V = ±3V to ±20V

R = 2kΩ

1.25

1.3

to V

OUT

R = 2kΩ, -40°C to +125°C

Output Voltage High,

to V

R = 2kΩ

1.2

1.25

1.3

OUT

R = 2kΩ, -40°C to +125°C

Slew Rate

R = 2kΩ, C = 100pF

0.2

600

140

V/µs

kHz

GBWP

AVOL

Gain Bandwidth Product

Large Signal Gain

R = 100kΩ, C = 60pF

= ±3V to ±13V, R = 10kΩ

120

OUT

FN7859 Rev 2.00

April 5, 2012

Page 3 of 15

ISL28177

Electrical Specifications V = ±5V to ±15V, R = Open, V = 0V, T = +25°C, unless otherwise specified. Boldface limits apply over the

operating temperature range, -40°C to +125°C. (Continued)

MIN

(Note 6)

MAX

(Note 6)

PARAMETER

DESCRIPTION

CONDITIONS

TYP

UNIT

Supply Current

1.18

1.4

1.7

Supply Voltage

±3V

±20V

Short Circuit Current

NOTE:

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

Typical Performance Curves

= ±15V, V = 0V, R = Open, unless otherwise specified.

100

1.4

1.2

1.0

0.8

0.6

0.4

0.2

= ±15V

-20

-40

-60

-80

-100

-40

-20

100

120

-40

-20

100

120

TEMPERATURE (°C)

FIGURE 3. INPUT OFFSET VOLTAGE (V ) vs TEMPERATURE

FIGURE 4. POWER SUPPLY CURRENT (I ) vs TEMPERATURE

500

= ±15V

V = ±15V

400

300

200

100

400

300

200

100

-100

-200

-300

-400

-500

-100

-200

-300

-400

-500

-40

-20

100

120

-40

-20

100

120

TEMPERATURE (°C)

FIGURE 5. POSITIVE INPUT BIAS CURRENT (I ) vs TEMPERATURE

IB+

FIGURE 6. NEGATIVE INPUT BIAS CURRENT (I ) vs TEMPERATURE

IB-

FN7859 Rev 2.00

April 5, 2012

Page 4 of 15

ISL28177

Typical Performance Curves

= ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)

14.5

-13.5

-13.6

-13.7

-13.8

-13.9

-14.0

-14.1

-14.2

-14.3

-14.4

-14.5

= ±15V

= 2k

= ±15V

R = 2k

14.4

14.3

14.2

14.1

14.0

13.9

13.8

13.7

13.6

13.5

-40

-20

100

120

-40

-20

100

120

TEMPERATURE (°C)

FIGURE 7. POSITIVE OUTPUT VOLTAGE (V ) vs TEMPERATURE

FIGURE 8. POSITIVE OUTPUT VOLTAGE (V ) vs TEMPERATURE

+25°C

+150°C

-1

0°C

= ∞

+125°C

-2

-3

-4

-5

-6

-7

-8

-9

-40°C

-55°C

= 100k

+75°C

= 10k

= 1k

= 499

= 100

= ±15V

= 2

= R = 100k

= 4pF

= +1

-5

-10

-15

= 50mV

OUT

= ±15V

P-P

= ±7.5V-DC

100

10k

100k

10M

CURRENT (mA)

FREQUENCY (Hz)

FIGURE 9. POSITIVE OUTPUT VOLTAGE (V

) vs OUTPUT CURRENT

OUT

FIGURE 10. UNITY GAIN FREQUENCY RESPONSE vs R

) vs TEMPERATURE

OUT

180

160

140

120

100

= 100kΩ, R = 100

= 1001

= 100kΩ, R = 1k

PHASE

= ±15V

= 101

= 10

= 4pF

= OPEN

= 50mV

OUT

P-P

GAIN

= 100kΩ, R = 11kΩ

= ±15V

= 1MΩ

SIMULATION

= 1

-20

= 0, R = ∞

-40

0.01 0.1

-10

10 100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

100

10k

100k

10M

FREQUENCY (Hz)

FIGURE 11. OPEN LOOP GAIN-PHASE vs FREQUENCY

FIGURE 12. FREQUENCY RESPONSE vs CLOSED LOOP GAIN

FN7859 Rev 2.00

April 5, 2012

Page 5 of 15

ISL28177

Typical Performance Curves

= ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)

= 1

= 22nF

= 10nF

R = 10k

OUT

= ±15V

= 50mV

+OVERSHOOT

P-P

= 4700pF

-2

-4

-6

-8

-10

-OVERSHOOT

= 10k

= +1

= 2200pF

= 50mV

OUT

P-P

= 1000pF

= ±15V

= 4pF

0.001

0.01

0.1

100

10k

100k

10M

FREQUENCY (Hz)

LOAD CAPACITANCE (nF)

FIGURE 13. UNITY GAIN FREQUENCY RESPONSE vs C

FIGURE 14. OVERSHOOT vs LOAD CAPACITANCE

10000

1000

100

10000

1000

100

500

400

300

200

100

= ±18V

= 10k

INPUT NOISE CURRENT

INPUT NOISE VOLTAGE

-100

-200

-300

-400

-500

0.1

100

10k

100k

FREQUENCY (Hz)

TIME (s)

FIGURE 15. INPUT NOISE VOLTAGE AND CURRENT SPECTRAL DENSITY

FIGURE 16. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz

= 1

= 2k AND 10k

= 4pF

= ±5V

-1

-2

-10

-20

-30

-40

= ±15V

= 1

= 2k AND 10k

= 4pF

-3

-4

-5

-6

100 200 300 400 500 600 700 800 900 1k

TIME (µs)

FIGURE 17. LARGE SIGNAL TRANSIENT RESPONSE

FIGURE 18. SMALL SIGNAL TRANSIENT RESPONSE

FN7859 Rev 2.00

April 5, 2012

Page 6 of 15

ISL28177

Typical Performance Curves

= ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)

280

240

200

160

120

-2

-4

-40

INPUT

OUTPUT

INPUT

= ±15V

= 100

= 10k

= 200mV

= ±15V

= 100

= 10k

= 200mV

-6

-80

-120

-160

-200

-240

-280

-8

P-P

-10

-12

-14

-16

OVERDRIVE = 1V

OUTPUT

-40

-80

-2

80 120 160 200 240 280 320 360 400

TIME (µs)

FIGURE 19. POSITIVE OUTPUT OVERLOAD RESPONSE TIME

FIGURE 20. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME

Applications Information

V+

Functional Description

The ISL28177 is a low noise op amp fabricated in a 40V

complementary bipolar DI process designed for general purpose

low power applications. It utilizes a super-beta NPN input stage

with input bias current cancellation for low input bias current and

low input noise voltage. A complimentary bipolar output stage

enables high capacitive load drive without external

compensation.

500Ω

OUT

V-

FIGURE 21. INPUT ESD DIODE CURRENT LIMITING

Operating Voltage Range

The series resistors limit the high feed-through currents that can

occur in pulse applications when the input dv/dt exceeds the

0.2V/µs slew rate of the amplifier. Without the series resistors, the

input can forward-bias the anti-parallel diodes causing current to

flow to the output, resulting in severe distortion and possible diode

failure. Figure 17 provides an example of distortion free large signal

The ISL28177 is designed to operate over the 6V (±3V) to 40V

(±20V) range. The common mode input voltage range extends to

2V from each rail, and the output voltage swings to 1.3V of

each rail.

Input Performance

response using a 10V input pulse with an input rise time of <1ns.

P-P

The super-beta NPN input pair reduces input bias current while

maintaining good frequency response, low input bias current and

low noise. Input bias cancellation circuits provide additional bias

current reduction to <1nA, and excellent temperature

The series resistors enable the input differential voltage to be equal

to the maximum power supply voltage (40V) without damage.

In applications where one or both amplifier input terminals are at

risk of exposure to high voltages beyond the power supply rails,

current limiting resistors may be needed at the input terminal to

limit the current through the power supply ESD diodes to

20mA max.

stabilization and low TCV

Input ESD Diode Protection

The input terminals (IN+ and IN-) have internal ESD protection

diodes to the positive and negative supply rails, series connected

500Ω current limiting resistors and an anti-parallel diode pair

across the inputs (Figure 21).

Output Current Limiting

The output current is internally limited to approximately ±30mA

at +25°C and can withstand a short circuit to either rail as long

as the power dissipation limits are not exceeded. Continuous

operation under these conditions may degrade long term

reliability.

Output Phase Reversal

Output phase reversal is a change of polarity in the amplifier

transfer function when the input voltage exceeds the supply

voltage. The ISL28177 is immune to output phase reversal.

FN7859 Rev 2.00

April 5, 2012

Page 7 of 15

ISL28177

Power Dissipation

ISL28177 SPICE Model

It is possible to exceed the +150°C maximum junction

temperature under certain load and power supply conditions. It is

therefore important to calculate the maximum junction

Figure 22 shows the SPICE model schematic and Figure 23 shows

the net list for the SPICE model. The model is a simplified version

of the actual device and simulates important AC and DC

temperature (T

) for all applications to determine if power

parameters. AC parameters incorporated into the model are: 1/f

and flatband noise voltage, Slew Rate, CMRR, Gain and Phase. The

JMAX

supply voltages, load conditions, or package type need to be

modified to remain in the safe operating area. These parameters

are related using Equation 1:

DC parameters are, VOS, I , total supply current and output

voltage swing. The model uses typical parameters given in the

“Electrical Specifications” table beginning on page 3. The AVOL is

adjusted for 140dB with the dominant pole at 0.075Hz. The CMRR

(EQ. 1)

= T

+  xPD

MAX JA MAXTOTAL

JMAX

is set 145dB, f = 500kHz. The input stage models the actual

device to present an accurate AC representation. The model is

configured for ambient temperature of +25°C.

where:

• PD

is the sum of the maximum power dissipation of

MAXTOTAL

each amplifier in the package (PD

)

MAX

Figures 24 through 37 show the characterization vs simulation

results for the Noise Voltage, Closed Loop Gain vs Frequency,

Small Signal 0.1V Step, Large Signal 5V Step Response, Open

• PD

MAX

for each amplifier can be calculated using Equation 2:

(EQ. 2)

OUTMAX

----------------------------

= V  I

+ V - V  

OUTMAX

MAX

qMAX

Loop Gain Phase, CMRR, Unity Gain Frequency Response vs C

and Output Voltage Swing for ±15V supplies.

where:

LICENSE STATEMENT

• T

= Maximum ambient temperature

MAX

The information in this SPICE model is protected under the

United States copyright laws. Intersil Corporation hereby grants

users of this macro-model hereto referred to as “Licensee”, a

nonexclusive, nontransferable license to use this model as long

as the Licensee abides by the terms of this agreement. Before

using this macro-model, the Licensee should read this license. If

the Licensee does not accept these terms, permission to use the

model is not granted.

•  = Thermal resistance of the package

• PD

= Maximum power dissipation of 1 amplifier

MAX

• V = Total supply voltage

• I

qMAX

= Maximum quiescent supply current of 1 amplifier

• V

OUTMAX

= Maximum output voltage swing of the application

The Licensee may not sell, loan, rent, or license the macro-model,

in whole, in part, or in modified form, to anyone outside the

Licensee’s company. The Licensee may modify the macro-model

to suit his/her specific applications, and the Licensee may make

copies of this macro-model for use within their company only.

This macro-model is provided “AS IS, WHERE IS, AND WITH NO

WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,

INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”

In no event will Intersil be liable for special, collateral, incidental,

or consequential damages in connection with or arising out of

the use of this macro-model. Intersil reserves the right to make

changes to the product and the macro-model without prior

notice.

FN7859 Rev 2.00

April 5, 2012

Page 8 of 15

V++

IEE1

96e-6

4.45e3

V++

Cascode

318.31927e-6

1e-9

2e-12

GAIN = 0.06

2122.196e6

GAIN = 4.712E-3

GAIN = 0.1e-6

1.7

Vin-

SuperB

1.7

R11

5e11

0.07

VCM

IOS

1e-9

EOS

Mirror

1.2e-12

5e11

R12

GAIN = 1E-9

Vmid

R19

5000

1.7

150E-6

VOS

R10

318.31927e-6

IEE

200e-6

Vin+

In+

2122.196e6

2e-12

GAIN = 0.06

GAIN = 4.712E-3

GAIN = 0.1e-6

1e-9

V--

COMMON MODE

GAIN STAGE

WITH ZERO

NOISE STAGE

INPUT STAGE

V+

1ST GAIN STAGE

2ND GAIN STAGE MID SUPPLY

REF VOLTAGE

GAIN = 1

D10

G11

10e-12

GAIN = 1.11e-2

R17

9E1

R13

R15

GAIN = 502.64e-6 1989.49546

1989.49546

GAIN = 502.64e-6

0.18

VOUT

ISY

1.18e-3

0.18

R14

1989.49546

G10

R16

G14

1989.49546

D12

G13

G12

R18

9E1

D11

GAIN = 502.64e-6

GAIN = 1.11e-2

GAIN = 502.64e-6

10e-12

GAIN = 1.11e-2

V--

V- _E2

CORRECTION CURRENT OUTPUT STAGE

SOURCES

2ND POLE STAGE

GAIN = 1

FIGURE 22. SPICE MODEL SCHEMATIC

ISL28177

*ISL28177 Macromodel

**Revision History:

*Input Stage

IN+ VIN- DC 1e-9

I_IOS

C_C1

C_C2

C_C3

R_R1

R_R2

R_R3

R_R4

Q_Q1

Q_Q2

Q_Q3

Q_Q4

Q_Q5

I_IEE

I_IEE1

D_D2

E_EOS

V_VOS

*Output Stage with Correction Current

Sources

*Revision A, LaFontaine December 14, 2011

*Model for Noise, quiescent supply currents,

*CMRR 145dB, fcm=500kHz, AVOL 140dB

*f=0.075Hz SR = 0.2V/us, GBWP 600kHz,

*2nd pole 8Mhz, output voltage clamp

*and short ckt current limit.

*Refer to data sheet "LICENSE

*STATEMENT", Use of this model indicates

*your acceptance with the terms and

*provisions in the License Statement.

IN+ VIN- 1.2e-12

0 VIN- 2e-12

0 IN+ 2e-12

VCM VIN- 5e11

IN+ VCM 5e11

6 V++ 4.45e3

7 V++ 4.45e3

4 VIN- 3 SuperB

5 10 3 SuperB

V-- 3 9 Mirror

6 8 4 Cascode

7 8 5 Cascode

3 V-- DC 200e-6

V++ 8 DC 96e-6

8 9 DX

G_G11

G_G12

G_G13

G_G14

D_D7

D_D8

D_D9

D_D10

D_D11

D_D12

V_V6

VOUT V++ V++ 21 1.11e-2

V-- VOUT 21 V-- 1.11e-2

22 V-- VOUT 21 1.11e-2

25 V-- 21 VOUT 1.11e-2

21 23 DX

24 21 DX

V++ 22 DX

V++ 25 DX

V-- 22 DY

V-- 25 DY

23 VOUT 0.18

V_V7

VOUT 24 0.18

R_R17

R_R18

VOUT V++ 9E1

V-- VOUT 9E1

*Intended use:

*This Pspice Macromodel is intended to give

*typical DC and AC performance

*characteristics under a wide range of

*external circuit configurations using

*compatible simulation platforms - such as

*iSim PE.

10 11 VC VMID 1E-9

11 IN+ 30E-6

.model SuperB npn

+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50

+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12

+ kf=0 af=0

*1st Gain Stage

G_G1

G_G2

R_R5

R_R6

V_V2

V_V3

D_D3

D_D4

V++ 13 6 7 0.06

.model Cascode npn

V-- 13 6 7 0.06

13 V++ 1

V-- 13 1

12 13 1.7

13 14 1.7

+ is=502E-18 bf=150 va=300 ik=17E-3

+rb=140 re=0.011 rc=900 cje=0.2E-12

+cjc=0.16E-12f kf=0 af=0

*Device performance features supported by

*this model

*Typical, room temp., nominal power supply

*voltages used to produce the following

*characteristics:

*Open and closed loop I/O impedances

*Open loop gain and phase

*Closed loop bandwidth and frequency

*response

*Loading effects on closed loop frequency

*response

*Input noise terms including 1/f effects

*Slew rate

*Input and Output Headroom limits to I/O

*voltage swing

*Supply current at nominal specified supply

*voltages

.model Mirror pnp

+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185

+ re=0.101 rc=180 cje=1.34E-12

+ cjc=0.44E-12

12 V++ DX

V-- 14 DX

*2nd Gain Stage

+ kf=0 af=0

G_G3

G_G4

R_R7

R_R8

V_V4

V_V5

D_D5

D_D6

C_C4

C_C5

V++ 15 13 VMID 4.712E-3

.model DN D(KF=6.69e-9 AF=1)

.MODEL DX D(IS=1E-12 Rs=0.1)

.MODEL DY D(IS=1E-15 BV=50 Rs=1)

.ends subckt ISL28177

V-- 15 13 VMID 4.712E-3

15 V++ 2122.196e6

V-- 15 2122.196e6

16 15 1.7

15 17 1.7

16 V++ DX

V-- 17 DX

15 V++ 1e-9

V-- 15 1e-9

*Device performance features NOT

*supported by this model:

*Mid supply Ref

*Harmonic distortion effects

*Disable operation (if any)

*Thermal effects and/or over temperature

*parameter variation

*Limited performance variation vs. supply

*voltage is modeled

R_R9

R_R10

E_E1

E_E2

I_ISY

VMID V++ 1

V-- VMID 1

V++ 0 V+ 0 1

V-- 0 V- 0 1

V+ V- DC 1.18e-3

*Part to part performance variation due to

*normal process parameter spread

*Any performance difference arising from

*different packaging

* source

*Common Mode Gain Stage with Zero

G_G5

G_G6

R_R11

R_R12

L_L1

L_L2

V++ VC VCM VMID 0.1e-6

V-- VC VCM VMID 0.1e-6

VC 18 1

19 VC 1

18 V++ 318.31927e-6

19 V-- 318.31927e-6

+input

-input

| +Vsupply

*2nd Pole Stage

-Vsupply

G_G7

G_G8

G_G9

G_G10

R_R13

R_R14

R_R15

R_R16

C_C6

V++ 20 15 VMID 502.64e-6

output

V-- 20 15 VMID 502.64e-6

V++ 21 20 VMID 502.64e-6

V-- 21 20 VMID 502.64e-6

20 V++ 1989.49546

V-- 20 1989.49546

21 V++ 1989.49546

V-- 21 1989.49546

20 V++ 10e-12

.subckt ISL28177 Vin+ Vin- V+ V- VOUT

* source ISL28177_SPICEMODEL

*Voltage Noise

E_En

D_D1

V_V1

R_R19

IN+ VIN+ 2 0 1

1 2 DN

1 0 0.07

C_C7

V-- 20 10e-12

2 0 5000

C_C8

21 V++ 10e-12

C_C9

V-- 21 10e-12

FIGURE 23. SPICE NET LIST

FN7859 Rev 2.00

April 5, 2012

Page 10 of 15

ISL28177

Characterization vs Simulation Results

10000

1000

100

10000

1000

100

10000

1000

100

= ±18V

= ±15V

INPUT NOISE CURRENT

INPUT NOISE VOLTAGE

0.1

100k

0.1

100

10k

100

10k

100k

FREQUENCY (Hz)

FIGURE 24. CHARACTERIZED INPUT NOISE VOLTAGE

FIGURE 25. SIMULATED INPUT NOISE VOLTAGE

= 100kΩ, R = 100

R = 100kΩ, R = 100

F G

= 1001

= 100kΩ, R = 1k

R = 100kΩ, R = 1k

F G

= ±15V

= 4pF

= OPEN

= ±15V

= 101

= 10

= 101

= 10

= 4pF

= OPEN

= 50mV

OUT

P-P

OUT

P-P

= 100kΩ, R = 11kΩ

= 1

= 0, R = ∞

R = 0, R = ∞

F G

-10

100

10k

100k

10M

100

10k

100k

10M

FREQUENCY (Hz)

FIGURE 26. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY

FIGURE 27. SIMULATED CLOSED LOOP GAIN vs FREQUENCY

= 1

= 10k

= 4pF

= 2k AND 10k

= 4pF

= ±5V

-10

-20

-30

-40

-10

-20

-30

-40

= ±15V

TIME (µs)

FIGURE 28. CHARACTERIZED SMALL SIGNAL TRANSIENT

RESPONSE vs R , V = ±0.9V, ±2.5V

FIGURE 29. SIMULATED SMALL SIGNAL TRANSIENT

RESPONSE V = ±15V

FN7859 Rev 2.00

April 5, 2012

Page 11 of 15

ISL28177

Characterization vs Simulation Results(Continued)

-1

-2

-3

-4

-5

-6

-1

-2

-3

-4

-5

-6

= ±15V

= 1

= 2k AND 10k

= 4pF

= ±15V

= 1

= 2k AND 10k

= 4pF

100 200 300 400 500 600 700 800 900 1k

TIME (µs)

100 200 300 400 500 600 700 800 900 1k

TIME (µs)

FIGURE 30. CHARACTERIZED LARGE SIGNAL TRANSIENT

RESPONSE vs R , V = ±15V

FIGURE 31. SIMULATED LARGE SIGNAL TRANSIENT

RESPONSE, V = ±14V

180

160

140

120

100

180

160

140

120

100

PHASE

GAIN

= ±15V

GAIN

= ±15V

= 1MΩ

SIMULATION

= 1MΩ

-20

-40

-20

-40

0.01 0.1

SIMULATION

0.01 0.1

10 100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

10 100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

FIGURE 32. SIMULATED (DESIGN) OPEN-LOOP GAIN, PHASE vs

FREQUENCY

FIGURE 33. SIMULATED (SPICE) OPEN-LOOP GAIN, PHASE vs

FREQUENCY

= 22nF

= 10nF

= 22nF

C = 10nF

= 4700pF

-2

-4

-6

-8

-10

= 2200pF

= 1000pF

-2

-4

-6

= 10k

= +1

= 2200pF

= 50mV

OUT

= ±15V

P-P

= 1000pF

-8

= 4pF

C = 4pF

-10

100

10k

100k

10M

100

10k

100k

10M

FREQUENCY (Hz)

FIGURE 34. CHARACTERIZEDUNITY GAIN

FREQUENCY RESPONSE vs C

FIGURE 35. SIMULATED UNITY GAIN FREQUENCY RESPONSE vs C

FN7859 Rev 2.00

April 5, 2012

Page 12 of 15

ISL28177

Characterization vs Simulation Results(Continued)

200

13.79V

160

120

-5

-13.8V

0.8

-10

-15

0.01 0.1 1.0 10 100 1k 10k 100k 1M 10M 100M 1G

0.2

0.4

0.6

1.0

FREQUENCY (Hz)

TIME (ms)

FIGURE 36. SIMULATED (SPICE) CMRR

FIGURE 37. SIMULATED OUTPUT VOLTAGE SWING ±15V

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest Rev.

DATE

REVISION

FN7859.2

CHANGE

March 29, 2012

Changed Note 1 in “Ordering Information” on page 2 from:

“Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.”

to:

“Please refer to TB347 for details on reel specifications.”

Listed out tape and reel parts individually in “Ordering Information” on page 2 (ISL28177FBZ-T13,

ISL28177FBZ-T7, ISL28177FBZ-T7A)

January 5, 2012

October 31, 2011

FN7859.1

FN7859.0

Added SPICE model to data sheet.

Added ESD Ratings to description on page 1.

Initial Release

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on

intersil.com: ISL28177

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

FITs are available from our website at: http://rel.intersil.com/reports/sear

FN7859 Rev 2.00

April 5, 2012

Page 13 of 15

ISL28177

Package Outline Drawing (M8.15E)

M8.15E

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 0, 08/09

4.90 ± 0.10

DETAIL "A"

0.22 ± 0.03

6.0 ± 0.20

3.90 ± 0.10

PIN NO.1

ID MARK

(0.35) x 45°

4° ± 4°

0.43 ± 0.076

1.27

0.25 M C A B

SIDE VIEW “B”

TOP VIEW

1.75 MAX

1.45 ± 0.1

0.25

GAUGE PLANE

SEATING PLANE

0.175 ± 0.075

SIDE VIEW “A

0.10 C

0.63 ±0.23

DETAIL "A"

(0.60)

(1.27)

NOTES:

(1.50)

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

(5.40)

4. Dimension does not include interlead flash or protrusions.

Interlead flash or protrusions shall not exceed 0.25mm per side.

The pin #1 identifier may be either a mold or mark feature.

Reference to JEDEC MS-012.

TYPICAL RECOMMENDED LAND PATTERN

FN7859 Rev 2.00

April 5, 2012

Page 14 of 15

ISL28177

Package Outline Drawing

P5.064A

5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE

Rev 0, 2/10

1.90

0-3°

0.08-0.20

PIN 1

INDEX AREA

2.80

1.60

0.15 C D

(0.60)

0.20 C

0.95

SEE DETAIL X

END VIEW

0.40 ±0.05

0.20 M C A-B D

TOP VIEW

10° TYP

(2 PLCS)

0.15 C A-B

2.90

1.45 MAX

1.14 ±0.15

GAUGE

PLANE

(0.25)

SEATING PLANE

0.10

0.45±0.1

SIDE VIEW

0.05-0.15

(0.60)

DETAIL "X"

(1.20)

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

(2.40)

2. Dimensioning and tolerancing conform to ASME Y14.5M-1994.

3. Dimension is exclusive of mold flash, protrusions or gate burrs.

4. Foot length is measured at reference to gauge plane.

This dimension is measured at Datum “H”.

Package conforms to JEDEC MO-178AA.

(0.95)

(1.90)

TYPICAL RECOMMENDED LAND PATTERN

FN7859 Rev 2.00

April 5, 2012

Page 15 of 15

IMPORTANT NOTICE AND DISCLAIMER

RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL

SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING

REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND

OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,

INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A

PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible

for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)

ensuring your application meets applicable standards, and any other safety, security, or other requirements. These

resources are subject to change without notice. Renesas grants you permission to use these resources only for

development of an application that uses Renesas products. Other reproduction or use of these resources is strictly

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expands or otherwise alters any applicable warranties or warranty disclaimers for these products.

(Rev.1.0 Mar 2020)

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Contact Information

TOYOSU FORESIA, 3-2-24 Toyosu,

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Electronics Corporation. All trademarks and registered

trademarks are the property of their respective owners.

ISL28177FBZ-T7A [RENESAS]

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