ISL29125 [RENESAS]
Digital Red, Green and Blue Color Light Sensor with IR Blocking Filter;
| 型号： | ISL29125 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Digital Red, Green and Blue Color Light Sensor with IR Blocking Filter |
| 文件： | 总17页 (文件大小：786K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL29125
FN8424
Rev.3.00
Jan 13, 2017
Digital Red, Green and Blue Color Light Sensor with IR Blocking Filter
The ISL29125 is a low power, high sensitivity, RED, GREEN and
Features
BLUE color light sensor (RGB) with an I2C (SMBus compatible)
• 56µA operating current, 0.5µA shutdown current
interface. Its state-of-the-art photodiode array provides an
accurate RGB spectral response and excellent light source to
light source variation (LS2LS). The ISL29125 is designed to
reject IR in light sources allowing the device to operate in
environments from sunlight to dark rooms. The integrating
ADC rejects 50Hz and 60Hz flicker caused by artificial light
sources. A selectable range allows the user to optimize
sensitivity suitable for the specific application. In normal
operation mode the device consumes 56µA, which reduces to
0.5µA in power-down mode. The ISL29125 supports hardware
and software user programmable interrupt thresholds. The
Interrupt persistency feature reduces false trigger notification.
The device operates on supplies (VDD) from 2.25V to 3.63V, I2C
supply from 1.7V to 3.63V, and operating temperature across the
-40°C to +85°C range.
• Selectable range (Via I2C)
• I2C (SMBus compatible) output
• ADC resolution 16 bits
• Programmable interrupt windows
• Two optical sensitivity ranges
- Range 0 = 5.7m lux to 375 lux
- Range 1 = 0.152 lux to 10,000 lux
• Operating power supply 2.25 to 3.63V
• I2C power supply 1.7V to 3.63V
• 6 Ld ODFN (1.65x1.65x0.7mm) package
Applications
Related Literature
AN1914, “Evaluation Hardware/Software User Manual for RGB
Sensor”
• Smart phone, PDA, GPS, tablet PCs, LCD-TVs, digital picture
frames, digital cameras
• Dynamic display color balancing
AN1910, “Enhancing RGB Sensitivity and Conversion Time”
• Printer color enhancement
• Industrial/commercial LED lighting color management
• Ambient light color detection/correction
• OLED display aging compensation
R1
C1
C2
Vbus
VDD
2.0
R2 R3 R4
1.8
NORMALIZED TO GREEN
1.6
1
1.4
VDD
RED
GREEN
1.2
1.0
0.8
0.6
SDA
SCL
SDA
SCL
INT
4
6
BLUE
1931 STD RED
1931 STD GREEN
1931 STD BLUE
2
ISL29125
NC
MCU
0.4
0.2
0.0
GPIO
5
GND
3
R1 - 100Ω
R
2 - 2.7kΩ to 10kΩ
350 380 410 440 470 500 530 560 590 620 650 680 710 740 770 800 830
R3 - 2.7kΩ to 10kΩ
WAVELENGTH
R
C
C
4 - 2.7kΩ to 10kΩ
1 - 1µF
2 - 0.1µF
FIGURE 1. TYPICAL APPLICATION DIAGRAM
FIGURE 2. NORMALIZED SPECTRAL RESPONSE FOR RED, GREEN
AND BLUE SENSING
FN8424 Rev.3.00
Jan 13, 2017
Page 1 of 17
ISL29125
Block Diagram
VDD
1
IREF
COMMAND
REGISTER
fOSC
R
6
4
SCL
SDA
I2C/SMB
RED
GREEN
INTEGRATING
ADC
DATA
REGISTER
LIGHT DATA
PROCESS
BLUE
INTERRUPT
3
5
GND
INT
Pin Configuration
Pin Descriptions
ISL29125
PIN
PIN
(6 LD ODFN)
TOP VIEW
NUMBER
NAME
DESCRIPTION
1
2
3
4
5
VDD
NC
Positive supply
No Connect
Ground
VDD
NC
6
5
4
SCL
INT
1
GND
SDA
INT
I2C serial data
GND
Interrupt; LOW for interrupt alarming. INT pin
is an open drain. INT remains asserted until
the interrupt status bit is reset.
INT also becomes an input when it is set in
SYNC mode.
6
SCL
I2C serial clock
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
TEMP RANGE
TAPE AND REEL
QUANTITY
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
(°C)
ISL29125IROZ-T7
-40 to +85
-40 to +85
3,000
250
6 Ld ODFN
6 Ld ODFN
L6.1.65x1.65
L6.1.65x1.65
ISL29125IROZ-T7A
ISL29125EVAL1Z
NOTES:
Evaluation Board.
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL29125. For more information on MSL please see tech brief TB477.
FN8424 Rev.3.00
Jan 13, 2017
Page 2 of 17
ISL29125
Absolute Maximum Ratings
Thermal Information
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0V
I2C Bus (SCL, SDA) and INT Pin Voltage. . . . . . . . . . . . . . . . . . -0.2V to 4.0V
I2C Bus (SCL, SDA) and INT Pin Current. . . . . . . . . . . . . . . . . . . . . . . <10mA
Input Voltage Slew Rate (Max). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1V/µs
ESD Ratings
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5kV
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Thermal Resistance (Typical)
JA (°C/W)
6 Ld ODFN Package (Note 4) . . . . . . . . . . . . . . . . . . . . .
260
Maximum Junction Temperature (TJMAX). . . . . . . . . . . . . . . . . . . . . . .+90°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications VDD = 3.0V, TA = +25°C, 16-bit ADC operation, unless otherwise specified.
MIN
MAX
SYMBOL
VDD
PARAMETER
Power Supply Range
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNIT
V
2.25
3.63
85
IDD
Supply Current
56
29
µA
IDD1
IDD2
VI2C
tINT
Supply Current when Standby
Supply Current when Powered Down
Supply Voltage Range for I2C Interface
ADC Integration/Conversion Time
I2C Clock Rate Range
Software disabled
37
µA
Software disabled
0.50
1.45
3.63
µA
1.70
V
16-bit ADC data
101
500
1
ms
kHz
Counts
%
fI2C
DDark Count Output when Dark
Lux = 0 lux, Range = 0 (375 lux)
5
CCT
Corrected Color Temperature Accuracy
Illuminant A is at 300 lux (see Note 11 on
page 11 and “References” on page 15 about
CIE 1931, Planckian locus and standard
illuminants)
±5
DFS
Full Scale ADC Code
Full Scale on Range 0
ADC 16 bits
65535
Counts
µW/cm2
µW/cm2
µW/cm2
Green = 565nm
Red = 620nm
Blue = 485nm
18
20
30
NOTES:
5. 565nm Green, 620nm Red LED, 485nm Blue in white LED is used in production test. Its irradiance is calibrated to produce the same DATA count
against an illuminance level of 130 lux fluorescent light.
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. SDA and INT current sinking capability are assured by design.
FN8424 Rev.3.00
Jan 13, 2017
Page 3 of 17
ISL29125
2
I C Interface Specifications VDD = 3.0V, TA = +25°C, 16-bit ADC operation, unless otherwise specified.
MIN
MAX
SYMBOL
VIL
PARAMETER
CONDITIONS
(Note 6)
1.25
0
TYP
(Note 6) UNIT
SDA and SCL Input Buffer LOW Voltage
SDA and SCL Input Buffer HIGH Voltage
0.55
V
V
V
V
VIH
V
Hys (Note 8) SDA and SCL Input Buffer Hysteresis
0.05xVDD
V
OL (Note 8) SDA Output Buffer LOW Voltage
0.4
10
(Open-Drain), Sinking 4mA
C
PIN (Note 8) SDA and SCL Pin Capacitance
TA = +25°C, f = 1MHz, VDD = 5V, VIN = 0V,
pF
VOUT = 0V
fSCL
tIN
SCL Frequency
500
50
kHz
ns
Pulse Width Suppression Time at SDA and SCL Any pulse narrower than the maximum
Inputs
specification is suppressed
tAA
SCL Falling Edge to SDA Output Data Valid
900
ns
ns
tBUF
Time the Bus Must be Free Before the Start of
a New Transmission
1300
tLOW
tHIGH
SCL LOW Time
1300
600
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
kΩ
SCL HIGH Time
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
START Condition Set-Up Time
START Condition Hold Time
Input Data Set-Up Time
Input Data Hold Time
STOP Condition Set-Up Time
600
600
100
30
600
tHD:STHD:ST STOP Condition Hold Time
tHD:ST Output Data Hold Time
600
0
t
t
HD:ST (Note 8) SDA and SCL Rise Time
HD:ST (Note 8) SDA and SCL Fall Time
Cb (Note 8) Capacitive Loading of SDA or SCL
20+0.1xCb
20+0.1xCb
Total on-chip and off-chip
400
R
PU (Note 8) SDA and SCL Bus Pull-Up Resistor Off-Chip
Maximum is determined by tR and tF
1
For Cb = 400pF, maximum is about 2kΩ~ 2.5kΩ
For Cb = 40pF, maximum is about 15kΩ~ 20kΩ
NOTES:
8. Limits should be considered typical and are not production tested.
9. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
10. Cb is the capacitance of the bus in pF.
FN8424 Rev.3.00
Jan 13, 2017
Page 4 of 17
ISL29125
SDA vs SCL Timing
tF
tHIGH
tLOW
tR
tHD:STO
SCL
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STA
SDA
(INPUT TIMING)
tDH
tBUF
tAA
SDA
(OUTPUT TIMING)
FIGURE 3. I2C BUS TIMING
SCL
SDA
8TH BIT OF LAST BYTE
ACK
tWC
STOP
START
CONDITION
CONDITION
FIGURE 4. I2C WRITE CYCLE TIMING
Typical Performance Curves
1.2
1.0
0.8
2.0
1.8
NORMALIZED TO GREEN
1.6
RED
1.4
1.2
1.0
0.8
0.6
RED
GREEN
BLUE
GREEN
0.6
0.4
0.2
0
1931 STD RED
1931 STD GREEN
1931 STD BLUE
BLUE
0.4
0.2
0.0
-90 -80 -70 -60 -50 -40 -30 -20 -10
0 10 20 30 40 50 60 70 80 90
350 380 410 440 470 500 530 560 590 620 650 680 710 740 770 800 830
ANGLE (°)
WAVELENGTH
FIGURE 5. NORMALIZED SPECTRAL RESPONSE FOR AMBIENT
LIGHT SENSING
FIGURE 6. RADIATION PATTERN
FN8424 Rev.3.00
Jan 13, 2017
Page 5 of 17
ISL29125
the actual count stored in Registers 0x9 and 0xA for Green or
Registers 0xB and 0xC for Red or Register 0xD and 0xE for Blue
are outside the user’s programmed window. Once ISL29125
issues the interrupt flag, the interrupt status (RGBTHF) bit at
Reg0x08 is asserted to logic HIGH and the INT pin goes low. Both
the INT pin and the interrupt status bit are automatically cleared at
the end of the 8-bit Device Register byte (0x08) transfer. By default
(RGBTHF) bit is LOW or it is within the interrupt thresholds window.
Principles of Operation
Photodiodes and ADC
The ISL29125 contains three photodiode arrays, which convert
light into current. The spectral response for RED, GREEN and
BLUE color ambient intensity sensing is shown in Figure 2. After
light is converted to current during the light to signal process, the
current output is converted to a digital count by an on-chip
Analog-to-Digital Converter (ADC). The ADC converter resolution
is selectable from 12 or 16 bits. The ADC conversion time is
inversely proportional to the ADC resolution.
Power-On Reset
The Power-On Reset (POR) circuitry protects the internal logic
against powering up in the incorrect state. The ISL29125 will
power up into Standby mode after VDD exceeds the POR trigger
level and will power down into Reset mode when VDD drops
below the POR trigger level. This bidirectional POR feature
protects the device against ‘brown-out’ failure following a
temporary loss of power.
The ADC converter uses an integrating architecture. This
conversion method is ideal for converting small signals in the
presence of a periodic noise. A 100ms integration time (16-bit
mode) for instance, rejects 50Hz and 60Hz power line as well as
florescent flicker noise.
The ADC integration time is determined by an internal oscillator
and the n-bit (n = 12, 16) counter inside the ADC. A good
balancing act of integration time and resolution depends on the
application for optimum system performance.
The POR is an important feature because it prevents the
ISL29125 from starting to operate with insufficient power supply
voltage. The ISL29125 prevents communication to its registers
and reduces the likelihood of data corruption on power-up.
The ADC provides two programmable ranges to dynamically
accommodate different lighting conditions. For dim conditions,
the ADC can be configured at its high sensitivity (low optical)
range. For bright conditions, the ADC can be configured at its low
sensitivity (higher optical) range. Note that the effective optical
sensitivity of the ISL29125 in terms of counts/µW/cm2 is
directly proportional to the ADC integration time.
Serial Interface
The ISL29125 supports the Inter-Integrated Circuit (I2C) bus data
transmission protocol. The I2C bus is a two-wire serial
bidirectional interface consisting of SCL (clock) and SDA (data).
Both the wires are connected to the device supply via pull-up
resistors. The I2C protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and the
device being controlled is the slave. The transmitting device pulls
down the SDA line to transmit a “0” and releases it to transmit a
“1”. The master always initiates the data transfer, only when the
bus is not busy and provides the clock for both transmit and
receive operations. The ISL29125 operates as a slave device in
all applications. The serial communication over the I2C interface
is conducted by sending the Most Significant Bit (MSB) of each
byte of data first.
SYNC Mode
SYNC mode is when B5 at Reg0x1 is set to ‘1’, the INT pin
becomes an input pin. This mode is beneficial for some systems
which have multiple sensors on I2C bus. Once B5 is set, on the
rising edge of INT the ADC starts conversion so that multiple
devices would measure at exactly the same time. Yet, to read
data out, the system needs to have a different I2C address for
each sensor or have a multiplexer. Moreover, if B5 is set to ‘0’,
then INT pin will be asserted whenever the sensor triggers an
interrupt.
Start Condition
Interrupt Function
During data transfer, the SDA line must remain stable while the
SCL line is HIGH. All I2C interface operations must begin with a
START condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (refer to Figure 9). The ISL29125 continuously
monitors the SDA and SCL lines for the START condition and does
not respond to any command until this condition is met (refer to
Figure 9). A START condition is ignored during the power-up
sequence.
The active low interrupt pin is an open-drain pull-down
configuration. The interrupt pin serves as an alarm or monitoring
function to determine whether the ambient light level exceeds
the upper threshold or goes below the lower threshold. It should
be noted that the function of ADC conversion continues without
stopping after interrupt is asserted. If the user needs to read the
ADC count that triggers the interrupt, the reading should be done
before the data registers are refreshed by the following
conversions. The user can also configure the persistency of the
interrupt pin. This reduces the possibility of false triggers, such as
noise or sudden spikes in ambient light conditions. An
unexpected camera flash, for example, can be ignored by setting
the persistency to 8 integration cycles. ISL29125 interrupt
modes can be selected at Bit[1:0] at Reg0x03 Table 11. The user
can select Red, Green or Blue to be the interrupt target. An
interrupt event (RGBTHF) bit at Reg0x08 is governed by Registers
4 through 7. The user writes a high and low threshold value to
these registers and the ISL29125 will issue an interrupt flag if
Stop Condition
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (refer to Figure 9). A STOP condition at the end of a
read/write operation places the device in its standby mode. If a
stop is issued in the middle of a Data byte, or before 1 full Data
byte and ACK is sent, then the serial communication of ISL29125
resets itself without performing the read/write. The contents of
the register array are not affected.
FN8424 Rev.3.00
Jan 13, 2017
Page 6 of 17
ISL29125
Acknowledge
Write Operation
An acknowledge (ACK) is a software convention used to indicate
a successful data transfer. The transmitting device releases the
SDA bus after transmitting 8 bits. During the ninth clock cycle,
the receiver pulls the SDA line LOW to acknowledge the reception
of the eight bits of data (refer to Figure 9). The ISL29125
responds with an ACK after recognition of a START condition
followed by a valid Identification Byte and once again, after
successful receipt of an Address Byte. The ISL29125 also
responds with an ACK after receiving a Data byte of a write
operation. The master must respond with an ACK after receiving
a Data byte of a read operation
BYTE WRITE
In a byte write operation, ISL29125 requires the Device Address
byte, Register Address byte and the Data byte. The master starts
the communication with a START condition. Upon receipt of the
Device Address byte, Register Address byte and the Data byte,
the ISL29125 responds with an acknowledge (ACK). Following
the ISL29125 data acknowledge response, the master
terminates the transfer by generating a STOP condition. The
ISL29125 then begins an internal write cycle of the data to the
volatile memory. During the internal write cycle, the device inputs
are disabled and the SDA line is in a high impedance state, so the
device will not respond to any requests from the master (refer to
Figure 8).
Device Addressing
Following a START condition, the master must output a Device
Address byte. The 7 MSBs of the Device Address byte are known
as the device identifier. The device identifier bits of ISL29125 are
internally hard-wired as “1000100”. The LSB of the Device
Address byte is defined as read or write (R/W) bit. When this
R/W bit is a “1”, a read operation is selected and when “0”, a
write operation is selected (refer to Figure 7). The master
generates a START condition followed by Device Address byte
1000100x (x as R/W) and the ISL29125 compares it with the
internal device identifier. Upon a correct comparison, the device
outputs an acknowledge (LOW) on the SDA line (refer to Figure 9).
BURST WRITE
The ISL29125 has a burst write operation, which allows the
master to write multiple consecutive bytes from a specific
address location. It is initiated in the same manner as the byte
write operation, but instead of terminating the write cycle after
the first Data byte is transferred, the master can write to the
whole register array. After the receipt of each byte, the ISL29125
responds with an acknowledge and the address is internally
incremented by one. The address pointer remains at the last
address byte written. When the counter reaches the end of the
register address list, it “rolls over” and goes back to the first
Register Address.
DEVICE
R/W
1
0
0
0
1
0
0
ADDRESS BYTE
REGISTER
ADDRESS BYTE
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE
FIGURE 7. DEVICE ADDRESS, REGISTER ADDRESS AND DATA BYTE
S
T
A
R
T
S
T
O
P
D EVICE
A D D RESS B YTE
SIG N A L FR O M
M A STER D EVIC E
A D D RESS B YTE
D A TA BYTE
1
0
0 0 1 0 0 0
SIG N A L A T SD A
A
C
K
A
C
K
A
C
K
SIG NA LS FR O M
SLAVE D EVIC E
FIGURE 8. BYTE WRITE SEQUENCE
8th
CLK
9th
CLK
SCL FROM
MASTER
HIGH
IMPEDANCE
SDA FROM
TRANSMITTER
SDA FROM
RECEIVER
DATA
DATA
DATA
START
STABLE
CHANGE
STABLE
ACK
STOP
FIGURE 9. START, DATA STABLE, ACKNOWLEDGE AND STOP CONDITION
FN8424 Rev.3.00
Jan 13, 2017
Page 7 of 17
ISL29125
The master terminates the read operation by not responding with
an acknowledge and then issuing a stop condition. Refer to
Figure 10.
Read Operation
ISL29125 has two basic read operations: Byte Read and Burst
Read.
BURST READ
BYTE READ
Burst read operation is identical to the Byte Read operation.
After the first Data byte is transmitted, the master now responds
with an acknowledge, indicating it requires additional data. The
device continues to output data for each acknowledge received.
The master terminates the read operation by not responding with
an acknowledge but issuing a STOP condition (refer to Figure 11).
Byte read operations allow the master to access any register
location in the ISL29125. The Byte read operation is a two step
process. The master issues the START condition and the Device
Address byte with the R/W bit set to “0”, receives an
acknowledge, then issues the Register Address byte. After
acknowledging receipt of the register address byte, the master
immediately issues another START condition and the Device
Address byte with the R/W bit set to “1”. This is followed by an
acknowledge from the device and then by the 8-bit data word.
For more information about the I2C standard, please consult the
Phillips™ I2C specification documents.
S
T
A
R
T
S
T
A
R
T
S
T
O
P
DEVICE ADDRESS
WRITE
DEVICE ADDRESS
READ
SIGNAL FROM
MASTER DEVICE
ADDRESS BYTE
DATA BYTE
1
0
0
0
1
0
0
0
1 0 0 0 1 0 0 1
SIGNAL AT SDA
A
C
K
A
C
K
A
C
K
SIGNALS FROM
SLAVE DEVICE
FIGURE 10. BYTE ADDRESS READ SEQUENCE
S
T
A
R
T
S
T
S
T
O
P
DEVICE
ADDRESS WRITE
DEVICE
A
SIGNAL FROM
MASTER DEVICE
ADDRESS BYTE
DATA BYTE 1
DATA BYTE 2
DATA BYTE n
ADDRESS READ
R
T
1 0 0 0 1 0 0 0
1 0 0 0 1 0 0 1
SIGNAL AT SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SIGNALS FROM
SLAVE DEVICE
("n" is any integer
greater than 1)
FIGURE 11. BURST READ SEQUENCE
FN8424 Rev.3.00
Jan 13, 2017
Page 8 of 17
ISL29125
TABLE 1. REGISTER MAP
REGISTER
ADDRESS
REGISTER BITS
B4 B3
NAME
DEC HEX
B7
B6
B5
B2
B1
B0
DEFAULT ACCESS
Device ID
0
0x00
ID[7]
ID[7]
ID[6]
ID[6]
ID[5]
ID[5]
SYNC
ID[4]
ID[4]
BITS
ID[3]
ID[3]
RNG
ID[2]
ID[2]
ID[1]
ID[1]
ID[0]
ID[0]
0x7D
NA
RO
WO
RW
RW
RW
RW
RW
RW
RW
RO
Device Reset
CONFIGURATION - 1
1
2
3
4
5
6
7
8
9
0x01
RESERVED
MODE[2] MODE[1] MODE[0] 0x00
CONFIGURATION - 2
0x02 IRCOM RESERVED ALSCC[5] ALSCC[4] ALSCC[3] ALSCC[2] ALSCC[1] ALSCC[0] 0x00
CONFIGURATION - 3
0x03
RESERVED
THL[6]
CONVEN
THL[4]
PRST[1]
THL[3]
PRST[0] INTSEL[1] INTSEL[0] 0x00
LOW THRESHOLD - LOW BYTE
LOW THRESHOLD - HIGH BYTE
HIGH THRESHOLD - LOW BYTE
HIGH THRESHOLD - HIGH BYTE
STATUS FLAGS
0x04 THL[7]
0x05 THL[15]
0x06 THH[7]
0x07 THH[15]
THL[5]
THL[13]
THH[5]
THL[2]
THL[10]
THH[2]
THL[1]
THL[9]
THH[1]
THH[9]
THL[0]
THL[8]
THH[0]
THH[8]
0x00
0x00
0xFF
0xFF
THL[14]
THH[6]
THL[12]
THH[4]
THL[11]
THH[3]
THH[11]
THH[14]
THH[13]
THH[12]
THH[10]
0x08
RESERVED
GRBCF[1] GRBCF[0] RESERVED BOUTF CONVENF RGBTHF 0x04
GREEN DATA - LOW BYTE
GREEN DATA - HIGH BYTE
RED DATA - LOW BYTE
RED DATA - HIGH BYTE
BLUE DATA - LOW BYTE
BLUE DATA - HIGH BYTE
0x09 GREEN[7] GREEN[6] GREEN[5] GREEN[4] GREEN[3] GREEN[2] GREEN[1] GREEN[0] 0x00
RW
RW
RW
RW
RW
RW
10 0x0A GREEN[15] GREEN[14] GREEN[13] GREEN[12] GREEN[11] GREEN[10] GREEN[9] GREEN[8] 0x00
11 0x0B RED[7]
12 0x0C RED[15]
13 0x0D BLUE[7]
RED[6]
RED[14]
BLUE[6]
RED[5]
RED[13]
BLUE[5]
RED[4]
RED[12]
BLUE[4]
RED[3]
RED[11]
BLUE[3]
RED[2]
RED[1]
RED[9]
RED[0]
RED[8]
0x00
0x00
0x00
0x00
RED[10]
BLUE[2] BLUE[1] BLUE[0]
14 0x0E BLUE[15] BLUE[14] BLUE[13] BLUE[12] BLUE[11] BLUE[10] BLUE[9] BLUE[8]
Register Description
Following are detailed descriptions of the control registers related to the operation of the ISL29125 ambient light sensor device. These
registers are accessed by the I2C serial interface. For details on the I2C interface, refer to “Serial Interface” on page 6.
All the features of the device are controlled by the registers. The ADC data can also be read. The following sections explain the details of
each register bit. All RESERVED bits are Intersil used bits ONLY. The value of the reserved bit can change without any notice.
Device Register (Address: 0x00)
TABLE 2. DEVICE ID REGISTER ADDRESS
REGISTER ADDRESS
REGISTER BITS
NAME
DEC
0
HEX
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT ACCESS
Device ID
0x00
ID[7]
ID[7]
ID[6]
ID[6]
ID[5]
ID[5]
ID[4]
ID[4]
ID[3]
ID[3]
ID[2]
ID[2]
ID[1]
ID[1]
ID[0]
ID[0]
0x7D
NA
RO
Device Reset
WO
Register 0x00 performs two functions. If Reg 0x00 is in READ ONLY mode then it will be a Device ID. By default, the device ID is 0x7D in
hex. Write 46h to register 0x00 in the WRITE ONLY, the device will reset all registers to their default states.
Configuation-1 Register (Address: 0x01)
TABLE 3. CONFIGURATION-1
REGISTER ADDRESS
REGISTER BITS
B4 B3
RESERVED RESERVED SYNC BITS RNG MODE[2] MODE[1] MODE[0]
NAME
DEC
1
HEX
B7
B6
B5
B2
B1
B0
DEFAULT ACCESS
0x00 RW
Configuration-1
0x01
FN8424 Rev.3.00
Jan 13, 2017
Page 9 of 17
ISL29125
RGB Operating Modes [B2:B0]
RGB Start Synced at INT Pin
This device has various RGB operating modes. These modes are
selected by setting B2:B0 bits in Table 4. The device powers up on
a disable mode. All operating modes are in continuous ADC
conversion. The following bits are used to enable the operating
mode.
TABLE 7. SYNCED AT INT
B5
0
OPERATION
ADC start at I2C write 0x01
ADC start at rising INT
1
TABLE 4. OPERATION MODES
SYNC has two different selectable modes at bit 5. B5 sets to 0
then the INT pin gets asserted whenever the sensor interrupts. B5
sets to 1 then the INT pin becomes input pin. On the rising edge
at INT pin, SYNC starts ADC conversion. The INT pin sets to
interrupt mode by default. More information about SYNC at
“Principles of Operation” on page 6.
B2:B0
000
001
010
011
100
101
110
111
OPERATION
Power-Down (ADC conversion)
GREEN Only
RED Only
BLUE Only
Configuration-2 Register (Address: 0x02)
Stand by (No ADC conversion)
GREEN/RED/BLUE
GREEN/RED
ACTIVE INFRARED (IR) COMPENSATION
The device is designed for operation under dark glass cover
which significantly attenuates visible light and passes the
infrared light without much attenuation. The device has an on
chip passive optical filter designed to block (reject) most of the
incident infrared. In addition, the device provides a
programmable active IR compensation which allows fine tuning
of residual infrared components from the output, which allows
optimizing the measurement variation between differing
IR-content light sources. B7 is “IR Comp Offset” and B[5:0] is “IR
Comp Adjust”, which provides means for adjusting IR
compensation. B7 = ‘0’ + B[5:0] is the effective IR compensation
from 0 to 63 codes and B7 set to ‘1’+B[5:0] the effective IR
compensation is from 106 to 169. Table 9 on page 11 shows
lightweight for each IR compensation bit and Figure 12 is a
typical system measure for both IR Comp Adjust and IR Comp
Offset. More detail about how to IR compensation, see IR
compensation in “Applications Information” on page 13.
GREEN/BLUE
RGB Data Sensing Range [B3]
The Full Scale RGB Range has two different selectable ranges at
bit 3. The range determines the ADC resolution (12 bits and
16 bits). Each range has a maximum allowable lux value. Higher
range values offer better resolution and wider lux value.
TABLE 5. SENSING RANGES
B3
0
RANGES (lux)
375
1
10,000
ADC Resolution [B4]
ADC’s resolution and the number of clock cycles per conversion is
determined by this bit in Table 6. Changing the resolution of the
ADC changes the number of clock cycles of the ADC which in turn
changes the integration time. Integration time is the period the
ADC samples the photodiode current signal for a measurement.
Recommended to set BF at register 0x02 to max out IR
compensation value. It make High range reach more than
10,000 lux.
TABLE 6. ADC RESOLUTIONS
B4
0
RESOLUTION (bits)
16
12
1
TABLE 8. CONFIGURATION-2
REGISTER BITS
B4 B3
IR-COM RESERVED ALSCC[5] ALSCC[4] ALSCC[3] ALSCC[2] ALSCC[1] ALSCC[0]
NAME
REGISTER ADDRESS
DEFAULT ACCESS
DEC
2
HEX
B7
B6
B5
B2
B1
B0
Configuration-2
0x02
0x00
RW
FN8424 Rev.3.00
Jan 13, 2017
Page 10 of 17
ISL29125
.
100
90
80
70
60
50
40
30
0x80-0xBF-IR
B[5:0]
IR COMP ADJUST
B7 is ‘0’ or ‘1’
IR COMP OFFSET
0x00-0x3F
20
10
0
0
32
64
96
128
160
192
224
256
COMPENSATION REGISTER (0x02) SET VALUE (DECIMAL)
FIGURE 12. IR COMPENSATION SET
TABLE 9.
B7
IR-COM
106
B6
B5
B4
ALSCC[4]
16
B3
ALSCC[3]
8
B2
ALSCC[2]
4
B1
B0
ALSCC[0]
1
LIGHT-WEIGHT
Codes
RESERVED
ALSCC[5]
32
ALSCC[1]
2
NOTES:
11. A illuminant is intended to represent typical, domestic, tungsten-filament lighting. Its CCT is about 2856K.
12. D series of illuminants are constructed to represent natural daylight. D65 is used in lab to represent as noon light to test. Its CCT is 6504K.
13. F series of illuminants represent various types of fluorescent lighting. F2 is cool white fluorescent used in lab to test. Its CCT is 4230K.
Configuration-3 Register (Address: 0x03)
TABLE 10. CONFIGURATION-3
NAME
REGISTER ADDRESS
REGISTER BITS
B4 B3
RESERVED RESERVED RESERVED CONVEN PRST[1] PRST[0] INTSEL[1] INTSEL[0] 0x00
DEFAULT ACCESS
DEC
3
HEX
B7
B6
B5
B2
B1
B0
CONFIGURATION-3
0x03
RW
INTERRUPT THRESHOLD ASSIGNMENT [B1:0]
INTERRUPT PERSIST CONTROL [B3:2]
The interrupt status bit (RGBTHF) bit0 at Reg0x08 is a status bit
for light intensity detection. The bit is set to logic HIGH when the
light intensity crosses the interrupt thresholds window (register
address 0x04 - 0x07) and set to logic LOW when it’s within the
interrupt thresholds window. Once the interrupt is triggered, the
INT pin goes low and the interrupt status bit goes HIGH until the
status bit is polled through the I2C read command. Both the INT
pin and the interrupt status bit are automatically cleared at the
end of the 8-bit Device Register byte (0x08) transfer. Table 11
shows selectable interrupt for the device.
To minimize interrupt events due to 'transient' conditions, an
interrupt persistency option is available. IN the event of a
transient condition, an 'X-consecutive' number of interrupt must
happen before the interrupt flag and PINT (INT) pin gets driven
low. The interrupt is active-low and remains asserted until the
status register (Addr: 0x08) is read to CLEAR the bit(s).
TABLE 12. INTERRUPT PERSIST
B3:2
00
NUMBER OF INTEGRATION CYCLE
1
2
4
8
01
TABLE 11. INTERRUPT STATUS
10
B1:0
00
INTERRUPT STATUS
No Interrupt
11
01
GREEN Interrupt
RED Interrupt
BLUE Interrupt
RGB CONVERSION DONE TO INT CONTROL [B4]
10
TABLE 13.
11
B4
0
CONVERSION DONE
Disable
Enable
1
FN8424 Rev.3.00
Jan 13, 2017
Page 11 of 17
ISL29125
Lower Interrupt Register (Address: 0x04 and 0x05) and Higher Interrupt Register
(Address: 0x06 and 0x07)
TABLE 14. CONFIGURATION-3
NAME
REGISTER ADDRESS
REGISTER BITS
B4 B3
DEFAULT ACCESS
DEC
4
HEX
0x04
0x05
0x06
0x07
B7
B6
B5
B2
B1
B0
Low Threshold - Low byte
Low Threshold - High byte
High Threshold - Low byte
High Threshold - High byte
THL[7] THL[6] THL[5] THL[4] THL[3] THL[2] THL[1] THL[0]
THH[7] THH[6] THH[5] THH[4] THH[3] THH[2] THH[1] THH[0]
THL[7] THL[6] THL[5] THL[4] THL[3] THL[2] THL[1] THL[0]
THH[7] THH[6] THH[5] THH[4] THH[3] THH[2] THH[1] THH[0]
0x00
0x00
0xFF
0xFF
RW
RW
RW
RW
5
6
7
Interrupt Threshold (Reg 0x4, Reg0x5, Reg0x6 and Reg0x7)
The interrupt threshold level is a 16-bit number (Low Threshold-1 and Low Threshold-2). The lower interrupt threshold registers are used
to set the lower trigger point for interrupt generation. If the ALS value crosses below or is equal to the lower threshold, an interrupt is
asserted on the interrupt pin (LOW) and the interrupt status bit (HIGH). Registers Low Threshold-1 (0x04 or 0x6) and Low Threshold-2
(0x05 or 0x7) provide the low and high bytes, respectively, of the lower interrupt threshold. The interrupt threshold registers default to
0x00 upon power-up. The user can also configure the persistency for the interrupt pin. This reduces the possibility of false triggers, such
as noise or sudden spikes in ambient light conditions or an unexpected camera flash, for example, can be ignored by setting the
persistency to 8 integration cycles.
Status Flag Register (Address: 0x08)
TABLE 15. STATUS FLAG REGISTER
REGISTER
NAME
ADDRESS
HEX
REGISTER BITS
B4 B3
DEFAULT ACCESS
Status Flag DEC
8
B7
B6
B5
B2
B1
B0
0x08 RESERVED RESERVED RGBCF[1] RGBCF[0] RESERVED
BOUTF
CONVENF RGBTHF
0x04
RO
RGBTHF [B0]
BOUTF [B2]
This is the status bit of the interrupt. The bit is set to logic high
when the interrupt thresholds have been triggered (out of
threshold window) and logic low when not yet triggered. Once
activated and the interrupt is triggered, the INT pin goes low and
the interrupt status bit goes high until the status bit is polled
through the I2C read command. Both the INT output and the
interrupt status bit are automatically cleared at the end of the
8-bit (00h) command register transfer
Bit2 on register address 0x08 is a status bit for brownout
condition (BOUT). The default value of this bit is HIGH, BOUT = 1,
during the initial power-up. This indicates the device may possibly
have gone through a brownout condition. Therefore, the status
bit should be reset to LOW, BOUT = 0, by an I2C write command
during the initial configuration of the device. The default register
value is 0x04 at power-on.
TABLE 18. BROWNOUT FLAG
TABLE 16. INTERRUPT FLAG
B2
0
OPERATION
B0
0
OPERATION
Interrupt is cleared or not triggered yet
Interrupt is triggered
No Brownout
Power-down or Brownout occurred
1
1
RGBCF [B5:B4]
CONVENF [B1]
B[5:4] are flag bits to display either Red Green or Blue is under
conversion process at Table 19.
This is the status bit of conversion. The bit is set to logic high
when the conversion have been completed and logic low when
the conversion is not done or not conversion.
TABLE 19. CONVERSION FLAG
B5:4
00
RGB UNDER CONVERSION
No Operation
TABLE 17. CONVERSION FLAG
B1
0
OPERATION
Still convert or cleared
Conversion completed
01
GREEN
RED
10
1
11
BLUE
FN8424 Rev.3.00
Jan 13, 2017
Page 12 of 17
ISL29125
Data Register (Address: 0x09,0x0A,0xB,0xC,0xD and 0xE)
TABLE 20. CONFIGURATION-3
REGISTER
NAME
ADDRESS
DEC HEX
REGISTER BITS
B4 B3
DEFAULT ACCESS
B7
B6
B5
B2
B1
B0
GREEN Data - Low Byte
9
0x09 GREEN[7] GREEN[6] GREEN[5] GREEN[4] GREEN[3] GREEN[2] GREEN[1] GREEN[0] 0x00
RW
RW
RW
RW
RW
RW
GREEN Data - High Byte 10 0x0A GREEN[15] GREEN[14] GREEN[13] GREEN[12] GREEN[11] GREEN[10] GREEN[9] GREEN[8] 0x00
RED Data - Low Byte
RED Data - High Byte
RED Data - Low Byte
RED Data - High Byte
11 0x0B RED[7]
12 0x0C RED15]
13 0x0D BLUE[7]
RED[6]
RED[14]
BLUE[6]
RED[5]
RED[13]
BLUE[5]
RED[4]
RED[12]
BLUE[4]
RED[3]
RED[11]
BLUE[3]
RED[2]
RED[10]
BLUE[2]
RED[1]
RED[9]
RED[0]
RED[8]
0x00
0x00
0x00
0x00
BLUE[1] RED[0]
14 0x0E BLUE[15] BLUE[14] BLUE[13] BLUE[12] BLUE[11] BLUE[10] BLUE[9] RED[8]
The ISL29125 has two 8-bit read-only registers to hold the higher and lower byte of the ADC value. The lower and higher bytes are
accessed at address, respectively. For 16-bit resolution, the data is from D0 to D15; for 12-bit resolution, the data is from D0 to D11.
The registers are refreshed after every conversion cycle. The default register value is 0x00 at power-on. Because all the register are
double buffered the data is always valid on the data registers.
RGB → XYZ TRANSFORM
Applications Information
Once the proper compensation setting is determined, measure
the RGB values of the various illuminates at this value. Calculate
the RGB to XYZ transform coefficients based on the measured
Figure 13 is a plot of the 1931 standard normalized spectral
response of various types of light sources for reference.
result against appropriate Chroma Meter Standard (using x and y
values) as shown in Equation 1.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
NORMALIZED TO GREEN
C
C
C
C
C
XR XG XB
X
Y
Z
R
G
B
=
x
RED
C
C
(EQ. 1)
YR YG YB
GREEN
BLUE
C
C
ZR ZG ZB
1931 STD RED
1931 STD GREEN
1931 STD BLUE
X, Y and Z are in the IEC system which specifies the color and
brightness of a particular homogeneous visual stimulus.
0.4
0.2
0.0
R, G and B are digital output from the sensor.
Cs are coefficents. These coefficients will be changed
respectively depending on the system setup.
350 380 410 440 470 500 530 560 590 620 650 680 710 740 770 800 830
WAVELENGTH
COMPENSATION
FIGURE 13. 1931 STANDARD NORMALIZED SPECTRAL RESPONSE
OF LIGHT SOURCES
The compensation adjustment is used to balance the various
illuminates of interest (A, F2 and D65 recommended) such that
the value measured at the same power level (measured with a
lux meter) is the closed value. Since the compensation
adjustment is piecewise linear the proper setting can be
determined by extrapolating from a pair of measurements and
calculating the closest intersection of the sources of interest.
System Compensation and RGB to XYZ
Transform (Chroma Meter)
The accuracy of the RGB sensor is extremely sensitive to the
optomechanical design of the system in which it resides. The
compensation setting and calculation of RGB to XYZ transform
should be characterized within that environment with as many
standard illuminants as possible. A minimal recommended set
would include A, F2 and D65 illuminants (see Notes 11, 12, 13
and “References” on page 15 about IEC 1931, Planckian locus
and standard illuminants). The two most important
The Configuration register (Reg 0x02[7:0]) allows coarse tuning
B7 and fine tuning (B[5:0] of the residual infrared component
from the ALS output.
optomechnical features are FOV (Field Of View FWHM) and
optical filters as example of tinted cell phone glass through
which the sensor will detect the ambient lighting. With the
combination of the FOV and a large sample for the filter
(30x30mm) it is possible to determine the best compensation
and XYZ transform coefficients. It is also possible to project the
accuracy of the measurement system.
FN8424 Rev.3.00
Jan 13, 2017
Page 13 of 17
ISL29125
The recommended procedure for determining ALS IR
compensation is as follows:
Noise Rejection
Electrical AC power worldwide is distributed at either 50Hz or
60Hz. Artificial light sources vary in intensity at the AC power
frequencies. The undesired interference frequencies are infused
on the electrical signals. This variation is one of the main sources
of noise for the light sensors. Integrating type ADC’s have
excellent noise-rejection characteristics for periodic noise
sources whose frequency is an integer multiple of the conversion
rate. By setting the sensor’s integration time to an integer
multiple of periodic noise signal, the performance of an ambient
light sensor can be improved greatly in the presence of noise. In
order to reject the AC noise, the integration time of the sensor
must be adjusted to match the AC noise cycle. For instance, a
60Hz AC unwanted signal’s sum from 0ms to k*16.66ms
(k = 1, 2...ki) is zero. Similarly, setting the device’s integration
time as an integer multiple of the periodic noise signal greatly
improves the light sensor output signal in the presence of noise.
• Illuminate the ISL29125 based design configuration with a no
IR F2 light source. Record the ALS measurement and the lux
level.
• Illuminate the device with A and D65 with heavy IR and the F2
light sources. Take an ALS measurement and lux level
measurement.
• It really depends on the system setup in order to adjust the
Configuration register (Reg 0x02, B7 and B[5:0]) to
compensate for the IR contribution.
• Repeat steps above until the IR light source contribution to the
ALS measurement is under 10 percent assuming no change in
lux level due to IR light source.
Figure 14 is an example showing how to calculate the
compensation for varying level of infrared components such as
A, F2 and D65 (see Notes 11, 12 and 13 on page 11). With
compensation adjustment from 0% to 100%. The crossing point
is the IR compensation value which results in tighter variation
with varying levels of infrared components. This setup system is
a sensor without IR tinted glass and is illuminated with 3
different light sources. Since it is not under IR tinted glass, then
reg0x2 setups like b7 = ‘0’ and B[5:0] is at about 25%
Layout and Board Mounting
Considerations
Suggested PCB Footprint
It is important that users check TB477 “Surface Mount Assembly
Guidelines for Optical Dual Flat Pack No Lead (ODFN) Package”
before starting ODFN product board mounting.
compensation adjust (%/range) which means about 40 codes.
Board Mounting
12000
For applications requiring the light measurement, the board
mounting location should be reviewed. The device uses an
Optical Dual Flat Pack No Lead (ODFN) package, which subjects
the die to mild stresses when the printed circuit (PC) board is
heated and cooled, which slightly changes the shape. Because of
these die stresses, placing the device in areas subject to slight
twisting can cause degradation of reference voltage accuracy. It
is normally best to place the device near the edge of a board, or
on the shortest side, because the axis of bending is most limited
in that location.
10000
A
8000
D65
6000
4000
F2
2000
0
Layout
0
20
40
60
80
100
COMPENSATION ADJUSTMENT (% RANGE)
The ISL29125 is relatively insensitive to layout. Similar to other
I2C devices, it is intended to provide excellent performance even
in significantly noisy environments. There are only a few
considerations that will ensure best performance.
FIGURE 14. IR COMPENSATION VALUE
Calculating Lux
Route the supply and I2C traces as far as possible from all
sources of noise. Use two power-supply decoupling capacitors,
1µF and 0.1µF, placed close to the device.
Y-coordinate is Ev measured in lux. The data can be converted to
lux by using an equation. There are two different data sensing
ranges (375 lux and 10,000 lux) and also two different resolution
selections (16 bits and 12 bits) on this device. Equation 2 is
dependent on both these parameters.
Soldering
Convection heating is recommended for reflow soldering; direct
infrared heating is not recommended. The plastic ODFN package
does not require a custom reflow soldering profile and is
qualified to +260°C. A standard reflow soldering profile with a
+260°C maximum is recommended.
Ev = Y = CYRxRed + CYGxGreen + CYBxBluexRange
(EQ. 2)
FN8424 Rev.3.00
Jan 13, 2017
Page 14 of 17
ISL29125
Typical Circuit
0.11
0.13
A typical application for the ISL29125 is shown in Figure 15. The
ISL29125’s I2C address is internally hard-wired as 1000100. The
device can be tied onto a system’s I2C bus together with other I2C
compliant devices.
scl
vdd
6
5
4
1
2
R1
C1
C2
Vbus
VDD
R2 R3 R4
intb
sda
1
SENSOR
vss
VDD
3
SDA
SCL
SDA
SCL
INT
4
6
0.24
0.48
2
ISL29125
NC
MCU
FIGURE 16. 6 LD ODFN SENSOR LOCATION OUTLINE
GPIO
5
GND
3
R1 - 100Ω
R2 - 2.7kΩ to 10kΩ
References
R
R
C
3 - 2.7kΩ to 10kΩ
4 - 2.7kΩ to 10kΩ
1 - 1µF
[1] Standard illuminants
[2] Planckian locus approximation
C2 - 0.1µF
[3] CIE 1931 2°, XYZ CMFs modified by Judd (1951) and Vos
(1978)
FIGURE 15. ISL29125 TYPICAL CIRCUIT
FN8424 Rev.3.00
Jan 13, 2017
Page 15 of 17
ISL29125
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN8424.3
CHANGE
January 15, 2016
Made correction to “Block Diagram” on page 2.
Page 3 Thermal Information - changed Note 4 from:
“JA is measured in free air with the component mounted on a high effective thermal conductivity test board
with “direct attach” features. See Tech Brief TB379.”
to:
“JA is measured with the component mounted on a high effective thermal conductivity test board in free air.
See Tech Brief TB379 for details.”
Removed “Digital Inputs and Termination” and “Temperature Coefficient” sections from “Applications
Information”
Updated POD L6.1.65x1.65 from rev 1 to rev 2. Changes since rev 1:
Tiebar Note updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
January 24, 2014
FN8424.2
FN8424.1
Page 2, Ordering Information table:
Changed Evaluation Board part # from: ISL29125IROZ-EVALZ to: ISL29125EVAL1Z
Page 9 - added Device Reset row to Tables 1 and 2.
December 23, 2013
Added Related Literature on page 1.
Updated “Interrupt Function” on page 6.
Edited last two rows in Table 20 on page 13.
Changed RED to BLUE and Register DEC column from 11 and 12 to 13 and 14.
November 20, 2013
FN8424.0
Initial Release
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modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8424 Rev.3.00
Jan 13, 2017
Page 16 of 17
ISL29125
Package Outline Drawing
L6.1.65x1.65
6 LEAD OPTICAL DUAL FLAT NO-LEAD PLASTIC PACKAGE (ODFN)
Rev 2, 4/15
1.65
0.55
0.70
PIN #1 INDEX AREA
6
PIN 1
1.65
0.50
0.25
4
0.20
(4X)
0.10
0.10
M CAB
0.85
0.40
TOP VIEW
BOTTOM VIEW
PACKAGE OUTLINE
0.75
SEE DETAIL "X"
0.10 C
0.70
0.70 ± 0.05
C
0.25
BASE PLANE
0.62
SEATING PLANE
0.08 C
SIDE VIEW
0.50
1.02
5
C
0 . 2 REF
0.60
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL “X”
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
4.
Unless otherwise specified, tolerance : Decimal ± 0.05
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
6.
Tiebar shown (if present) is a non-functional feature and may
be located on any of the 4 sides (or ends).
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN8424 Rev.3.00
Jan 13, 2017
Page 17 of 17
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