ISL34341INZ-T13 [RENESAS]
WSVGA 24-Bit Long-Reach Video SERDES with Bi-directional Side-Channel; TQFP64; Temp Range: -40° to 85°C;
| 型号： | ISL34341INZ-T13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | WSVGA 24-Bit Long-Reach Video SERDES with Bi-directional Side-Channel; TQFP64; Temp Range: -40° to 85°C 接口集成电路 |
| 文件： | 总11页 (文件大小：607K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL34341
FN6827
Rev 1.00
Jun 19, 2008
WSVGA 24-Bit Long-Reach Video SERDES with Bi-directional Side-Channel
The ISL34341 is a serializer/deserializer of LVCMOS parallel
video data. The video data presented to the serializer on the
Features
• 24-bit RGB transport over single differential pair
• 6MHz to 40MHz pixel clock rates
parallel LVCMOS bus is serialized into a high-speed
differential signal. This differential signal is converted back to
parallel video at the remote end by the deserializer. It also
transports auxiliary data bi-directionally over the same link
during the video vertical retrace interval.
• Bi-directional auxiliary data transport without extra
bandwidth and over the same differential pair
2
• I C Bus Mastering to the remote side of the link with a
2
I C bus mastering allows the placement of external slave
controller on either the serializer or deserializer
2
devices on the remote side of the link. An I C controller can
• 40MHz PCLK transports
2
be placed on either side of the link allowing bi-directional I C
- SVGA 800x600 @ 70fps, 16% blanking
- WSVGA 1024x600 @ 60fps, 8% blanking
communication through the link to the external devices on
the other side. Both chips can be fully configured from a
single controller or independently by local controllers.
• Internal 100 termination on high-speed serial lines
• DC balanced with industry standard 8b/10b line code
allows AC-coupling
Ordering Information
- Provides immunity against ground shifts
PART
NUMBER
(Note)
TEMP.
RANGE
(°C)
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
• Hot plugging with automatic resynchronization every line
• 16 programmable settings each for transmitter amplitude
boost and pre-emphasis and receiver equalization allow
for longer cable lengths and higher data rates
ISL34341INZ* ISL34341INZ -40 to +85 64 Ld EPTQFP Q64.10x10C
*Add “-T13” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
• Programmable power-down of the transmitter and the
receiver
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
• Same device for serializer and deserializer simplifies
inventory
2
• I C communication interface
• 8kV ESD rating for serial lines
• Pb-free (RoHS compliant)
Applications
• Navigation and display systems
• Video entertainment systems
• Industrial computing terminals
• Remote cameras
3.3V
1.8V
VDD_IO
3.3V
1.8V
VDD_IO
24
24
10m DIFFERENTIAL CABLE
27nF
27nF
27nF
27nF
RGBA/B/C
RGBA/B/C
SERIOP
SERIOP
VSYNC
VSYNC
HSYNC
VIDEO
SOURCE
VIDEO
SINK
HSYNC
DATAEN
PCLK_IN
ISL34341
ISL34341
SERION
SERION
PCLK_IN
DATAEN
PCLK_OUT
REF_CLK
VDD_IO
VDD_IO
FN6827 Rev 1.00
Jun 19, 2008
Page 1 of 11
ISL34341
Pinout
ISL34341
(64 LD TQFP)
TOP VIEW
VIDEO_TX
VDD_IO
PCLK_OUT
RGBA0
RGBA1
RGBA2
RGBA3
RGBA4
RGBA5
RGBA6
RGBA7
RGBB0
RGBB1
RGBB2
RGBB3
GND_IO
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
I2CA2
I2CA3
SDA
SCL
VDD_P
GND_P
PCLK_IN
VSYNCPOL
HSYNCPOL
VSYNC
HSYNC
DATAEN
VDD_CR
VDD_CR
GND_CR
GND_CR
Block Diagram
SCL
SDA
I2C
VCM
GENERATOR
RAM
TDM
SERIOP
SERION
PRE-
EMPHASIS
TX
3
V/H/DE
MUX
DEMUX
8b/10b
RGB
24
RX EQ
VIDEO_TX
(HI)
CDR
PCLK_IN
x30
(REF_CLK WHEN
VIDEO_TX IS LO)
PCLK_OUT
30
FN6827 Rev 1.00
Jun 19, 2008
Page 2 of 11
ISL34341
Absolute Maximum Ratings
Thermal Information
Supply Voltage
VDD_P to GND_P, VDD_TX to GND_TX,
Thermal Resistance (Typical, Notes 1, 2)
EPTQFP. . . . . . . . . . . . . . . . . . . . . . . .
(°C/W)
12
JA
40
JC
VDD_IO to GND_IO . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.6V
VDD_CDR to GND_CDR, VDD_CR to GND_CR . . -0.5V to 2.5V
Between any pair of GND_P, GND_TX,
GND_IO, GND_CDR, GND_CR . . . . . . . . . . . . . -0.1V to 0.1V
3.3V Tolerant LVTTL/LVCMOS
Input Voltage . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD_IO + 0.3V
Differential Input Voltage . . . . . . . . . . . . . . .-0.3V to VDD_IO + 0.3V
Differential Output Current . . . . . . . . . . . . . .Short Circuit Protected
LVTTL/LVCMOS Outputs. . . . . . . . . . . . . . . .Short Circuit Protected
ESD Rating
Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 327mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Human Body Model
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4kV
SERIOP/N (all VDD Connected, all GND Connected) . . . . .8kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
2. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V
,
VDD_TX = VDD_P = VDD_AN = 3.3V, T = +25°C, Ref_Res = 3.16k, High-speed AC-coupling
A
capacitor = 27nF.
PARAMETER
POWER SUPPLY VOLTAGE
VDD_CDR, VDD_CR
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.7
3.0
1.8
3.3
1.9
3.6
V
V
VDD_TX, VDD_P, VDD_AN, VDD_IO
SERIALIZER POWER SUPPLY CURRENTS
Analog TX Supply Current
Analog CDR Supply Current
Digital I/O Supply Current
I
VIDEO_TX = 1
PCLK_IN = 40MHz
17
57
1
mA
mA
mA
mA
mA
mA
mA
mA
DDTX
I
DDCDR
I
2
DDIO
Digital Supply Current
I
20
17
5.5
77
40
DDCR
PLL/VCO Supply Current
I
DDP
DDAN
Analog Bias Supply Current
Total 1.8V Supply Current
I
90
46
Total 3.3V Supply Current
DESERIALIZER POWER SUPPLY CURRENTS
Analog TX Supply Current
Analog CDR Supply Current
Digital I/O Supply Current
I
VIDEO_TX = 0
REF_CLK = 40MHz
24
45
17
32
17
5.4
77
64
mA
mA
mA
mA
mA
mA
mA
mA
DDTX
I
DDCDR
I
25
DDIO
Digital Supply Current
I
DDCR
PLL/VCO Supply Current
I
DDP
DDAN
Analog Bias Supply Current
Total 1.8V Supply Current
I
90
80
Total 3.3V Supply Current
FN6827 Rev 1.00
Jun 19, 2008
Page 3 of 11
ISL34341
Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V
,
VDD_TX = VDD_P = VDD_AN = 3.3V, T = +25°C, Ref_Res = 3.16k, High-speed AC-coupling
A
capacitor = 27nF. (Continued)
PARAMETER
POWER-DOWN SUPPLY CURRENT
Total 1.8V Power-Down Supply Current
Total 3.3V Power-Down Supply Current
PARALLEL INTERFACE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RSTB = GND;
spec is per device
0.5
1
mA
mA
High Level Input Voltage
V
2.0
-10
V
V
IH
Low Level Input Voltage
V
0.8
10
IL
IN
Input Leakage Current
I
±0.01
µA
V
High Level Output Voltage
V
I
I
= -2.0mA, VDD_IO = 3V 0.8*VDD_IO
= 2.0mA, VDD_IO = 3V
OH
OH
OL
Low Level Output Voltage
V
0.2*VDD_IO
50
V
OL
Output Short Circuit Current
Output Rise and Fall Times
I
mA
ns
OSC
/t
t
Slew rate control set to min,
= 8pF
1
4
OR OF
C
L
Slew rate control set to max,
= 8pF
ns
C
L
SERIALIZER PARALLEL INTERFACE
PCLK_IN Frequency
f
6
40
60
MHz
%
IN
PCLK_IN Duty Cycle
t
40
3.6
1.6
50
IDC
Parallel Input Setup Time
t
ns
IS
IH
Parallel Input Hold Time
t
ns
DESERIALIZER PARALLEL INTERFACE
PCLK_OUT Frequency
f
6
40
MHz
%
OUT
PCLK_OUT Duty Cycle
t
50
0.5
±20
ODC
PCLK_OUT Period Jitter (rms)
PCLK_OUT Spread Width
Time to Parallel Output Data Valid
Deserializer Output Latency
t
Clock randomizer off
Clock randomizer on
Relative to PCLK_OUT
%t
%t
OJ
PCLK
t
OSPRD
PCLK
ns
t
-4.7
4
5.5
14
DV
t
Part-to-part,
9
PCLK
CPD
side-channel disabled
DESERIALIZER REFERENCE CLOCK (REF_CLK IS FED INTO PCLK_IN)
REF_CLK Lock Time
t
100
µs
PLL
REF_CLK to PCLK_OUT Maximum Frequency
Offset
PCLK_OUT is the
recovered clock
1500
600
5000
ppm
HIGH-SPEED TRANSMITTER
HS Differential Output Voltage, Transition Bit
VOD
TXCN = 0x00
TXCN = 0x0F
TXCN = 0xF0
TXCN = 0xFF
TXCN = 0x00
TXCN = 0x0F
TXCN = 0xF0
TXCN = 0xFF
825
1170
975
1300
825
460
975
600
990
990
mV
mV
mV
mV
mV
mV
mV
mV
TR
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
HS Differential Output Voltage, Non-Transition Bit VOD
600
NTR
FN6827 Rev 1.00
Jun 19, 2008
Page 4 of 11
ISL34341
Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V
,
VDD_TX = VDD_P = VDD_AN = 3.3V, T = +25°C, Ref_Res = 3.16k, High-speed AC-coupling
A
capacitor = 27nF. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
2.35
20
MAX
UNITS
V
HS Generated Output Common Mode Voltage
V
OCM
HS Common Mode Serializer-Deserializer
Voltage Difference
V
120
mV
CM
HS Differential Output Impedance
HS Output Latency
R
80
4
100
7
120
10
PCLK
ps
OUT
t
t
Part-to-part
LPD
HS Output Rise and Fall Times
HS Differential Skew
t
20% to 80%
150
<10
13.4
40
R/ F
t
ps
SKEW
HS Output Random Jitter
t
t
ps
ps
RJ
DJ
rms
P-P
HS Output Deterministic Jitter
HIGH SPEED RECEIVER
HS Differential Input Voltage
HS Generated Input Common Mode Voltage
HS Differential Input Impedance
HS Maximum Jitter Tolerance
V
150
80
mV
P-P
ID
V
2.32
100
V
ICM
R
120
IN
0.52
UI
P-P
2
I C
2
I C Clock Rate (on SCL)
f
100
400
1
kHz
I2C
2
I C Clock Pulse Width (HI or LO)
1.3
0
µs
µs
µs
ns
ns
ms
2
I C Clock Low to Data Out Valid
2
I C Start/Stop Setup/Hold Time
0.6
100
100
100
2
I C Data in Setup Time
2
I C Data in Hold Time
2
I C Data out Hold Time
Pin Descriptions
DESCRIPTION
PIN NUMBER
PIN NAME
RGBA[7:0],
SERIALIZER
DESERIALIZER
52 to 63,
2 to 13
Parallel video data LVCMOS inputs
Parallel video data LVCMOS outputs
RGBB[7:0], RGBC[7:0]
22
23
HSYNC
Horizontal (line) Sync LVCMOS input
Vertical (frame) Sync LVCMOS input
Video Data Enable LVCMOS input
Pixel clock LVCMOS input
Horizontal (line) Sync LVCMOS output
Vertical (frame) Sync LVCMOS output
Video Data Enable LVCMOS output
PLL reference clock LVCMOS input
Recovered clock LVCMOS output
High speed differential serial I/O
VSYNC
21
DATAEN
26
PCLK_IN
51
PCLK_OUT
SERIOP, SERION
HSYNCPOL
Default; not used
41, 40
24
High speed differential serial I/O
CMOS input for HSYNC
1: HSYNC is active low
0: HSYNC is active high
25
VSYNCPOL
CMOS input for VSYNC
1: VSYNC is active low
0: VSYNC is active high
FN6827 Rev 1.00
Jun 19, 2008
Page 5 of 11
ISL34341
Pin Descriptions (Continued)
DESCRIPTION
PIN NUMBER
PIN NAME
VIDEO_TX
SERIALIZER
DESERIALIZER
49
CMOS input for video flow direction
1: video serializer
0: video deserializer
2
2
2
29, 30
31 to 34
35
SCL, SDA
I2CA[3:0]
MASTER
I C Interface Pins (I C DATA, I C CLK)
2
I C Device Address
2
I C Master Mode
1: Master
0: Slave
16
14
RSTB/PDB
STATUS
CMOS input for Reset and Power-down. For normal operation, this pin must be forced high. When
this pin is forced low, the device will be reset. If this pin stays low, the device will be in PD mode.
CMOS output for Receiver Status:
1: Valid 8b/10b data received
0: otherwise
Note: serializer and deserializer switch roles during side-channel reverse traffic
36
27
REF_RES
GND_P
Analog bias setting resistor connection; use 3.16k ±1% to ground
PLL Ground
48, 64
44, 45
39, 42
37
GND_IO
Digital (Parallel and Control) Ground
Analog (Serial) Data Recovery Ground
Analog (Serial) Output Ground
Analog Bias Ground
GND_CDR
GND_TX
GND_AN
GND_CR
VDD_CR
VDD_TX
VDD_AN
VDD_CDR
VDD_IO
17, 18
19, 20
43
Core Logic Ground
Core Logic VDD
Analog (Serial) Output VDD
Analog Bias VDD
38
46, 47
1, 50
28
Analog (Serial) Data Recovery VDD
Digital (Parallel and Control) VDD
PLL VDD
VDD_P
15
TEST_EN
Exposed Pad
Must be connected to ground
Must be connected to ground
Exposed Pad
NOTES:
3. Pins with the same name are internally connected together. However, this connection must NOT be used for connecting together external
components or features.
4. The various differently-named Ground pins are internally weakly connected. They must be tied together externally. The different names are
provided to assist in minimizing the current loops involved in bypassing the associated supply VDD pins. In particular, for ESD testing, they
should be considered a common connection.
FN6827 Rev 1.00
Jun 19, 2008
Page 6 of 11
ISL34341
Diagrams
VODTR
VODNTR
TXCN
0x00
0x0F
0xF0
0xFF
FIGURE 1. VOD vs TXCN SETTING
1/f
t
IDC
IN
VIDEO_TX = 1
PCLK_IN
t
t
IH
VALID DATA
IS
RGB[A:C][7:0]
VALID DATA
DATA
DATA
VALID DATA
t
t
IS
IH
HSYNC
VSYNC
DATAEN
FIGURE 2. PARALLEL VIDEO INPUT TIMING [HSYNCPOL = 0, VSYNCPOL = 0, PCLKPOL (reg) = 0]
FN6827 Rev 1.00
Jun 19, 2008
Page 7 of 11
ISL34341
VIDEO_TX = 0
T
t
t
OF
1/f
ODC
OR
OU
PCLK_OUT
t
DV
VALID DATA
VALID DATA
DATA HELD AT PREVIOUS
VALID DATA
RGB[A:C][7:0]
t
DV
HSYNC
VSYNC
DATAEN
FIGURE 3. PARALLEL VIDEO OUTPUT TIMING [HSYNCPOL = 0, VSYNCPOL = 0, PCLKPOL (reg) = 0]
The high bit rate of the differential serial data requires special
care in the layout of traces on PCBs, in the choice and
assembly of connectors, and in the cables themselves.
Applications
Overview
A pair of ISL34341 SERDES transports 24-bit parallel video
(16-bit parallel video for the ISL34321) along with auxiliary data
over a single 100 differential cable either to a display or from
a camera. Auxiliary data is transferred in both directions and
can be used for remote configuration and telemetry.
PCB traces need to be adjacent and matched in length (so as
to minimize the imbalanced coupling to other traces or
elements) and of a geometry to match the impedance of the
transmitter and receiver to minimize reflections. Similar care
needs to be applied to the choice of connectors and cables.
The benefits include lower EMI, lower costs, greater reliability
and space savings. The same device can be configured to be
either a serializer or deserializer by setting one pin
(VIDEO_TX), simplifying inventory. RGBA/B/C, VSYNC,
HSYNC, and DATAEN pins are inputs in serializer mode and
outputs in deserializer mode.
SERIOP and SERION pins incorporate internal differential
termination of the serial signal lines.
SERIO Pin AC-Coupling
AC-coupling minimizes the effects of DC common mode
voltage difference and local power supply variations between
two SERDES. The serializer outputs DC balanced 8b/10b line
code, which allows AC-coupling.
The video data presented to the serializer on the parallel
LVCMOS bus is serialized into a high-speed differential signal.
This differential signal is converted back to parallel video at the
remote end by the deserializer. The Side Channel data is
transferred between the SERDES pair during two lines of the
vertical video blanking interval.
The AC-coupling capacitor on SERIO pins must be 27nF on
the serializer board and 27nF on the deserializer board. The
value of the AC-coupling capacitor is very critical since a value
too small will attenuate the high speed signal at low clock rate.
A value too big will slow down the turn around time for the side-
channel.
When the side-channel is enabled, there will be a number of
PCLK cycles uncertainty from frame-to-frame. This should not
cause sync problems with most displays, as this occurs during
the vertical front porch of the blanking period. When properly
configured, the SERDES link supports end-to-end transport
Receiver Reference Clock (REF_CLK)
The reference clock (REF_CLK) for the PLL is fed into
PCLK_IN pin. REF_CLK is used to recover the clock from the
high speed serial stream. REF_CLK is very sensitive to any
instability. The following conditions must be met at all times
after power is applied to the deserializer, or else the
deserializer may need a manual reset:
10
with fewer than one error in 10 bits.
Differential Signals and Termination
The ISL34341 serializes the 24-bit parallel data along with
3 sync signals at 30x the PCLK_IN frequency. The ISL34321
serializes the 16-bit parallel data plus 3 sync signals at 20x the
PCLK_IN frequency. The extra 2 bits per word come from the
8b/10b encoding scheme which helps create the highest
quality serial link.
• REF_CLK frequency must be within the limits specified
• REF_CLK amplitude must be stable.
A simple 3.3V CMOS crystal oscillator can be used for
REF_CLK.
FN6827 Rev 1.00
Jun 19, 2008
Page 8 of 11
ISL34341
supplies are tied together, the PCB layout should be arranged
to emulate this arrangement, at least for the smaller value
(high frequency) capacitors, as much as possible.
Power Supply Sequencing
The 3.3V supply must be higher than the 1.8V supply at all
times, including during power-up and power-down. To meet
this requirement, the 3.3V supply must be powered up before
the 1.8V supply.
For the deserializer, REF_CLK must not be applied before the
device is fully powered up. Applying REF_CLK before power-
up may require the deserializer to be manually reset. A 10ms
delay after the 1.8V supply is powered up guarantees normal
operation.
Power Supply Bypassing
The serializer and deserializer functions rely on the stable
functioning of PLLs locked to local reference sources or locked
to an incoming signal. It is important that the various supplies
(VDD_P, VDD_AN, VDD_CDR, VDD_TX) be well bypassed
over a wide range of frequencies, from below the typical loop
bandwidth of the PLL to approaching the signal bit rate of the
serial data. A combination of different values of capacitors from
1000pF to 5µF or more with low ESR characteristics is
generally required.
FIGURE 4. POWER SUPPLY BYPASSING
The parallel LVCMOS VDD_IO supply is inherently less
sensitive, but since the RGB and SYNC/DATAEN signals can
all swing on the same clock edge, the current in these pins and
the corresponding GND pins can undergo substantial current
flow changes, so once again, a combination of different values
of capacitors over a wide range, with low ESR characteristics,
is desirable.
2
I C Interface
2
The I C interface allows access to internal registers used to
configure the SERDES and to obtain status information. A
serializer must be assigned a different address than its
deserializer counterpart. The upper 3 bits are permanently set
to 011 and the lower 4 bits determined by pins as follows:
0
1
1
I2CA3 I2CA2 I2CA1 I2CA0 R/W
A set of arrangements of this type is shown in Figure 4, where
each supply is bypassed with a ferrite-bead-based choke, and
a range of capacitors. A “choke” is preferable to an “inductor” in
this application, since a high-Q inductor will be likely to cause
one or more resonances with the shunt capacitors. This
potentially causes problems at or near those frequencies, while
a “lossy” choke will reflect a high impedance over a wide
frequency range.
Thus, 16 SERDES can reside on the same bus. By convention,
when all address pins are tied low, the device address is
referred to as 0x60.
SCL and SDA are open drain to allow multiple devices to share
the bus. If not used, SCL and SDA should be tied to VDD_IO.
Side Channel Interface
The higher value capacitor, in particular, needs to be chosen
carefully with special care regarding its ESR. Very good results
can be obtained with multilayer ceramic capacitors, available
from many suppliers, and generally in small outlines (such as
the 1210 outline suggested in the schematic shown in
Figure 4), which provide good bypass capabilities down to a
few m at 1MHz to 2MHz. Other capacitor technologies may
also be suitable (perhaps niobium oxide), but “classic”
electrolytic capacitors frequently have ESR values of above
1, that nullify any decoupling effect above the 1kHz to 10kHz
frequency range.
The Side Channel is a mechanism for transferring data
between the two chips on each end of the link. This data is
transferred during video blanking so none of the video
bandwidth is used. It has three basic uses:
• Data exchanges between two processors
• Master Mode I2C commands to remote slaves
• Remote SERDES configuration
This interface allows the user to initialize registers, control and
monitor both SERDES chips from a single micro-controller
which can reside on either side of the serial link. This feature is
used to automatically transport the remote side chip’s status
which is available in a local register. The Side Channel needs
to be enabled for this to work which is the default mode. In the
case where there is a micro-controller on each side of the of
the link data can be buffered and exchanged between the two.
Capacitors of 0.1µF offer low impedance in the 10MHz to
20MHz region, and 1000pF capacitors in the 100MHz to
200MHz region. In general, one of the lower value capacitors
should be used at each supply pin on the IC. Figure 4 shows
the grounding of the various capacitors to the pin
corresponding to the supply pin. Although all the ground
FN6827 Rev 1.00
Jun 19, 2008
Page 9 of 11
ISL34341
Up to 224 bytes can be sent in each direction during each
VSYNC active period.
components are needed other than the serial link. The I2C
commands and data are transferred during video blanking
causing no interruptions in the video data. Data is
transported by the Side Channel across the link so the
maximum throughput would be the same.
Master Mode
This is a mode activated by strapping the MASTER pin to a
‘1’ on the 34341 on the remote side of the controller. This is
a virtual extension of the I2C interface across the link that
allows the local processor to read and write slave devices
connected to the remote side I2C bus. No additional wires or
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure
you have the latest Rev.
DATE
REVISION
FN6827.1
FN6827.0
CHANGE
Changed Tja and Tjc in Thermal Information from 33 and 4.5 to 40 and 12.
Initial Release to web.
06/19/08
12/15/08
© Copyright Intersil Americas LLC 2008. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6827 Rev 1.00
Jun 19, 2008
Page 10 of 11
ISL34341
Thin Plastic Quad Flatpack Exposed Pad Plastic Packages (EPTQFP)
D
Q64.10x10C (JEDEC MS-026ACD-HU ISSUE D)
D1
-D-
64 LEAD THIN PLASTIC QUAD FLATPACK EXPOSED
PAD PACKAGE
MILLIMETERS
SYMBOL
MIN
-
MAX
1.20
NOTES
A
A1
A2
b
-
EJECTOR PIN MARK
NOT PIN #1 ID
0.05
0.95
0.16
0.17
11.80
9.90
2.90
11.80
9.90
2.90
0.45
0.15
-
-B-
-A-
1.05
-
0.28
6
b1
D
0.23
-
E1
E
12.20
10.10
3.10
3
D1
D2
E
4, 5
-
e
12.20
10.10
3.10
3
E1
E2
L
4, 5
-
0.75
-
N
64
7
PIN 1
e
0.50 BSC
-
TOP VIEW
Rev. 0 10/08
o
o
NOTES:
11 -13
0.020
0.008
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
MIN
o
0
MIN
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
A2
o
A1
GAGE
PLANE
o
o
0 -7
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
L
o
11 -13
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
0.25
0.010
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed
the maximum b dimension by more than 0.08mm (0.003
inch).
PIN 1
7. “N” is the number of terminal positions.
EJECTOR PIN MARK
NOT PIN #1 ID
SEATING
PLANE
A
-H-
0.08
0.003
E2
-C-
0.08
0.003
D
b
M
C
A-B S
S
EJECTOR PIN MARK
NOT PIN #1 ID
b1
0.09/0.16
0.004/0.006
BASE METAL
D2
WITH PLATING
0.09/0.20
0.004/0.008
BOTTOM VIEW
FN6827 Rev 1.00
Jun 19, 2008
Page 11 of 11
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