ISL43142IVZ [RENESAS]
Low-Voltage, Single and Dual Supply, High Performance, Quad SPST, Analog Switches; SOIC16, TSSOP16; Temp Range: -40° to 85°C;
| 型号： | ISL43142IVZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Low-Voltage, Single and Dual Supply, High Performance, Quad SPST, Analog Switches; SOIC16, TSSOP16; Temp Range: -40° to 85°C 光电二极管 |
| 文件： | 总17页 (文件大小：984K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL43140, ISL43141, ISL43142
Low-Voltage, Single and Dual Supply, High Performance, Quad SPST, Analog
Switches
FN6032
Rev 2.00
Aug 24, 2015
The Intersil ISL43140–ISL43142 devices are CMOS,
precision, quad analog switches designed to operate from a
Features
• Fully Specified at 5V, 12V, 5V, and 3V Supplies for 10%
Tolerances
single +2V to +12V supply or from a 2V to 6V supply.
Targeted applications include battery powered equipment that
benefit from the devices’ low power consumption (1W), low
leakage currents (1nA max), and fast switching speeds
• Four Separately Controlled SPST Switches
• Pin Compatible with DG411/DG412/DG413
(t
= 30ns, t
= 18ns). A 12 maximum R flatness
ON
OFF
ON
• ON Resistance (R ) . . . . . . . . . . . . . . . . . . . . . . . . 50
ensures signal fidelity, while channel-to-channel mismatch is
guaranteed to be less than 2.5. The 3mm x 3mm Quad No-
Lead Flatpack (QFN) package alleviates board space
limitations, making this newest line of low-voltage switches an
ideal solution.
ON
• R
Matching Between Channels. . . . . . . . . . . . . . . . . . . 2
• Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . 5pC (Max)
ON
• Low Power Consumption (P ). . . . . . . . . . . . . . . . . . . .<1W
D
The ISL43140/ISL43141/ISL43142 are quad single-pole/
single-throw (SPST) devices. The ISL43140 has four normally
closed (NC) switches; the ISL43141 has four normally open
(NO) switches; the ISL43142 has two NO and two NC
switches and can be used as a dual SPDT, or a dual 2:1
multiplexer.
• Low Leakage Current (Max at 85°C) . . . . . . . . . . . . . 5nA
• Fast Switching Action
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18ns
OFF
• Guaranteed Break-Before-Make (ISL43142 only)
• Minimum 2000V ESD Protection per Method 3015.7
• TTL, CMOS Compatible
Table 1 summarizes the performance of this family.
TABLE 1. FEATURES AT A GLANCE
• Pb-free Available
ISL43142
(No longer
available or
Applications
ISL43140
4
ISL43141
4
supported)
• Battery Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
Number of Switches
Configuration
4
- Pagers
All NC
50
All NO
50
2 NC / 2 NO
50
- Laptops, Notebooks, Palmtops
10.8V R
ON
• Communications Systems
- Military Radios
10.8V t
/ t
30ns / 18ns 30ns / 18ns 30ns / 18ns
50 50 50
40ns / 15ns 40ns / 15ns 40ns / 15ns
110 110 110
50ns / 20ns 50ns / 20ns 50ns / 20ns
200 200 200
ON OFF
4.5V R
ON
- RF “Tee” Switches
4.5V t
/ t
ON OFF
• Test Equipment
- Ultrasound
4.5V R
ON
- Electrocardiograph
4.5V t
2.7V t
/ t
ON OFF
• Heads-Up Displays
2.7V R
ON
/ t
120ns / 25ns 120ns / 25ns 120ns / 25ns
• Audio and Video Switching
ON OFF
16 Ld SOIC (N), 16 Ld 3x3 QFN,
16 Ld TSSOP
• General Purpose Circuits
Packages
- +3V/+5V DACs and ADCs
- Digital Filters
- Operational Amplifier Gain Switching Networks
- High Frequency Analog Switching
- High Speed Multiplexing
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
FN6032 Rev 2.00
Aug 24, 2015
Page 1 of 17
ISL43140, ISL43141, ISL43142
Pinouts (Note 1)
ISL43140 (SOIC, TSSOP)
TOP VIEW
ISL43140 (QFN)
TOP VIEW
IN1
COM1
NC1
V-
1
2
3
4
5
6
7
8
16 IN2
15 COM2
14 NC2
13 V+
16 15 14 13
NC1
V-
1
2
3
4
12 NC2
11 V+
GND
NC4
COM4
IN4
12 N.C.
11 NC3
10 COM3
GND
NC4
10 N.C.
9
NC3
5
6
7
8
9
IN3
ISL43141 (SOIC, TSSOP)
ISL43141 (QFN)
TOP VIEW
TOP VIEW
IN1
COM1
NO1
V-
1
2
3
4
5
6
7
8
16 IN2
15 COM2
14 NO2
13 V+
16 15 14 13
NO1
V-
1
12 NO2
11 V+
2
3
4
GND
NO4
COM4
IN4
12 N.C.
11 NO3
10 COM3
GND
NO4
10 N.C.
9
NO3
9
IN3
5
6
7
8
ISL43142 (SOIC, TSSOP)
ISL43142 (QFN)
TOP VIEW
TOP VIEW
IN1
COM1
NO1
V-
1
2
3
4
5
7
8
16 IN2
15 CM2
4 NC2
13 V+
16 15 14 13
NO1
V-
1
2
3
4
12 NC2
11 V+
GND
NO4
CM4
IN4
12 N.C.
11 NC3
10 COM3
GND
NO4
10 N.C.
9
NC3
9
IN3
5
6
7
8
NOTE:
1. Switches Shown for Logic “0” Input.
FN6032 Rev 2.00
Aug 24, 2015
Page 2 of 17
ISL43140, ISL43141, ISL43142
Truth Table
ISL43140
ISL43141
SW 1, 2, 3, 4
OFF
ISL43142
LOGIC
SW 1, 2, 3, 4
ON
SW 1, 4
OFF
SW 2, 3
ON
0
1
OFF
ON
ON
OFF
NOTE: Logic “0” 0.8V. Logic “1” 2.4V.
Pin Descriptions
PIN
FUNCTION
Positive Power Supply Input
V+
V-
Negative Power Supply Input. Connect to GND for Single Supply Configurations.
Ground Connection
GND
IN
Digital Control Input
COM
NO
NC
Analog Switch Common Pin
Analog Switch Normally Open Pin
Analog Switch Normally Closed Pin
No Internal Connection
N.C.
Ordering Information
PART NUMBER
(BRAND)
TEMP.
PACKAGE
PKG.
(NOTES 2, 3)
RANGE (°C)
RoHS Compliant
16 Ld SOIC (N)
16 Ld QFN
DWG. #
ISL43140IBZ
-40 to 85
-40 to 85
M16.15
L16.3x3
ISL43140IRZ
(140I)
ISL43140IVZ
ISL43141IBZ
-40 to 85
-40 to 85
-40 to 85
16 Ld TSSOP
16 Ld SOIC (N)
16 Ld QFN
M16.173
M16.15
L16.3x3
ISL43141IRZ
(141I)
ISL43141IVZ
-40 to 85
-40 to 85
-40 to 85
16 Ld TSSOP
16 Ld SOIC (N)
16 Ld TSSOP
M16.173
M16.15
ISL43142IBZ (No longer available, recommended replacement: ISL43120IHZ-T)
ISL43142IVZ (No longer available, recommended replacement: ISL43120IHZ-T)
M16.173
NOTES:
2. Most surface mount devices are available on tape and reel; add “-T” to suffix.
3. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
FN6032 Rev 2.00
Aug 24, 2015
Page 3 of 17
ISL43140, ISL43141, ISL43142
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V
V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V
All Other Pins (Note 4). . . . . . . . . . . . . ((V-) - 0.3V) to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 10mA
Peak Current, IN, NO, NC, or COM
Thermal Resistance (Typical, Note 5)
(°C/W)
JA
16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
16 Ld QFN Package. . . . . . . . . . . . . . . . . . . . . . . . .
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Moisture Sensitivity (See Technical Brief TB363)
All Other Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2
Maximum Storage Temperature Range. . . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC and TSSOP - Lead Tips Only)
115
75
150
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 20mA
ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>2kV
Operating Conditions
Temperature Range
ISL4314XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
4. Signals on NC, NO, COM, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings.
5. is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications: ±5V Supply Test Conditions V
= 4.5V to 5.5V, GND = 0V, V
INH
Unless Otherwise Specified
= 2.4V, V
= 0.8V (Note 6),
INL
SUPPLY
TEMP (NOTE 7)
(NOTE 7)
PARAMETER
TEST CONDITIONS
(°C)
MIN
TYP
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
Full
25
V-
-
-
V+
65
75
2.5
5
V
ANALOG
ON Resistance, R
V
= 4.5V, I
= 1.0mA, V
= 1.0mA, V
or V
or V
= 3V,
50
ON
S
COM
COM
COM
NO
NO
NO
NC
NC
NC
See Figure 5
Full
25
-
-
R
Matching Between Channels,
V
V
V
= 4.5V, I
= 3V
-
2
ON
R
S
S
S
ON
Full
25
-
-
R
Flatness, R
= 4.5V, I
= 1.0mA, V
or V
= 3V, Note 9
= +4.5V,
= +4.5V,
-
10
12
13
1
ON
FLAT(ON)
Full
25
-
-
NO or NC OFF Leakage Current,
or I
= 5.5V, V
= 4.5V, V
= 4.5V, V
or V
-1
-5
-1
-5
-2
-10
0.01
nA
nA
nA
nA
nA
nA
COM
COM
COM
NO
NC
NC
I
Note 8
NO(OFF)
NC(OFF)
Full
25
-
0.01
-
5
COM OFF Leakage Current,
V
= 5.5V, V
or V
1
S
NO
I
Note 8
COM(OFF)
Full
25
5
COM ON Leakage Current,
V
= 5.5V, V
= V
or V = 4.5V, Note 8
NC
0.01
-
2
S
NO
I
COM(ON)
Full
10
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Full
Full
Full
2.4
-
1.6
1.6
-
V
V
INH
Input Voltage Low, V
Input Current, I , I
0.8
0.5
INL
V
= 5.5V, V = 0V or V+
IN
-0.5
0.03
A
INH INL
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
S
V
V
= 4.5V, V
or V
= 3V, R = 300, C = 35pF,
25
Full
25
-
-
40
-
80
100
30
40
-
ns
ns
ns
ns
ns
ON
S
NO
NC
L
L
= 0 to 3V, See Figure 1
IN
Turn-OFF Time, t
V
V
= 4.5V, V
or V
= 3V, R = 300, C = 35pF,
-
15
-
OFF
S
NO
NC
L
L
= 0 to 3V, See Figure 1
IN
Full
Full
-
Break-Before-Make Time Delay
(ISL43142), t
V
V
= 5.5V, V
or V
= 3V, R = 300, C = 35pF,
5
20
S
NO
NC
L
L
= 0 to 3V, See Figure 3
D
IN
Charge Injection, Q
C
= 1.0nF, V = 0V, R = 0, See Figure 2
25
25
25
-
-
-
1
7
7
5
-
pC
pF
pF
L
G
G
NO or NC OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= 0V, See Figure 7
= 0V, See Figure 7
OFF
NO
NC
COM
COM
COM OFF Capacitance,
= V
-
NO
NC
C
COM(OFF)
COM ON Capacitance, C
f = 1MHz, V
or V
= V
= 0V, See Figure 7
25
-
14
-
pF
COM(ON)
NO
NC
COM
FN6032 Rev 2.00
Aug 24, 2015
Page 4 of 17
ISL43140, ISL43141, ISL43142
Electrical Specifications: ±5V Supply Test Conditions V
= 4.5V to 5.5V, GND = 0V, V
Unless Otherwise Specified (Continued)
= 2.4V, V
= 0.8V (Note 6),
INL
SUPPLY
INH
TEMP (NOTE 7)
(NOTE 7)
PARAMETER
OFF Isolation
TEST CONDITIONS
(°C)
MIN
TYP
>90
<-90
-60
MAX
UNITS
dB
R
= 50, C = 15pF, f = 100kHz,
25
-
-
-
-
-
-
L
L
V
or V
= 1V
, See Figures 4, 6, and 19
NO
NC
RMS
Crosstalk, Note 10
All Hostile Crosstalk
25
dB
R
= 50, C = 15pF, f = 10MHz,
25
dB
L
L
V
or V
= 1V
, See Figure 19
NO
NC
RMS
Power Supply Rejection Ratio
R
= 50, C = 15pF, f = 1MHz, See Figure 20
25
-
60
-
dB
L
L
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
25
2
-1
-1
-1
-1
-
0.05
-
6
1
V
Positive Supply Current, I+
Negative Supply Current, I-
NOTES:
V
= 5.5V, V = 0V or V+, Switch On or Off
IN
A
A
A
A
S
Full
25
1
0.05
-
1
Full
1
6. V = Input voltage to perform proper function.
IN
7. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
8. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25°C.
9. Flatness is defined as the delta between the maximum and minimum R
10. Between any two switches.
values over the specified voltage range.
ON
Electrical Specifications: 12V Supply Test Conditions: V+ = +10.8V to +13.2V, V- = GND = 0V, V
= 5V, V
= 0.8V (Note 6),
(NOTE7)
INH
INL
Unless Otherwise Specified
TEMP (NOTE 7)
PARAMETER
TEST CONDITIONS
(°C)
MIN
TYP
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
Full
25
0
-
-
50
60
2
-
V+
65
75
2.5
5
V
ANALOG
ON Resistance, R
V+ = 10.8V, I
See Figure 5
= 1.0mA, V
= 1.0mA, V
or V
or V
= 9V,
ON
COM
COM
COM
NO
NO
NO
NC
NC
NC
Full
25
-
R
Matching Between Channels, V+ = 10.8V, I
= 9V
-
ON
R
ON
Full
25
-
R
Flatness, R
V+ = 10.8V, I
Note 9
= 1.0mA, V
or V
= 3V, 6V, 9V,
-
8
9
-
12
13
1
ON
FLAT(ON)
Full
25
-
NO or NC OFF Leakage Current,
or I
V+ = 13.2V, V
Note 8
= 1V, 10V, V
= 10V, 1V, V
or V
= 10V, 1V,
= 1V, 10V,
-1
-5
-1
-5
-2
-10
nA
nA
nA
nA
nA
nA
COM
COM
COM
NO
NC
I
NO(OFF)
NC(OFF)
Full
25
-
5
COM OFF Leakage Current,
V+ = 13.2V, V
Note 8
or V
-
1
NO
NC
I
COM(OFF)
Full
25
-
5
COM ON Leakage Current,
V = 13.2V, V
10V, Note 8
= 1V, 10V, or V
or V
= 1V,
NC
-
2
NO
I
COM(ON)
Full
-
10
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Full
Full
Full
3.5
-
3.1
-
0.8
1
V
V
INH
Input Voltage Low, V
Input Current, I , I
-
-
INL
V+ = 13.2V, V = 0V or V+
IN
-1
A
INH INL
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 10.8V, V
or V = 10V, R = 300, C = 35pF,
NC
25
Full
25
-
-
30
34
18
20
8
70
100
50
75
-
ns
ns
ns
ns
ns
ON
NO
= 0 to 3.3V, See Figure 1
L
L
V
IN
Turn-OFF Time, t
V+ = 10.8V, V
or V = 10V, R = 300, C = 35pF,
NC
-
OFF
NO
= 0 to 3.3V, See Figure 1
L
L
V
IN
Full
Full
-
Break-Before-Make Time Delay
(ISL43142), t
V+ = 13.2V, V
V
or V
= 10V, R = 300, C = 35pF,
0
NO
= 0 to 3.3V, See Figure 3
IN
NC
L
L
D
FN6032 Rev 2.00
Aug 24, 2015
Page 5 of 17
ISL43140, ISL43141, ISL43142
Electrical Specifications: 12V Supply Test Conditions: V+ = +10.8V to +13.2V, V- = GND = 0V, V
Unless Otherwise Specified (Continued)
= 5V, V
= 0.8V (Note 6),
(NOTE7)
INH
INL
TEMP (NOTE 7)
PARAMETER
Charge Injection, Q
TEST CONDITIONS
= 1.0nF, V = 0V, R = 0See Figure 2
(°C)
MIN
TYP
5
MAX
UNITS
C
R
V
25
-
-
-
-
15
-
pC
L
G
G
OFF Isolation
= 50, C = 15pF, f = 100kHz,
25
>90
<-90
-60
dB
L
L
or V
= 1V
, See Figures 4, 6, and 19
NO
NC
RMS
Crosstalk, Note 10
All Hostile Crosstalk
25
-
dB
R
= 50, C = 15pF, f = 10MHz,
25
-
dB
L
L
V
or V
= 1V
, See Figure 19
NO
NC
RMS
Power Supply Rejection Ratio
NO or NC OFF Capacitance, C
COM OFF Capacitance,
R
= 50, C = 15pF, f = 1MHz, See Figure 20
25
25
25
-
-
-
60
7
-
-
-
dB
pF
pF
L
L
f = 1MHz, V
f = 1MHz, V
or V
= V
= V
= 0V, See Figure 7
= 0V, See Figure 7
OFF
NO
NO
NC
NC
COM
COM
or V
7
C
COM(OFF)
COM ON Capacitance, C
f = 1MHz, V
or V
= V
= 0V, See Figure 7
25
-
14
-
pF
COM(ON)
NO
NC
COM
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
Negative Supply Current, I-
V+ = 13.2V, V = 0V or V+, Switch On or Off
IN
25
Full
25
-1
-1
-1
-1
0.05
1
1
1
1
A
A
A
A
-
0.05
-
Full
Electrical Specifications: 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, V
Unless Otherwise Specified
= 2.4V, V
= 0.8V (Note 6),
INL
INH
TEMP
(°C)
MIN
(NOTE 7)
MAX
(NOTE 7) UNITS
PARAMETER
TEST CONDITIONS
TYP
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
Full
25
0
-
-
V+
120
150
2
V
ANALOG
ON Resistance, R
V+ = 4.5V, I
= 1.0mA, V
or V
= 3.5V,
= 3.5V
110
ON
COM
See Figure 5
NO
NO
NO
NC
Full
25
-
-
R
Matching Between Channels, V+ = 4.5V, I
= 1.0mA, V
= 1.0mA, V
or V
-
1.5
ON
R
COM
NC
ON
Full
25
-
-
5
R
Flatness, R
V+ = 4.5V, I
Note 9
or V
NC
= 1.5V to 4.5V,
-
12
16
20
1
ON
FLAT(ON)
COM
Full
25
-
-
NO or NC OFF Leakage Current,
or I
V+ = 5.5V, V
Note 8
= 1V, 4.5V, V
= 1V, 4.5V, V
or V
or V
= 4.5V, 1V,
= 4.5V, 1V,
-1
-5
-1
-5
-2
-10
0.01
nA
nA
nA
nA
nA
nA
COM
COM
COM
NO
NO
NC
I
NO(OFF)
NC(OFF)
Full
25
-
5
COM OFF Leakage Current,
V+ = 5.5V, V
Note 8
0.01
1
NC
I
COM(OFF)
Full
25
-
-
-
5
COM ON Leakage Current,
V+ = 5.5V, V
= 1V, 4.5V, Note 8
2
I
COM(ON)
Full
10
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Full
Full
Full
2.4
-
1.6
1.6
-
V
V
INH
Input Voltage Low, V
Input Current, I , I
0.8
0.5
INL
V+ = 5.5V, V = 0V or V+
IN
-0.5
0.03
A
INH INL
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 4.5V, V
or V
= 3V, R = 300, C = 35pF,
25
Full
25
-
-
50
-
100
150
50
75
-
ns
ns
ns
ns
ns
ON
NO
NC
L
L
V
= 0 to 3V, See Figure 1
IN
Turn-OFF Time, t
V+ = 4.5V, V
or V
= 3V, R = 300, C = 35pF,
-
20
-
OFF
NO
NC
L
L
V
= 0 to 3V, See Figure 1
IN
Full
Full
-
Break-Before-Make Time Delay
(ISL43142), t
V+ = 5.5V, V
or V
= 3V, R = 300, C = 35pF,
10
30
NO
= 0 to 3V, See Figure 3
IN
NC
L
L
V
C
R
D
Charge Injection, Q
OFF Isolation
= 1.0nF, V = 0V, R = 0See Figure 2
25
25
25
-
-
-
1
5
-
pC
dB
dB
L
G
G
= 50, C = 15pF, f = 100kHz,
>90
<-90
L
L
V
or V
= 1V
, See Figures 4, 6, and 19
NO
NC
RMS
Crosstalk, Note 10
-
FN6032 Rev 2.00
Aug 24, 2015
Page 6 of 17
ISL43140, ISL43141, ISL43142
Electrical Specifications: 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, V
Unless Otherwise Specified (Continued)
= 2.4V, V
= 0.8V (Note 6),
INL
INH
TEMP
(°C)
MIN
(NOTE 7)
MAX
(NOTE 7) UNITS
PARAMETER
TEST CONDITIONS
= 50, C = 15pF, f = 10MHz,
TYP
All Hostile Crosstalk
R
25
-
-60
-
dB
L
L
V
or V
= 1V
, See Figure 19
NO
NC
RMS
Power Supply Rejection Ratio
NO or NC OFF Capacitance, C
COM OFF Capacitance,
R
= 50, C = 15pF, f = 1MHz, See Figure 20
25
25
25
-
-
-
60
7
-
-
-
dB
pF
pF
L
L
f = 1MHz, V
f = 1MHz, V
or V
= V
= V
= 0V, See Figure 7
= 0V, See Figure 7
OFF
NO
NO
NC
NC
COM
COM
or V
7
C
COM(OFF)
COM ON Capacitance, C
f = 1MHz, V
or V
= V
= 0V, See Figure 7
25
-
14
-
pF
COM(ON)
NO
NC
COM
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
Negative Supply Current, I-
V+ = 5.5V, V = 0V or V+, Switch On or Off
IN
25
Full
25
-1
-1
-1
-1
0.05
1
1
1
1
A
A
A
A
-
0.05
-
Full
Electrical Specifications: 3V to 3.3V Supply
Test Conditions: V+ = +2.7V to +3.6V, V- = GND = 0V, V
(Note 6), Unless Otherwise Specified
= 2.4V, V
= 0.8V
INL
INH
TEMP
(°C)
MIN
(NOTE 7)
MAX
(NOTE 7) UNITS
PARAMETER
TEST CONDITIONS
TYP
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
Full
25
0
-
-
V+
250
270
4
V
ANALOG
ON Resistance, R
V+ = 2.7V, I
= 1.0mA, V
or V
= 1V,
= 1V
200
ON
COM
See Figure 5
NO
NO
NO
NC
Full
25
-
-
R
Matching Between Channels, V+ = 2.7V, I
= 1.0mA, V
= 1.0mA, V
or V
-
2
ON
R
COM
NC
ON
Full
25
-
-
6
R
Flatness, R
V+ = 2.7V, I
Note 9
or V
NC
= 0.5V to 1.5V,
-
80
100
120
1
ON
FLAT(ON)
COM
Full
25
-
-
NO or NC OFF Leakage Current,
or I
V+ = 3.6V, V
Note 8
= 1V, 2.6V, V
or V
or V
= 2.6V, 1V,
= 2.6V, 1V,
-1
-5
-1
-5
-2
-10
0.01
nA
nA
nA
nA
nA
nA
COM
COM
COM
NO
NO
NC
I
NO(OFF)
NC(OFF)
Full
25
-
5
COM OFF Leakage Current,
V+ = 3.6V, V
Note 8
= 1V, 2.6V, V
0.01
1
NC
I
COM(OFF)
Full
25
-
-
-
5
COM ON Leakage Current,
V+ = 3.6V, V
= 1V, 2.6V, Note 8
2
I
COM(ON)
Full
10
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Full
Full
Full
2.4
-
1.6
1.6
-
V
V
INH
Input Voltage Low, V
Input Current, I , I
0.8
0.5
INL
V+ = 3.6V, V = 0V or V+
IN
-0.5
0.03
A
INH INL
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 2.7V, V
or V
= 1.5V, R = 300, C = 35pF,
25
Full
25
-
-
120
-
180
220
45
60
-
ns
ns
ns
ns
ns
ON
NO
NC
L
L
V
= 0 to V+, See Figure 1
IN
Turn-OFF Time, t
V+ = 2.7V, V
or V
= 1.5V, R = 300, C = 35pF,
-
25
-
OFF
NO
NC
L
L
V
= 0 to V+, See Figure 1
IN
Full
25
-
Break-Before-Make Time Delay
(ISL43142), t
V+ = 3.6V, V
or V
= 1.5V, R = 300, C = 35pF,
15
50
NO
= 0 to 3V, See Figure 3
IN
NC
L
L
V
C
R
D
Charge Injection, Q
OFF Isolation
= 1.0nF, V = 0V, R = 0See Figure 2
25
25
25
25
-
-
-
-
0.5
>90
<-90
-60
5
-
pC
dB
dB
dB
L
G
G
= 50, C = 15pF, f = 100kHz,
L
L
V
or V
= 1V
, See Figures 4, 6, and 19
NO
NC
RMS
Crosstalk, Note 10
All Hostile Crosstalk
-
R
= 50, C = 15pF, f = 10MHz,
-
L
L
V
or V
= 1V
, See Figure 19
NO
NC
RMS
Power Supply Rejection Ratio
R
= 50, C = 15pF, f = 1MHz, See Figure 20
25
-
60
-
dB
L
L
FN6032 Rev 2.00
Aug 24, 2015
Page 7 of 17
ISL43140, ISL43141, ISL43142
Electrical Specifications: 3V to 3.3V Supply
Test Conditions: V+ = +2.7V to +3.6V, V- = GND = 0V, V
(Note 6), Unless Otherwise Specified (Continued)
= 2.4V, V
= 0.8V
INL
INH
TEMP
(°C)
MIN
(NOTE 7)
MAX
(NOTE 7) UNITS
PARAMETER
NO or NC OFF Capacitance, C
COM OFF Capacitance,
TEST CONDITIONS
TYP
7
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= V
= 0V, See Figure 7
= 0V, See Figure 7
25
25
-
-
-
-
pF
pF
OFF
NO
NO
NC
COM
COM
7
NC
C
COM(OFF)
COM ON Capacitance, C
f = 1MHz, V
or V
= V
= 0V, See Figure 7
25
-
14
-
pF
COM(ON)
NO
NC
COM
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
Negative Supply Current, I-
V+ = 3.6V, V = 0V or V+, Switch On or Off
IN
25
Full
25
-1
-1
-1
-1
0.05
1
1
1
1
A
A
A
A
-
0.05
-
Full
Test Circuits and Waveforms
V+
3V
t < 20ns
r
t < 20ns
f
C
LOGIC
INPUT
50%
SWITCH
INPUT
0V
NX
C
t
OFF
V
OUT
NO or NC
IN
SWITCH
INPUT
V
V
NX
COM
V
OUT
90%
90%
C
35pF
R
300
L
L
GND
SWITCH
OUTPUT
0V
LOGIC
INPUT
t
ON
C
V-
Repeat test for all switches. C includes fixture and stray
L
Logic input waveform is inverted for switches that have the opposite
logic sense.
capacitance.
R
L
------------------------------
V
= V
OUT
(NO or NC)
R
+ R
ON
L
FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
V+
C
SWITCH
OUTPUT
V
OUT
V
R
OUT
G
COM
NO or NC
V
OUT
3V
0V
ON
ON
LOGIC
INPUT
V
GND
OFF
G
IN
C
L
LOGIC
INPUT
C
Q = V
x C
L
OUT
V-
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. C includes fixture and stray
L
capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
FN6032 Rev 2.00
Aug 24, 2015
Page 8 of 17
ISL43140, ISL43141, ISL43142
Test Circuits and Waveforms (Continued)
V+
C
C
3V
LOGIC
INPUT
V
OUT1
NO1
NC2
IN1
V
NX
COM1
COM2
0V
C
V
R
L1
L1
35pF
OUT2
300
90%
90%
SWITCH
OUTPUT
R
C
L2
300
L2
V
35pF
0V
0V
OUT1
IN2
LOGIC
INPUT
GND
90%
90%
SWITCH
OUTPUT
V
OUT2
C
t
t
D
D
V-
C
includes fixture and stray capacitance.
L
Reconfigure accordingly to test SW3 and SW4.
FIGURE 3B. TEST CIRCUIT
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE TIME (ISL43142 ONLY)
V+
C
V+
C
R
= V /1mA
1
SIGNAL
GENERATOR
ON
NO or NC
NO or NC
V
NX
0V or 2.4V
IN
1mA
0.8V or 2.4V
IN
V
1
COM
COM
ANALYZER
GND
GND
R
L
C
C
V-
V-
Repeat test for all switches.
Repeat test for all switches.
FIGURE 5. R
FIGURE 4. OFF ISOLATION TEST CIRCUIT
TEST CIRCUIT
ON
V+
C
V+
SIGNAL
GENERATOR
50
NO1 or NC1
IN1
COM1
NO or NC
0V or 2.4V
IN
0V or 2.4V
0V or 2.4V
IMPEDANCE
ANALYZER
IN2
NO
COM
CONNECTION
NO2 or NC2
COM2
ANALYZER
GND
GND
R
L
C
V-
V-
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
FN6032 Rev 2.00
Aug 24, 2015
Page 9 of 17
ISL43140, ISL43141, ISL43142
Power-Supply Considerations
Detailed Description
The ISL4314X construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and GND.
V+ and V- drive the internal CMOS switches and set their
analog voltage limits, so there are no connections between the
analog signal path and GND. Unlike switches with a 13V
maximum supply voltage, the ISL4314X 15V maximum supply
voltage provides plenty of room for the 10% tolerance of 12V
supplies (6V or 12V single supply), as well as room for
overshoot and noise spikes.
The ISL43140–ISL43142 quad analog switches offer precise
switching capability from a bipolar 2V to 6V or a single 2V to
12V supply with low on-resistance (50) and high speed
switching (t
= 40ns, t = 15ns). The devices are
ON
OFF
especially well suited to portable battery powered equipment
thanks to the low operating supply voltage (2V), low power
consumption (1W), low leakage currents (1nA max), and the
tiny QFN packaging. High frequency applications also benefit
from the wide bandwidth, and the very high off isolation and
crosstalk rejection.
This family of switches performs equally well when operated
with bipolar or single voltage supplies. The addition of the GND
pin allows for asymmetrical bipolar supplies (e.g. +5V and -
3V). The minimum recommended supply voltage is 2V or 2V.
It is important to note that the input signal range, switching
times, and on-resistance degrade at lower supply voltages.
Refer to the electrical specification tables and Typical
Performance Curves for details.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to V- (see Figure
8). To prevent forward biasing these diodes, V+ and V- must
be applied before any input signals, and input signal voltages
must remain between V+ and V-. If these conditions cannot be
guaranteed, then one of the following two protection methods
should be employed.
V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals, so switch parameters - especially
Logic inputs can easily be protected by adding a 1k resistor
in series with the input (see Figure 8). The resistor limits the
input current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
R
- are strongly influenced by V-.
ON
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no
affect on logic thresholds. This switch family is TTL compatible
(0.8V and 2.4V) over a V+ supply range of 2.5V to 10V (see
Adding a series resistor to the switch input defeats the purpose
Figure 17). At 12V the V level is about 2.7V, so for best
of using a low R
switch, so two small signal diodes can be
IH
ON
results use a logic family the provides a V
greater than 3V.
added in series with the supply pins to provide overvoltage
protection for all pins (see Figure 8). These additional diodes
limit the analog signal from 1V below V+ to 1V above V-. The
low leakage current performance is unaffected by this
approach, but the switch resistance may increase, especially
at low supply voltages.
OH
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving the
digital input signals from GND to V+ with a fast transition time
minimizes power dissipation.
High-Frequency Performance
In 5systems, signal response is reasonably flat even past
100MHz (see Figure 18). Figure 18 also illustrates that the
frequency response is very consistent over a wide V+ range,
and for varying analog signal levels.
OPTIONAL PROTECTION
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
An off switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
IN
V
X
feedthrough from a switch’s input to its output. Off Isolation is
the resistance to this feedthrough, while Crosstalk indicates
the amount of feedthrough from one switch to another. Figure
19 details the high Off Isolation and Crosstalk rejection
provided by this family. At 10MHz, off isolation is about 50dB in
5systems, decreasing approximately 20dB per decade as
frequency increases. Higher load impedances decrease Off
Isolation and Crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load impedance.
V
NO or NC
COM
V-
OPTIONAL PROTECTION
DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
Leakage Considerations
FN6032 Rev 2.00
Aug 24, 2015
Page 10 of 17
ISL43140, ISL43141, ISL43142
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One of
these diodes conducts if any analog signal exceeds V+ or V-.
the signal varies. The difference in the two diode leakages to
the V+ and V- pins constitutes the analog-signal-path leakage
current. All analog leakage current flows between each pin and
one of the supply terminals, not to the other switch terminal.
This is why both sides of a given switch can show leakage
currents of the same or opposite polarity. There is no
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given signal
pin are identical and therefore fairly well balanced, they are
reverse biased differently. Each is biased by either V+ or V-
and the analog signal. This means their leakages will vary as
connection between the analog signal paths and GND.
Typical Performance Curves T = 25°C, Unless Otherwise Specified
A
100
90
250
200
150
100
V- = -5V
V
= (V+) - 1V
V+ = 3V
V- = 0V
COM
= 1mA
I
= 1mA
COM
85°C
25°C
-40°C
80
85°C
I
COM
70
60
25°C
50
-40°C
40
120
50
135
V- = -3V
85°C
100
80
V+ = 5V
85°C
25°C
-40°C
115
95
V- = 0V
60
25°C
-40°C
75
40
300
250
200
150
100
50
55
80
70
60
50
40
30
20
V- = 0V
85°C
V+ = 12V
V- = 0V
85°C
25°C
25°C
4
-40°C
3
-40°C
1
0
2
4
5
6
7
8
9
10
11
12
13
0
2
3
5
6
7
8
9
10 11 12
V+ (V)
V
(V)
COM
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
5
FIGURE 9. ON RESISTANCE vs POSITIVE SUPPLY VOLTAGE
180
V
V
=2V
I
= 1mA
S
COM
140
100
85°C
25°C
2.5
-40°C
V+ = 12V
V+ = 3V
V+ = 5V
60
120
0
=3V
S
100
80
85°C
-2.5
25°C
-40°C
V
=5V
S
60
-5
40
90
V
=5V
85°C
25°C
S
-7.5
70
50
30
-40°C
-10
-5
-2.5
0
2.5
5
7.5
10
12.5
-5
-4
-3
-2
-1
0
1
2
3
4
5
V
(V)
COM
V
(V)
COM
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
FN6032 Rev 2.00
Aug 24, 2015
Page 11 of 17
ISL43140, ISL43141, ISL43142
Typical Performance Curves T = 25°C, Unless Otherwise Specified (Continued)
A
50
40
30
20
10
300
250
200
150
100
50
V
= (V+) - 1V
V- = 0V
V
= (V+) - 1V
V- = 0V
COM
COM
85°C
85°C
25°C
25°C
-40°C
-40°C
0
2
3
4
5
6
7
8
9
10
11
12
2
3
4
5
6
7
8
9
10
11
12
V+ (V)
V+ (V)
FIGURE 13. TURN - ON TIME vs POSITIVE SUPPLY VOLTAGE
250
FIGURE 14. TURN - OFF TIME vs POSITIVE SUPPLY VOLTAGE
125
V
= (V+) - 1V
V
= (V+) - 1V
COM
V- = -5V
-40°C
V- = -5V
COM
25°C
200
150
100
50
100
75
85°C
-40°C
50
25°C
25°C
85°C
85°C
25
-40°C
-40°C
0
0
250
300
V- = -3V
V- = -3V
250
200
150
100
50
200
150
100
50
-40°C
-40°C
25°C
25°C
3
85°C
85°C
-40°C
3
0
0
2
4
5
6
7
8
9
10
11
12
2
4
5
6
7
8
9
10
11
12
V+ (V)
V+ (V)
FIGURE 15. TURN - ON TIME vs POSITIVE SUPPLY VOLTAGE
FIGURE 16. TURN - OFF TIME vs POSITIVE SUPPLY VOLTAGE
3.5
V- = 0V to -5V
V+ = 2.7V (V = 2V
IN P-P
)
3
0
V
= 2V (V = 3V ) or V+ = 5V (V = 4V
IN P-P IN
)
3
S
P-P
-40°C
25°C
2.5
GAIN
V
= 5V (V = 5V
IN
)
S
P-P
-3
85°C
V
INH
V+ = 2.7V (V = 2V
IN
)
P-P
2
1.5
1
0
PHASE
-40°C
45
V
= 2V (V = 3V
)
P-P
)
S
IN
25°C
V+ = 5V (V = 4V
IN
P-P
V
INL
90
V
= 5V (V = 5V )
IN P-P
S
135
180
85°C
R
= 50
0.5
L
2
3
4
5
6
7
8
9
10
11
12
1
10
100
FREQUENCY (MHz)
600
V+ (V)
FIGURE 17. DIGITAL SWITCHING POINT vs
POSITIVE SUPPLY VOLTAGE
FIGURE 18. FREQUENCY RESPONSE
FN6032 Rev 2.00
Aug 24, 2015
Page 12 of 17
ISL43140, ISL43141, ISL43142
Typical Performance Curves T = 25°C, Unless Otherwise Specified (Continued)
A
V+ = 3V to 12V or
-10
-20
-30
-40
-50
-60
-70
-80
-90
10
20
30
40
50
60
70
80
90
V+ = 3V to 12V or
V
R
= 2V to 5V
= 50
0
10
20
30
40
50
60
70
80
S
L
V
= 2V to 5V
= 50
S
L
R
V
= 1V
P-P
IN
-PSRR, SWITCH ON
ISOLATION
CROSSTALK
-PSRR, SWITCH OFF
+PSRR, SWITCH OFF
ALL HOSTILE CROSSTALK
-100
-110
100
110
+PSRR, SWITCH ON
0.3
1
10
FREQUENCY (MHz)
100
1000
1k
10k
100k
1M
10M
100M 500M
FREQUENCY (Hz)
FIGURE 19. CROSSTALK AND OFF ISOLATION
FIGURE 20. PSRR vs FREQUENCY
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
V-
TRANSISTOR COUNT:
ISL43140: 188
ISL43141: 188
ISL43142: 188
PROCESS:
Si Gate CMOS
FN6032 Rev 2.00
Aug 24, 2015
Page 13 of 17
ISL43140, ISL43141, ISL43142
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
CHANGE
August 24, 2015
FN6032.2
Updated Ordering Information table on page 3.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing (POD) M16.173 to the latest revision.
-Revision 1 to Revision 2 changes - Converted to new POD format by moving dimensions from table onto
drawing and adding land pattern. No dimension changes.
Updated POD L16.3X3 to the latest revision.
-Revision 1 to Revision 2 changes - Converted to new QFN template.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2002-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6032 Rev 2.00
Aug 24, 2015
Page 14 of 17
ISL43140, ISL43141, ISL43142
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
N
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
0.0688
0.0098
0.020
MIN
1.35
0.10
0.33
0.19
9.80
3.80
MAX
1.75
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
-
1
2
3
0.25
-
L
0.51
9
SEATING PLANE
A
0.0075
0.3859
0.1497
0.0098
0.3937
0.1574
0.25
-
-A-
10.00
4.00
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
16
16
7
0°
8°
0°
8°
-
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN6032 Rev 2.00
Aug 24, 2015
Page 15 of 17
ISL43140, ISL43141, ISL43142
Package Outline Drawing
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
5.00 ±0.10
SEE DETAIL "X"
9
16
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
8
B
0.09-0.20
0.65
TOP VIEW
END VIEW
1.00 REF
-
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25 +0.05/-0.06
0.25
5
0.10
C B A
M
0.10 C
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
(5.65)
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
(0.65 TYP)
(0.35 TYP)
6. Dimension in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
7. Conforms to JEDEC MO-153.
FN6032 Rev 2.00
Aug 24, 2015
Page 16 of 17
ISL43140, ISL43141, ISL43142
Package Outline Drawing
L16.3x3
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 4/07
4X
1.5
3.00
0.50
12X
A
6
B
PIN #1 INDEX AREA
16
13
6
PIN 1
INDEX AREA
1
12
1 .50 ± 0 . 15
9
4
(4X)
0.15
5
8
0.10 M C A B
+ 0.07
4
TOP VIEW
16X 0.23
- 0.05
16X 0.40 ± 0.10
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
C
0 . 90 ± 0.1
BASE PLANE
( 2. 80 TYP )
(
SEATING PLANE
0.08 C
SIDE VIEW
1. 50 )
( 12X 0 . 5 )
( 16X 0 . 23 )
( 16X 0 . 60)
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6032 Rev 2.00
Aug 24, 2015
Page 17 of 17
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