ISL54302IRZ [RENESAS]
12V, 1.5? Quad SPST Switch with Latched Parallel Interface; QFN20; Temp Range: -40° to 85°C;
| 型号： | ISL54302IRZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 12V, 1.5? Quad SPST Switch with Latched Parallel Interface; QFN20; Temp Range: -40° to 85°C 输出元件 |
| 文件： | 总16页 (文件大小：800K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL54302
FN6592
Rev 0.00
Mar 19, 2008
Data
12V, 1.5W Quad SPST Switch with llel Interface
The ISL54302 is a quad analog bidirectional switch device
Features
targeted at industrial applications, including test and
measurement equipment. It features low resistance and low
leakage along with 12V operation and can be digitally
controlled via a latched parallel interface. This parallel
interface features a latch input pin that can be used to connect
multiple devices into a parallel arrangement.
• 4 independently controlled SPST switches
• ON-resistance @ 12V. . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5
• Single or split supply voltage operation
• r
• r
flatness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <1
matching between channels . . . . . . . . . . . . . . . . . <0.2
ON
The ISL54302 can operate from a single, or split bipolar
power supply and has a 3V logic interface. The ISL54302 is
specified for use over the -40°C to +85°C temperature range
and is available in a 20 Ld 4x4 QFN Pb-free package.
ON
• Turn-on/Turn-off time . . . . . . . . . . . . . . . . . . . . . . . 25ns/80ns
• Switch bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60MHz
• Parallel data interface up to 40MHz
• 3V logic interface
Table 1 summarizes the performance of this family.
TABLE 1. FEATURES AT A GLANCE
• 20 Ld QFN package
CONFIGURATION
QUAD SPST
1.5
• Pb-free (RoHS compliant)
r
ON
t
/t
25ns/80ns
20 Ld QFN 4x4
ON OFF
Related Literature
• TB363 “Guidelines for Handling and Processing Moisture
Sensitive Surface Mount Devices (SMDs)”
Package
Pinout
• TB389 “PCB Land Pattern and Surface Mount Guidelines
for QFN Packages”
ISL54302
(20 LD QFN)
TOP VIEW
• AN557 “Recommended Test Procedures for Analog
Switches”
Ordering Information
PART
NUMBER
(Note)
TEMP.
RANGE
(°C)
20 19 18 17 16
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
1
2
3
4
5
15
14
13
12
11
2B
3A
3B
4A
4B
NC
ISL54302IRZ* 54 302IRZ -40 to +85 20 Ld 4x4 QFN L20.4x4C
2A
1B
*Add “-T” for tape and reel. Please refer to TB347 for details on reel
specifications.
1A
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
CS-LATCH
6
7
8
9
10
ISL54302 Block Diagram
VLOGIC
VPLUS
VDD
LATCHES
S1-CTRL
1 OF 4
S2-CTRL
SW-A
S3-CTRL
S4-CTRL
LEVEL
SHIFTER
SW-B
GND
VSS
VSS
CS-LATCH
FN6592 Rev 0.00
Mar 19, 2008
Page 1 of 16
ISL54302
Pin Descriptions
PIN NUMBER
PIN NAME
2B
PIN DESCRIPTION
1
2
Switch 2 signal terminal
Switch 2 signal terminal
Switch 1 signal terminal
Switch 1 signal terminal
Chip Select input
2A
3
1B
4
1A
5
CS-LATCH
S1-CTRL
S2-CTRL
GND
6
Switch one logic control
Switch two logic control
Device ground terminal
Switch three logic control
Switch four logic control
Not internally connected
Switch 4 signal terminal
Switch 4 signal terminal
Switch 3 signal terminal
Switch 3 signal terminal
Positive analog power supply
Logic supply voltage
7
8
9
S3-CTRL
S4-CTRL
NC
10
11
12
13
14
15
16
17
18
19
20
4B
4A
3B
3A
VPLUS
VLOGIC
VDD
Level shifter supply voltage
Negative analog power supply
Not internally connected
VSS
NC
FN6592 Rev 0.00
Mar 19, 2008
Page 2 of 16
ISL54302
Absolute Maximum Ratings
Thermal Information
VPLUS to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to15V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5V
VLOGIC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5V
VSS to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4V to 0.3V
VPLUS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V
All Other Pins (Note 1). . . . . . . . ((VSS) - 0.3V) to ((VPLUS) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 35mA
Peak Current, 1A-4A,1B-4B
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . 100mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>3kV
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Resistance (Typical)
(°C/W)
32
(°C/W)
1.4
JA
JC
20 Ld QFN Package (Notes 2, 3) . . . . . .
Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Analog Switch Signal Range . . . . . . . . VSS + 0.5V to VPLUS - 0.5V
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Signals on 1A-4A,1B-4B, exceeding VPLUS or VSS are clamped by internal diodes. DATA_IN, CLOCK_IN, CS_LATCH exceeding VLOGIC or
VSS are clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
3. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Test Conditions: VPLUS = +9V, VSS = -3V Supply, VLOGIC = 3V, VDD = GND = 0V, V
= 2.2V, V = 0.8V,
INL
INH
Unless Otherwise Specified.
TEMP
(°C)
MIN
TYP
MAX
PARAMETER
TEST CONDITIONS
(Note 9) (Note 10) (Note 9) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-resistance, r
I
= 10mA, VXA, VXB within analog signal
COM
25
Full
25
2.0
2.5
0.2
0.3
0.4
0.6
15
ON
(see Figure 4)
r
Matching Between Channels,
I
= 10mA, VXA, VXB within analog signal range
ON
r
COM
(Note 5)
ON
Full
25
r
Flatness, r
FLAT(ON)
I
= 10mA, VXA, VXB within analog signal range
COM
ON
(Note 4)
Full
25
OFF Leakage Current, I
VXA, VXB within analog signal range
nA
nA
NO(OFF)
Full
-200
2.2
+200
0.8
DIGITAL INPUT CHARACTERISTICS (Note 8)
Input Voltage High, Digital Interface SW-CTRL(1-4), CS_LATCH
Input Voltage Low, Digital Interface SW-CTRL(1-4), CS_LATCH
Full
Full
Full
1.75
1.75
1
V
V
tSETUP (Note 6, Figure 5)
SW-CTRL (1-4) Into CS_Latch
Setup Time
ns
SW-CTRL (1-4) Into CS_Latch Hold
Time
t
(Note 6, Figure 5)
= 0V or VLOGIC
Full
3.5
ns
HOLD
Input Current, I , I
INH INL
V
Full
Full
Full
-1
0.01
3
1
µA
ns
ns
IN
CS_LATCH Rise, Fall Time
10% to 90% and 90% to 10%
CS_LATCH Minimum Pulse Width Rising to Falling Edge 50% Points
10
SWITCH DYNAMIC CHARACTERISTICS
Turn-ON Time, t
VXA, VXB = 3V, R = 300, C = 35pF, V = 0V to 3V,
IN
(see Figure 1)
25
50
55
ns
ns
ON
L
L
Full
FN6592 Rev 0.00
Mar 19, 2008
Page 3 of 16
ISL54302
Electrical Specifications Test Conditions: VPLUS = +9V, VSS = -3V Supply, VLOGIC = 3V, VDD = GND = 0V, V
Unless Otherwise Specified. (Continued)
= 2.2V, V
= 0.8V,
INL
INH
TEMP
(°C)
MIN
TYP
MAX
PARAMETER
Turn-OFF Time, t
TEST CONDITIONS
VXA, VXB = 3V, R = 300, C = 35pF, V = 0V to 3V,
(Note 9) (Note 10) (Note 9) UNITS
25
Full
25
90
95
ns
ns
OFF
L
L
IN
(see Figure 1)
OFF Capacitance, C
f = 1MHz, VXA or VXB = 0V
f = 1MHz, VXA or VXB = 0V
50
pF
OFF
ON Capacitance, C
OFF Isolation
25
100
-45
-65
60
pF
COM(ON)
R
= 50, C = 15pF, f = 1MHz,
25
dB
dB
MHz
pC
L
L
VXA or VXB = 1V
(see Figure 3)
P-P
Crosstalk (Note 5)
25
Switch Contact 3dB Bandwidth
Charge Injection, Q
R
C
= 50, C = 5pF
L
L
L
= 1nF, V = 0V, R = 0see Figure 2)
25
125
G
G
POWER SUPPLY CHARACTERISTICS
VPLUS Supply, I (Quiescent)
25
Full
25
15
17
18
22
16
22
1
µA
µA
µA
µA
µA
µA
mA
mA
µA
µA
mA
mA
µA
µA
mA
mA
45
50
10
VPLUS Supply, I (40MHz)
VSS Supply, I (Quiescent)
VSS Supply, I (40MHz)
VDD Supply, I (Quiescent)
VDD Supply, I (40MHz)
Full
25
Full
25
Full
25
1
1
Full
25
4
0.4
0.4
0
Full
25
VLOGIC Internal Logic Supply, I
(Quiescent)
Full
25
1
10
VLOGIC Internal Logic Supply, I
(40MHz)
3.5
3.5
Full
Electrical Specifications Test Conditions: VPLUS = +7V, VSS = 0V Supply, VLOGIC= 3V, VDD = 3V, GND = 0V, V
= 2.2V, V
= 0.8V,
INH
INL
Unless Otherwise Specified.
TEMP
(°C)
MIN
TYP
MAX
PARAMETER
TEST CONDITIONS
(Note 9) (Note 10) (Note 9) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-resistance, r
I
= 10mA, VXA, VXB within Analog Signal Range
COM
25
Full
25
2.7
3.5
0.1
0.15
0.5
0.6
3
ON
(see Figure 4)
r
Matching Between Channels,
I
= 10mA, VXA, VXB within Analog Signal Range
ON
r
COM
(Note 5)
ON
Full
25
r
Flatness, r
I = 10mA, VXA, VXB within Analog Signal Range
COM
(Note 4)
ON
FLAT(ON)
Full
25
OFF Leakage Current, I
VXA = 1V, 4.5V, VXB= 4.5V, 1V
nA
nA
NO(OFF)
Full
-200
2.2
30
200
0.8
DIGITAL INPUT CHARACTERISTICS (Note 8)
Input Voltage High, Digital Interface SW-CTRL(1-4), CS_LATCH
Input Voltage Low, Digital Interface SW-CTRL(1-4), CS_LATCH
Full
Full
1.75
1.75
V
V
FN6592 Rev 0.00
Mar 19, 2008
Page 4 of 16
ISL54302
Electrical Specifications Test Conditions: VPLUS = +7V, VSS = 0V Supply, VLOGIC= 3V, VDD = 3V, GND = 0V, V
Unless Otherwise Specified. (Continued)
= 2.2V, V = 0.8V,
INL
INH
TEMP
(°C)
MIN
TYP
MAX
PARAMETER
TEST CONDITIONS
SETUP (Note 6, Figure 5)
(Note 9) (Note 10) (Note 9) UNITS
t
SW-CTRL (1-4) Into CS_Latch
Setup Time
Full
1
ns
ns
SW-CTRL (1-4) Into CS_Latch Hold
Time
t
(Note 6, Figure 5)
Full
3.5
HOLD
Input Current, I
, I
INH INL
V
= 0V or VLOGIC
Full
Full
Full
-1
0.01
3
1
µA
ns
ns
IN
10% to 90% and 90% to 10%
CS_LATCH Rise, Fall Time
CS_LATCH Minimum Pulse Width Rising to Falling Edge 50% Points
10
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
VXA or VXB = 3V, R = 300, C = 35pF
(see Figure 1)
25
Full
25
25
30
ns
ns
ON
L
L
Turn-OFF Time, t
VXA or VXB = 3V, R = 300, C = 35pF
80
ns
OFF
L
L
(see Figure 1)
Full
25
85
ns
OFF Capacitance, C
f = 1MHz, VXA or VXB = V
f = 1MHz, VXA or VXB = V
= 0V
= 0V
50
pF
OFF
COM
COM
ON Capacitance, C
OFF Isolation
25
100
-45
-65
60
pF
COM(ON)
R
= 50, C = 15pF, f = 1MHz,
25
dB
dB
MHz
pC
L
L
VXA or VXB= 1V
(see Figure 3)
P-P
Crosstalk (Note 5)
25
Switch Contact 3dB Bandwidth
Charge Injection, Q
R
C
= 50, C = 5pF
25
L
L
L
= 1nF, V = 0V, R = 0see Figure 2)
25
25
G
G
POWER SUPPLY CHARACTERISTICS
VPLUS Supply, I (Quiescent)
25
Full
25
13
15
18
20
14
19
0.7
0.7
1
µA
µA
µA
µA
µA
µA
mA
mA
µA
µA
mA
mA
µA
µA
mA
mA
45
50
10
10
VPLUS Supply, I (40MHz)
VSS Supply, I (Quiescent)
VSS Supply, I (40MHz)
VDD Supply, I (Quiescent)
VDD Supply, I (40MHz)
Full
25
Full
25
Full
25
Full
25
4
0.4
0.5
0
Full
25
VLOGIC Internal Logic Supply, I
(Quiescent)
Full
25
1
VLOGIC Internal Logic Supply, I
(40MHz)
3.2
3.2
Full
NOTES:
4. Flatness is defined as the delta between the maximum and minimum r
5. Between any two switches.
values over the specified voltage range.
ON
6. CS_LATCH must remain low when changing SW-CTRL(1-4) condition. Likewise, while CS_LATCH is being toggled, it is important to keep SW-
CTRL(1-4) in the intended switch condition.
7. Typical Values are not production tested
8. Digital Characteristics remain stable with respect to VPLUS and VSS variation. These parameters are controlled by the difference between VSS
and VDD, which the user should maintain at a constant spread of VDD = VSS + 3V.
9. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
10. Limits established by characterization and are not production tested.
FN6592 Rev 0.00
Mar 19, 2008
Page 5 of 16
ISL54302
Test Circuits and Waveforms
3V
t < 20ns
r
t < 20ns
f
VPLUS
VDD
VLOGIC
C
C
C
CS-LATCH
C
50%
INPUT
0V
t
ON
V
1-4A
OUT
1-4B
V
NB
V
NB
SWITCH
INPUTS
IN
V
OUT
25%
75%
LATCH
GND
C
R
L
L
SWITCH
OUTPUT
35pF
300
t
SX-CRTL
INPUT
OFF
C
VSS
V
NB
Repeat test for all switches. C includes fixture and stray
L
V
OUT
capacitance.
R
L
----------------------------
V
= V
Switch changes state on rising edge of CS-LATCH. V
all times.
= VOUT at
OUT
(NB)
NA
R
+ r
ON
L
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
VPLUS
VDD
VLOGIC
C
C
C
SWITCH
OUTPUT
V
OUT
V
R
OUT
G
1-4A
1-4B
GND
V
OUT
3V
LATCH
ON
ON
OFF
V
G
IN
0V
C
L
CONTROLLER
SEQUENCE
Q = V
OUT
x C
L
C
SW: ON/OFF/ON
VSS
Switch changes state on rising edge of CS-LATCH.
FIGURE 2A. MEASUREMENT POINTS
Repeat test for all switches. C includes fixture and stray
L
capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
VPLUS
VDD
VLOGIC
C
VPLUS
VDD
VLOGIC
C
C
C
C
C
r
= V /10mA
1
ON
SIGNAL
GENERATOR
1-4A
1-4A
V
XA
10mA
CS-LATCH/SX-CRTL
CS-LATCH/SX-CRTL
V
1
1-4B
1-4B
ANALYZER
GND
GND
R
L
C
C
VSS
VSS
Repeat test for all switches.
FIGURE 3. OFF ISOLATION TEST CIRCUIT
Repeat test for all switches.
FIGURE 4. r
TEST CIRCUIT
ON
FN6592 Rev 0.00
Mar 19, 2008
Page 6 of 16
ISL54302
Test Circuits and Waveforms (Continued)
SX-CTRL SHOULD REMAIN IN DESIRED STATE, BEFORE DURING AND AFTER CS-LATCH.
CS-LATCH
INPUT
50%
50%
t
t
SETUP
100%
HOLD
100%
DATA = 1
SX-CTRL
DATA = 0
FIGURE 5. SETUP AND HOLD TIMES
ISL54302 Parallel Communications
ISL54302 Detailed Description
The ISL54302 operates based on parallel data. CTRL and
LATCH inputs are 3V level compatible. Setup and Hold times
relative to the rising the edge of the CS-LATCH input must
be maintained for proper operation. Switch control data is
clocked into internal registers on the rising edge of
CS-LATCH.
The ISL54302 quad analog switches offer switching capability
from a split-supply -3V and +9V or single 0V and 5V to 12V
supply. Please review “Power Supply Considerations” on
page 7 before powering up the device.
The user can employ multi-device control data in two ways.
The S1-S4-CTRL lines can be connected to several devices,
with each device having its own CS-LATCH connection to
the system controller. The other way is to have separate
S1-4-CTRL connections for each switch and a single
CS-LATCH connection to all ISL54302s.
MULTIPLE DEVICE CONNECTION
The user can configure the four SX-CTRL inputs to connect
to several ISL54302’s. In this configuration each ISL54302
requires a separate/dedicated CS-LATCH input. Therefore,
each device will update at different times.
Power Supply Considerations
So in essence, the S1-S4-CTRL signals are multiplexed and
connected to all switch control inputs in parallel (see Figure 8).
The ISL54302 construction consists of CMOS analog
switches and four supply pins: VPLUS, VSS, VLOGIC, VDD
and GND. VPLUS and VSS determine the switch voltage
range of the four SPST CMOS switches and set their analog
voltage limits. There are no connections between the switch
contact signal path and GND.
For non-multiplexed connections, each SX-CTRL input must
have a dedicated logic input for each switch/each device. If
three ISL54302s are being used, the user must supply 12
dedicated SX-CTRL signals. All switches are then tied to the
same CS-LATCH pin and all devices would change state at
the same time.
VLOGIC and GND power the digital input/output logic level
shifters (thus setting the digital switching point). The level
shifters convert the external logic levels to VDD and VSS
signals to drive the internal digital circuitry.
ISL54302 CS-LATCH Pin Discussion
The ISL54302’s operational state does not change while
SX-CTRL inputs are changing. The user must insure that the
CS-LATCH pin remains low and does not change state while
SX-CTRL inputs are changing.
VDD and VSS power the internal logic of the device. VDD
must always be held at a fixed 3V above VSS to avoid
device damage.
Whether operating split or single device, GND will
always be @ 0V and VLOGIC will always be @ 3V.
Once the user has set the SX-CTRL inputs, the CS-LATCH
pin is then utilized. Just as the CS-LATCH pin must remain
low during SX-CTRL setup, the SX-CTRL pins must remain
stable during and after the CS-LATCH operation.
VDD should always remain 3V above VSS. VSS to
VPLUS should not exceed a maximum spread of more
than 12V. For examples, see the following:
The switch from present to next operation occurs on the
rising edge on the CS-LATCH pin. This rising edge transfers
data to the internal 4-bit switch control registers. This
transfer updates opening/closing of the four switches.
SPLIT POSITIVE AND NEGATIVE SWITCH RANGE
OPERATION
• VSS = -3V, VDD = +0V, VPLUS = +9V, VLOGIC = 3V
• VSS = -1V, VDD = +2V, VPLUS = +11V, VLOGIC = 3V
ISL54302 Power On Reset (POR)
Switch conditions are controlled during POR (Power On
Reset). During and after a POR condition, the switches are
opened until closed by the controller.
POSITIVE SWITCH RANGE OPERATION
• VSS = 0V, VDD = +3V, VPLUS = +12V, VLOGIC = 3V
FN6592 Rev 0.00
Mar 19, 2008
Page 7 of 16
ISL54302
SW2-B
SW2-A
SW3-A
SW3-B
S3 CONTROL
S2 CONTROL
INTERNAL
CS-LATCH
REGISTERS
INTERNAL
CS-LATCH
REGISTERS
SW1-B
SW1-A
SW4-A
SW4-B
S4 CONTROL
S1 CONTROL
LEVEL
SHIFTER
LEVEL
LEVEL
LEVEL
LEVEL
SHIFTER SHIFTER
SHIFTER SHIFTER
FIGURE 6. ISL54302 FUNCTIONAL DIAGRAM
The leakage current performance is unaffected by this
approach, but the switch resistance may increase, especially
at low supply voltages.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents,
which might permanently damage the IC. All switch contact
I/O pins contain ESD protection diodes from the pin to
VPLUS and to VSS (see Figure 7). To prevent forward
biasing these diodes, VPLUS, GND and VSS must be
applied before any input signals, and switch signal voltages
must remain between VPLUS and VSS. Digital control
signals should be limited to VLOGIC and VSS.
ESD Protection
The device contains ESD protection on the device pins.
These devices are design to work based on dV/dt. During
power-up, the user should review the rise/fall times on the
power connections. The rise time of the power rails should
not be faster than 1µs.
VPLUS
VDD
VLOGIC
SPECIFIC POWER SEQUENCE
1. GND
CLAMP
VSS
CLAMP
VSS
CLAMP
GND
2. VSS Typical . . . . . . . . . . . 3V to 0V with respect to GND
3. VPLUS Typical. . . . . . . +5V to +9V with respect to GND
4. VDD . . . . . . . . . . . . . . . . . . . +3V to with respect to VSS
5. VLOGIC . . . . . . . . . . . . . . . . . . +3V with respect to GND
VPLUS
ONE FOR EACH PIN LISTED: 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B,
VDD, VLOGIC
If these conditions cannot be guaranteed, then one of the
following two protection methods should be employed.
VLOGIC
Logic inputs can easily be protected by adding a 1k
resistor in series with the input. The resistor limits the input
current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
ONE FOR EACH PIN LISTED: S1-CTRL, S2-CTRL,
S3-CTRL, S4-CTRL, CS-LATCH
GND
VSS
Adding a series resistor to the switch input defeats the purpose
FIGURE 7. ESD/OVERVOLTAGE PROTECTION
of using a low r
switch, so two small signal diodes can be
ON
added in series with the supply pins to provide overvoltage
protection for all pins (see Figure 7). These additional diodes
limit the analog signal from 1V below VPLUS to 1V above VSS.
FN6592 Rev 0.00
Mar 19, 2008
Page 8 of 16
ISL54302
Logic-Level Thresholds
ISL54302 Device Programming
VLOGIC and GND power the internal logic level shifter
stages, so VPLUS and VSS have no affect on logic
thresholds. Thus, SX-CTRL, CS-LATCH receive thresholds
which will remain constant, despite changes to VPLUS and
VSS.
Programming the device entails accessing the internal
switch control registers. To write data into the register, the
data must be transferred via the CS-LATCH pin.
Via the CS-LATCH pin, the programmer has complete
control as to “when” data is transferred to the internal
latches. Until such time as the CS-LATCH pin is “toggled,”
the device will remain as previously programmed. Therefore,
data transitions on the SX-CTRL inputs will not effect the
switch’s operational condition.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both VPLUS and VSS.
One of these diodes conducts if any analog signal exceeds
VPLUS or VSS.
FN6592 Rev 0.00
Mar 19, 2008
Page 9 of 16
ISL54302
VPLUS (VSUB+5 TO VSUB+12V)
VLOGIC (GND + 3V)
VDD (VSUB +3V)
VSUB (-3V TO 0V)
C1
4.7µF
C2
4.7µF
C3
4.7µF
C4
4.7µF
SWITCH CONTACT
CONNECTIONS
GND
CS-LATCH DEVICE 1
CS-LATCH
DIGITAL INPUTS FROM
SYSTEM CONTROLLER
SW1-CTRL
SW2-CTRL
SW3-CTRL
SW4-CTRL
6
7
20
19
18
17
16
SW1_CTRL
NC
VSS
SW2_CTRL
GND
8
VDD
9
10
SW3_CTRL
SW4_CTRL
VLOGIC
VPLUS
C5
0.1µF
C8
0.1µF
C9
0.1µF
C10
0.1µF
ISL54302
SWITCH CONTACT
CONNECTIONS
CS-LATCH DEVICE 2
CS-LATCH
6
DEVICE DECOUPLING
20
SW1_CTRL
NC
7
8
19
18
17
16
SW2_CTRL
GND
VSS
VDD
9
SW3_CTRL
SW4_CTRL
VLOGIC
VPLUS
10
C6
0.1µF
C11
0.1µF
C12
0.1µF
C13
0.1µF
ISL54302
SWITCH CONTACT
CONNECTIONS
CS-LATCH DEVICE 3
CS-LATCH
6
20
SW1_CTRL
NC
7
8
19
18
17
16
SW2_CTRL
GND
VSS
VDD
9
SW3_CTRL
SW4_CTRL
VLOGIC
VPLUS
10
C7
0.1µF
C14
0.1µF
C15
0.1µF
C16
0.1µF
ISL54302
GND
SWITCH CONTACT
CONNECTIONS
FIGURE 8. ISL54302 SW-CONTROL LINES MULTIPLEXED
FN6592 Rev 0.00
Mar 19, 2008
Page 10 of 16
ISL54302
Typical Performance Curves VLOGIC = 3V, T = +25°C, V = 3V, V = 0V, Unless Otherwise Specified.
A
IH
IL
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
I
= 10mA
VSS = -3V, VPLUS = 3V, VDD = 0V
COM
+85°C
+25°C
+85°C
+25°C
-40°C
-40°C
I
= 10mA
VSS = 0V, VPLUS = 5V, VDD = 3V
COM
4
-3
-2
-1
0
1
2
3
0
1
2
3
5
V
(V)
V
(V)
COM
COM
FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
5.0
5.0
I
= 10mA
VSS = 0V, VPLUS = 7V, VDD = 3V
COM
I
= 10mA
VSS = -3V, VPLUS = 7V, VDD = 0V
COM
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
+85°C
+85°C
+25°C
+25°C
-40°C
-40°C
0
1
2
3
4
5
6
7
-3
-2
-1
0
1
2
3
4
5
6
7
V
(V)
V
(V)
COM
COM
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
5.0
5.0
I
= 10mA
I
= 10mA
VSS = 0V, VPLUS = 12V, VDD = 3V
VSS = -3V, VPLUS = 9V, VDD = 0V
COM
COM
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.5
4.0
3.5
3.0
2.5
+85°C
+85°C
2.0
1.5
1.0
0.5
-40°C
-40°C
+25°C
+25°C
0.0
-3
-2 -1
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
10 11 12
V
(V)
COM
V
(V)
COM
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
FN6592 Rev 0.00
Mar 19, 2008
Page 11 of 16
ISL54302
Typical Performance Curves VLOGIC = 3V, T = +25°C, V = 3V, V = 0V, Unless Otherwise Specified. (Continued)
A
IH
IL
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VSS = -3V, VPLUS = 3V, VDD = 0V
VSS = 0V, VPLUS = 5V, VDD = 3V
-3
-2
-1
0
1
2
3
0
1
2
3
4
5
V
(V)
V
(V)
COM
COM
FIGURE 15. ON-LEAKAGE vs SWITCH VOLTAGE
FIGURE 16. ON-LEAKAGE vs SWITCH VOLTAGE
5.0
5.0
VSS = 0V, VPLUS = 7V, VDD = 3V
VSS = -3V, VPLUS = 7V, VDD = 0V
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-3
-2
-1
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
V
(V)
V
(V)
COM
COM
FIGURE 17. ON-LEAKAGE vs SWITCH VOLTAGE
FIGURE 18. ON-LEAKAGE vs SWITCH VOLTAGE
5.0
5.0
VSS = -3V, VPLUS = 9V, VDD = 0V
VSS = 0V, VPLUS = 12V, VDD = 3V
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-3
-2 -1
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
10 11
12
V
(V)
V
(V)
COM
COM
FIGURE 19. ON-LEAKAGE vs SWITCH VOLTAGE
FIGURE 20. ON-LEAKAGE vs SWITCH VOLTAGE
FN6592 Rev 0.00
Mar 19, 2008
Page 12 of 16
ISL54302
Typical Performance Curves VLOGIC = 3V, T = +25°C, V = 3V, V = 0V, Unless Otherwise Specified. (Continued)
A
IH
IL
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VSS = 0V, VPLUS = 5V, VDD = 3V
VSS = -3V, VPLUS = 3V, VDD = 0V
-3
-2
-1
0
1
2
3
0
1
2
3
4
5
V
(V)
V
(V)
COM
COM
FIGURE 21. OFF-LEAKAGE vs SWITCH VOLTAGE
FIGURE 22. OFF-LEAKAGE vs SWITCH VOLTAGE
10
10
VSS = 0V, VPLUS = 7V, VDD = 3V
VSS = -3V, VPLUS = 7V, VDD = 0V
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
-3
-2
-1
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
V
(V)
V
(V)
COM
COM
FIGURE 23. OFF-LEAKAGE vs SWITCH VOLTAGE
FIGURE 24. OFF-LEAKAGE vs SWITCH VOLTAGE
10
10
VSS = -3V, VPLUS = 9V, VDD = 0V
VSS = 0V, VPLUS = 12V, VDD = 3V
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10 11
12
-3 -2 -1
0
1
2
3
4
5
6
7
8
9
V
(V)
V
(V)
COM
COM
FIGURE 25. OFF-LEAKAGE vs SWITCH VOLTAGE
FIGURE 26. OFF-LEAKAGE vs SWITCH VOLTAGE
FN6592 Rev 0.00
Mar 19, 2008
Page 13 of 16
ISL54302
Typical Performance Curves VLOGIC = 3V, T = +25°C, V = 3V, V = 0V, Unless Otherwise Specified. (Continued)
A
IH
IL
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
VSS = -3V, VCOM = VPLUS - 1V, VDD = 0V
VSS = 0V, VCOM = VPLUS - 1V, VDD = 3V
= 10mA
I
I
= 10mA
COM
COM
+25°C
+25°C
+85°C
+85°C
-40°C
-40°C
3.0
4.5
6.0
7.5
VPLUS (V)
9.0
10.5
12.0
3
4
5
6
7
8
9
VPLUS (V)
FIGURE 28. ON-RESISTANCE vs SUPPLY VOLTAGE
FIGURE 27. ON-RESISTANCE vs SUPPLY VOLTAGE
17.0
2.00
VSS = -3V, VDD = 0V
VSS = -3V, VDD = 0V
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
1.94
1.88
1.82
1.76
1.70
1.64
1.58
1.52
1.46
1.40
+25°C
+85°C
+85°C
+25°C
-40°C
-40°C
3
4
5
6
7
8
9
2.5
2.7
2.9
3.1
3.3
3.5
VPLUS (V)
VPLUS (V)
FIGURE 29. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 30. DEVICE QUIESCENT CURRENT (VPLUS)
450
60
VPLUS = 9V, VSS = -3V, VDD = 0V
400
50
350
300
VPLUS = 9V, VSS = -3V, VDD = 0V
40
VPLUS = 12V, VSS = 0V,
VDD = 3V
250
200
150
100
50
30
VPLUS = 7V, VSS = 0V,
VDD = 3V
20
VPLUS = 9V, VSS = 0V, VDD = 3V
10
0
0
-3 -2 -1
0
1
2
3
4
5
6
7
8
9
10 11 12
-3 -2 -1
0
1
2
3
4
5
6
7
8
9
V
(V)
V
(V)
COM
COM
FIGURE 32. t
vs VCOM
FIGURE 31. CHARGE INJECTION vs SWITCH VOLTAGE
ON
FN6592 Rev 0.00
Mar 19, 2008
Page 14 of 16
ISL54302
Typical Performance Curves VLOGIC = 3V, T = +25°C, V = 3V, V = 0V, Unless Otherwise Specified. (Continued)
A
IH
IL
0
0
VPLUS = 9V, VSS = 0V, VDD = 3V
VPLUS = 9V, VSS = -3V, VDD = 0V
VPLUS = 9V, VSS = 0V, VDD = 3V
VPLUS = 9V, VSS = -3V, VDD = 0V
-10
10
R
= 50
R
= 50
L
L
-20
-30
20
30
-40
40
-50
-60
50
60
-70
70
-80
80
-90
90
-100
-110
100
110
1k
10k
100k
1M
10M
100M 500M
1k
10k
100k
1M
10M
100M 500M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 33. CROSSTALK
FIGURE 34. OFF-ISOLATION
VPLUS = 9V
0
-1
-2
-3
-4
-5
-6
-7
-8
VPLUS = 5V TO 9V, VSS = 0V, VDD = 3V
CS-LATCH
GAIN
4
0
V
= 0V, V
= 3V
DD
SS
4
0
DATA = 0
DATA = 1
SX-CRTL
V
= -3V, V
= 0V
DD
SS
4
0
SWITCH OFF
SWITCH ON
R
= 50
L
VOUT WITH VCOM = 3V
V
= 0.2V
to 2V
P-P
IN
P-P
1
10
100
600
40ms/DIV
FREQUENCY (MHz)
FIGURE 35. FREQUENCY RESPONSE
FIGURE 36. TIMING
© Copyright Intersil Americas LLC 2008. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6592 Rev 0.00
Mar 19, 2008
Page 15 of 16
ISL54302
L20.4x4C
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/06
4X
2.0
4.00
0.50
16X
A
6
B
16
20
PIN #1 INDEX AREA
6
PIN 1
INDEX AREA
1
15
2 .70 ± 0 . 15
11
5
0.15
(4X)
6
10
0.10 M
C
A B
4
20X 0.25 +0.05 / -0.07
20X 0.4 ± 0.10
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
0 . 90 ± 0 . 1
C
BASE PLANE
( 3. 8 TYP )
(
SEATING PLANE
0.08 C
2. 70 )
( 20X 0 . 5 )
SIDE VIEW
5
C
0 . 2 REF
( 20X 0 . 25 )
( 20X 0 . 6)
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
TYPICAL RECOMMENDED LAND PATTERN
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6592 Rev 0.00
Mar 19, 2008
Page 16 of 16
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