ISL54405IRTZ-T13 [RENESAS]
SGL POLE DOUBLE THROW SWITCH;
| 型号： | ISL54405IRTZ-T13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SGL POLE DOUBLE THROW SWITCH 光电二极管 |
| 文件： | 总20页 (文件大小：911K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD/MP3 Quality Stereo 2:1 Multiplexer with Click and
Pop Elimination
ISL54405
Features
The Intersil ISL54405 is a single supply, bidirectional, dual
single-pole/double-throw (SPDT) ultra low distortion, high
OFF-Isolation analog switch that can pass analog signals that
are positive and negative with respect to ground. It is primarily
targeted at consumer and professional audio switching
applications such as computer sound cards and home theater
products. The inputs can accommodate ground referenced
• Clickless audio switching
• 2 switches
• Switch type SPDT or 2 to 1 MUX
• 2V
RMS
signal switching from 3.3V or 5V supply
• -106dB THD+N into 20k load at 2V
RMS
• -108dB THD+N into 32 load at 3.9mW
• Signal to noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >124dBV
• ±0.01dB insertion loss at 1kHz, 20k load
• ±0.007dB gain variation 20Hz to 20kHz
• 125dB signal muting into 20k load
signals up to 2V
while operating from a single 3.3V or 5V DC
RMS
supply. The digital logic inputs are 1.8V logic-compatible when
using a single 3.3V or 5V supply. It can be used in both AC or DC
coupled ground referenced applications.
The ISL54405 features a soft-switch feature and click/pop
circuitry at each signal pin that eliminates clicks and pops
associated with power-up/down conditions of the preceding
amplifier outputs.
• 90dB PSRR 20Hz to 20kHz
• Single supply operation . . . . . . . . . . . . . . . . . . . . . . . . . 3.3V or 5V
• Available in 16 Ld TSSOP, 16 Ld TQFN, and 16 Ld µTQFN
• Pb-Free (RoHS compliant)
With -106dB THD+N performance with a 2V
RMS
signal into
20k load, superior signal muting, high PSRR and very flat
frequency response, the ISL54405 meets the exacting
requirements of consumer and professional audio engineers.
Applications
• Computer sound cards
The ISL54405 is available in 16 Ld TSSOP, 16 Ld 3mmx3mm
TQFN, and 16 Ld 2.6mmx1.8mm µTQFN packages. It’s specified
for operation over the -40°C to +85°C temperature range.
• Home theater audio products
• SACD/DVD audio
Related Literature
• TB363 “Guidelines for Handling and Processing Moisture
Sensitive Surface Mount Devices (SMDs)”
• DVD player audio output switching
• Headsets for MP3/cellphone switching
• Hi-Fi audio switching application
• AN557 “Recommended Test Procedures for Analog
Switches”
5V_Supply
VDD
ISL54405
LOGIC
AND
CLICK/POP
CONTROL
DIR_SEL
CAP_SS
AC/DC
MUTE
SEL
L1
L2
L
R1
R2
R
GND
For 5V operation connect the 5V_Supply pin to 5V and float the
VDD pin. For 3.3V operation connect the VDD pin to 3.3V and float
the 5V_Supply pin.
FIGURE 1. ISL54405 BLOCK DIAGRAM
May 6, 2014
FN6699.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2008, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL54405
Pin Configurations (Note 1)
ISL54405
(16 LD µTQFN)
TOP VIEW
ISL54405
(16 LD TQFN)
TOP VIEW
16
15
14
13
16
15
14
13
1
2
3
4
12
11
10
9
MUTE
L
L1
L2
R1
R2
MUTE
1
2
3
4
12 L1
L
R
11
10
9
L2
R1
R2
R
SEL
SEL
5
6
7
8
5
6
7
8
ISL54405
(16 LD TSSOP)
TOP VIEW
5V_Supply
AC/DC
MUTE
L
1
16 VDD
2
3
4
5
6
7
8
15 CAP_SS
14 L1
13 L2
R
12 R1
SEL
11 R2
10 GND
GND
9
GND
DIR_SEL
NOTE:
1. See Figure 1 on page 1.
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ISL54405
Truth Table
INPUTS
OUTPUTS
COM (L, R)
L1, R1
L2, R2
AC/DC
DIR
MUTE
SEL
0
L1, R1
ON
L2, R2
OFF
ON
C/P SHUNTS
C/P SHUNTS
C/P SHUNTS
0
0
0
1
1
1
1
1
1
X
X
X
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
1
OFF
OFF
ON
X
OFF
OFF
ON
0
1
OFF
OFF
ON
OFF
ON
X
OFF
OFF
ON
ON
0
OFF
OFF
OFF
OFF
OFF
OFF
1
OFF
OFF
X
OFF
NOTE: MUTE, AC/DC, DIR: Logic “0” 0.5V, Logic “1” 1.4V or float with a 3.3V supply or 5V supply.
SEL: Logic “0” 0.5V, Logic “1” 1.4V with a 3.3V supply or 5V supply.
X = Don’t Care
Pin Descriptions
PIN #
PIN #
TSSOP
µTQFN, TQFN
PIN NAME
VDD
DESCRIPTION
16
14
15
System power supply pin (+3V to +3.6V) (float pin for 5V applications)
5V supply pin (+4.5V to +5.5V) (float pin for 3.3V applications)
Ground connection
1
5V_Supply
GND
7, 9, 10
5, 7, 8
13
15
CAP_SS
MUTE
SEL
Soft-start capacitor pin
3
1
Signal mute control pin
6
4
Input select control pin
2
16
AC/DC
DIR_SEL
R
AC/DC select control pin
8
5
6
Direction select control pin
3
Analog switch common pin
4
2
L
Analog switch common pin
11, 13
12, 14
9, 11
10, 12
R2, L2
R1, L1
Analog switch normally open pin
Analog switch normally closed pin
Ordering Information
PACKAGE
(Pb-Free)
PKG.
DWG. #
PART NUMBER
ISL54405IVZ (Notes 3, 4)
ISL54405IRTZ (Notes 3, 4)
ISL54405IRUZ-T (Notes 2, 5)
NOTES:
PART MARKING
TEMP. RANGE (°C)
-40 to +85
54405 IVZ
05TZ
16 Ld TSSOP
M16.173
-40 to +85
16 Ld 3x3 TQFN
16 Ld µTQFN
L16.3x3A
GAD
-40 to+ 85
L16.2.6x1.8A
2. Please refer to TB347 for details on reel specifications.
3. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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ISL54405
Absolute Maximum Ratings
Thermal Information
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V
5V_Supply to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Input Voltages
Thermal Resistance (Typical)
(°C/W)
110
75
(°C/W)
41
11
JA
JC
16 Ld TSSOP Package (Note 7) . . . . . . . . .
16 Ld TQFN Package (Notes 8, 9) . . . . . . .
16 Ld µTQFN Package (Note 8) . . . . . . . . .
SEL, MUTE, AC/DC, DIR_SEL (Note 6) . . . . . . . . . . -0.3 to ((V ) + 0.3V)
93
N/A
DD
L1, L2, R1, R2 (Note 6) . . . . . . . . . . . . . . . . . . . . . . -3.1 to ((V ) + 0.3V)
DD
Output Voltages
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
R, L (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3.1 to ((V ) + 0.3V)
DD
Continuous Current L1, L2, R1, R2 or L, R . . . . . . . . . . . . . . . . . . ±300mA
Peak Current L1, L2, R1, R2 or L, R
(Pulsed 1ms, 10% Duty Cycle, Max). . . . . . . . . . . . . . . . . . . . . . ±500mA
ESD Rating:
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. Signals on L1, L2, R1R2, MUTE, SEL, AC/DC, DIR_SEL, R, and L exceeding V or GND by specified amount are clamped. Limit current to maximum
DD
current ratings.
7. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
8. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
9. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications 3.3V Supply: V = +3.0V to +3.6V, GND = 0V, V
= VAC/DC = GND, V
= 0.5V, CAP_SS = 0.1µF, (Note 10), Unless otherwise specified.
= Float,
DD
MUTEH
DIR_SEL 5V_SUPPLY
V
= 2V
, R
RMS LOAD
= 20kΩ , f = 1kHz, V
SELH
= V
= 1.4V, V = V
SELL MUTEL
SIGNAL
SUPPLY TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(V)
(°C) (Notes 11, 12)
TYP
2
(Notes 11, 12) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
3.3, 5
3.3
Full
-
-
V
RMS
V
ANALOG
ON-Resistance, r
V
= 3.3V, I or I = 80mA, V or V =
Lx Rx
25
Full
25
-
1.9
2.6
-
ON
DD
R
L
-2.828V to +2.828V (See Figure 5)
-
-
r
Matching Between
V
= 3.3V, I or I = 80mA, V or V = Voltage at
Lx Rx
3.3
3.3
3.6
-
0.023
0.045
0.003
0.009
300
-
ON
Channels, r
DD
R
L
max r over -2.828V to +2.828V (Note 15)
ON
ON
Full
25
-
-
r
Flatness, r
V
= 3.3V, I or I = 80mA, V or V = -2.828V, 0V,
Lx Rx
-
0.01
ON
FLAT(ON)
DD
R
L
+2.828V (Note 13)
Full
25
-
225
-
-
375
-
L, R, Lx, Rx Pull-down
Resistance
V
= 3.6V, V or V = -2.83V, 2.83V, V or V =
Lx Rx R
k
k
DD
L
-2.83V, 2.83V, V
= 0V, V
= 3.6V, measure
AC/DC MUTE
Full
345
current, calculate resistance.
DYNAMIC CHARACTERISTICS
THD+N
V
R
= 2V
= 20k
, f = 1kHz, A-weighted filter,
3.3, 5
25
25
25
25
25
25
-
-
-
-
-
-
-106
-113
-
-
-
-
-
-
dB
dB
dB
dB
SIGNAL
RMS
LOAD
V
= 1.9V
= 1.8V
, f = 1kHz, A-weighted filter, R
SIGNAL
RMS
RMS
LOAD
LOAD
= 20k
V
, f = 1kHz, A-weighted filter, R
-116
SIGNAL
= 20k
V
= 0.707V
= 32
, f = 1kHz, A-weighted filter,
RMS
-100
SIGNAL
R
LOAD
SNR
f = 20Hz to 20kHz, A-weighted filter, inputs grounded, 3.3, 5
= 20k or 32
>124
±0.01
dBV
dB
R
LOAD
Insertion Loss, G
ON
f = 1kHz, R
= 20k
3.3
LOAD
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ISL54405
Electrical Specifications 3.3V Supply: V = +3.0V to +3.6V, GND = 0V, V
= VAC/DC = GND, V = Float,
5V_SUPPLY
DD
DIR_SEL
= 0.5V, CAP_SS = 0.1µF, (Note 10), Unless otherwise specified.
V
= 2V
, R
RMS LOAD
= 20kΩ , f = 1kHz, V
= V
= 1.4V, V = V
SELL MUTEL
SIGNAL
SELH
MUTEH
SUPPLY TEMP
MIN
MAX
PARAMETER
Gain vs Frequency, G
TEST CONDITIONS
(V)
(°C) (Notes 11, 12)
TYP
(Notes 11, 12) UNITS
f = 20Hz to 20kHz, R
at 1kHz
= 20k, reference to G
3.3
25
25
25
25
-
-
-
-
±0.007
-
-
-
-
dB
dB
dB
dB
f
LOAD
ON
Stereo Channel Imbalance f = 20Hz to 20kHz, R
L1 and R1, L2 and R2
= 20k
3.3
±0.003
120
LOAD
OFF-Isolation (Muting)
f = 20Hz to 22kHz, L = R = 2V
, R
RMS LOAD
= 20k,
3.3, 5
MUTE = AC/DC = 3.3V, DIR_SEL = GND, SEL = “X”
f = 20Hz to 22kHz, L1, R1, L2, R2 = 2V
,
120
RMS
= 20kMUTE = AC/DC = DIR_SEL = 3.3V,
R
LOAD
SEL = “X”
f = 20Hz to 22kHz, V or V = 0.7V
, R
RMS LOAD
= 32
25
25
-
-
125
120
-
-
dB
dB
L
R
Crosstalk (Channel-to-
Channel)
R = 20k, f = 20Hz to 20kHz, V
= 2V ,
RMS
3.3
L
SIGNAL
signal source impedance = 20, Note 16
R = 32, f = 20Hz to 20kHz, V
= 0.7V
RMS,
25
-
120
-
dB
L
SIGNAL
signal source impedance = 20, Note 16
PSRR
f = 1kHz, V = 100mV , inputs grounded
3.3, 5
25
25
25
25
-
-
-
-
110
90
-
-
-
-
dB
dB
SIGNAL
RMS
f = 20kHz, V
= 100mV
, inputs grounded
RMS
SIGNAL
= 50
Bandwidth, -3dB
ON to Mute Time,
R
3.3
3.3
230
50
MHz
ns
LOAD
CAP_SS = 0.1µF
T
TRANS-OM
Mute to ON Time,
CAP_SS = 0.1µF
(Selectable via soft-start capacitor value)
3.3
3.3
3.3
3.6
25
25
25
25
-
-
-
-
58
45
50
45
-
-
-
-
ms
µs
ns
T
TRANS-MO
Turn-ON Time, t
V
= 3.3V, V or V = 1.5V, V
Lx Rx
= 0V, R = 20k
L
ON
DD
MUTE
MUTE
MUTE
(See Figure 2)
Turn-OFF Time, t
OFF
V
= 3.3V, V or V = 1.5V, V
= 0V, R = 20k
L
DD
Lx Rx
(See Figure 2)
Break-Before-Make Time
Delay, t
V
= 3.6V, V or V = 1.5V, V
= 0V, R = 20k
µs
DD
Lx Rx
L
(See Figure 3)
D
OFF-Isolation
R = 50, f = 1MHz, V or V = 1V
(See Figure 4)
(See Figure 6)
3.3
3.3
25
25
-
-
100
70
-
-
dB
dB
L
L
R
RMS
RMS
Crosstalk (Channel-to-
Channel)
R = 50, f = 1MHz, V or V = 1V
L L R
Lx, Rx OFF Capacitance,
f = 1MHz, V or V = V or V = 0V (See Figure 7)
3.3
3.3
25
25
-
-
10
27
-
-
pF
pF
Lx
Rx
L
R
C
OFF
L, R ON Capacitance,
f = 1MHz, V or V = V
Lx Rx
= 0V (See Figure 7)
COM
C
COM(ON)
POWER SUPPLY CHARACTERISTICS
Power Supply Range, VDD 5V_Supply = Float
3.3
5
Full
Full
3
-
-
3.6
5.5
V
V
Power Supply Range,
5V_Supply
V
= Float
4.5
DD
Positive Supply Current, I+
V
= +3.6V, V
= 0V, V
SEL
= 0V or V
3.6
25
Full
25
-
-
-
-
-
-
54
59
14
15
55
58
65
µA
µA
µA
µA
µA
µA
DD
MUTE
MUTE
MUTE
DD
-
18
-
V
V
= +3.6V, V
= +3.6V, V
= V , V
= 0V or V
= 1.8V
3.6
3.6
3.6
3.6
DD
DD
DD SEL
DD
Full
25
= 0V, V
SEL
65
-
Full
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
,
3.3, 5
Full
-
-
0.5
V
SELL
V
MUTEL
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ISL54405
Electrical Specifications 3.3V Supply: V = +3.0V to +3.6V, GND = 0V, V
= VAC/DC = GND, V = Float,
5V_SUPPLY
DD
DIR_SEL
= 0.5V, CAP_SS = 0.1µF, (Note 10), Unless otherwise specified.
V
= 2V
, R
RMS LOAD
= 20kΩ , f = 1kHz, V
= V
= 1.4V, V = V
SELL MUTEL
SIGNAL
SELH
MUTEH
SUPPLY TEMP
MIN
MAX
PARAMETER
Input Voltage High, V
TEST CONDITIONS
(V)
(°C) (Notes 11, 12)
TYP
-
(Notes 11, 12) UNITS
,
3.3,
5
Full
1.4
-
V
SELH
V
MUTEH
Input Current, I
, I
SELH SELL
V
= 3.6V, V
= 3.6V, V
= 0V, V
SEL
= 0V or V
3.6
3.6
Full
Full
-0.5
-1.3
0.01
-0.7
0.5
0.3
µA
µA
DD
MUTE
DD
Input Current, I
,
V
V
, V
AC/DC DIR_SEL
= 0V, V
= Float,
MUTE
AC/DCL
DD
I
= V
DIR_SELL
SEL
DD
Input Current, I
,
V
V
= 3.6V, V
, V
AC/DC DIR_SEL
= V , V
DD MUTE
= 0V,
3.6
Full
-0.5
0.01
0.5
µA
AC/DCH
DD
I
= 0V
DIR_SELH
SEL
Input Current, I
Input Current, I
NOTES:
V
V
= 3.6V, V
= 3.6V, V
= V , V
DD MUTE
= 0V
3.6
3.6
Full
Full
-1.3
-0.5
-0.7
0.3
0.5
µA
µA
MUTEL
MUTEH
DD
DD
SEL
SEL
= 0V, V = V
0.01
MUTE
DD
10. V = input voltage to perform proper function.
IN
11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
13. Flatness is defined as the difference between maximum and minimum value of ON-resistance at the specified analog signal voltage points.
14. Limits established by characterization and are not production tested.
15. r matching between channels is calculated by subtracting the channel with the highest max r value from the channel with lowest max r value.
ON
ON
ON
16. Crosstalk is inversely proportional to source impedance.
Test Circuits and Waveforms
V
DD
C
V
t < 20ns
r
t < 20ns
f
DD
LOGIC
INPUT
50%
0V
V
OUT
t
Lx OR Rx
SEL
OFF
SWITCH
INPUT
L or R
SWITCH
INPUT
V
V
Lx OR Rx
V
OUT
90%
90%
R
C
L
LOGIC
INPUT
L
GND MUTE
SWITCH
OUTPUT
0V
t
ON
Repeat test for all switches. C includes fixture and stray
L
Logic input waveform is inverted for switches that have the opposite logic
sense.
capacitance.
R
L
-----------------------
V
= V
OUT
(Lx or Rx)
R
+ r
ON
L
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. SWITCHING TIMES
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ISL54405
Test Circuits and Waveforms(Continued)
V
DD
C
V
DD
0V
LOGIC
INPUT
Lx
Rx
V
V
OUT
NX
R OR L
C
R
L
L
90%
SWITCH
OUTPUT
SEL
V
OUT
0V
MUTE
GND
t
LOGIC
INPUT
D
Repeat test for all switches. C includes fixture and stray capacitance.
L
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
V
V
DD
DD
C
C
r
= V /80mA
1
SIGNAL
GENERATOR
ON
MUTE
Lx or Rx
Lx or Rx
V
NX
SEL 0V OR V
DD
0V OR V
DD
80mA
SEL
V
1
L, R
L, R
ANALYZER
GND
GND
MUTE
R
L
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 5. r TEST CIRCUIT
ON
FIGURE 4. OFF-ISOLATION TEST CIRCUIT
V
DD
V
DD
C
C
SIGNAL
GENERATOR
Lx OR Rx
SEL
Lx or Rx
L, R
0V OR V
DD
SEL
IMPEDANCE
ANALYZER
0V OR V
DD
L, R
Lx or Rx
MUTE
L, R
ANALYZER
NC
GND
MUTE
GND
R
L
Repeat test for all switches.
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 7. CAPACITANCE TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT
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ISL54405
Sound Card AC Coupled Application Block Diagrams
FLOAT
3.3V
5V_Supply
VDD
ISL54405
DIR_SEL
SOFT-START
CAPACITOR
LOGIC
AND
CLICK/POP
CONTROL
CAP_SS
AC/DC
MUTE
LOGIC
0.1µF
SEL
µ-CONTROLLER
L1
L
L1
L2
FRONT PANEL
L
LINE OUT
OR
AUDIO
R1
HEADPHONE
JACK
CODEC
R1
R2
R
R
L2
R2
BACK PANEL
LINE OUT
OR
HEADPHONE
JACK
GND
FLOAT
3.3V
5V_Supply
VDD
ISL54405
DIR_SEL
SOFT-START
CAPACITOR
LOGIC
AND
CLICK/POP
CONTROL
CAP_SS
AC/DC
MUTE
LOGIC
0.1µF
SEL
µ-CONTROLLER
L
L1
R1
L1
L2
L
FRONT PANEL
AUDIO
LINE OUT
OR
CODEC
R1
R2
HEADPHONE
JACK
R
R
L2
R2
AUDIO
GND
CODEC
The ISL54405 has special circuitry to eliminate click and pops
in the speakers during power-up and power-down of the audio
CODEC drivers, during removal and insertion of headphones,
and while switching between sources and loads.
Detailed Description
The ISL54405 is a single supply, bidirectional, dual single
pole/double throw (SPDT) ultra low distortion, high
OFF-Isolation analog switch. It was designed to operate from
either a 3.3V or 5V single supply. When operated with a 3.3V or
The ISL54405 was designed primarily for consumer and
professional audio switching applications such as computer
sound cards and home theater products. The “Sound Card AC
Coupled Application Block Diagrams” show two typical sound
card applications. In the upper block diagram the ISL54405 is
being used to route a single stereo source to either the front or
back panel line outs of the computer sound card. In the lower
block diagram the ISL54405 is being used to multiplex two stereo
sources to a single line out of the computer sound card.
5V single supply, the switches can accommodate ±2.83V
PEAK
(2V
) ground reference analog signals. The switch r
RMS
ON
flatness across this range is extremely small resulting in
excellent THD+N performance (0.0006% with 20k load and
0.0014% with 32 load at 707mV ). The T-Type
RMS
configuration of the switch cells prevents signals from getting
through to the output when a switch is in the OFF-state
providing for superior mute performance (>120dB) in audio
applications.
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ISL54405
SPDT Switch Cell Architecture and
Performance Characteristics
Supply Voltage, Signal Amplitude, and
Grounding
The normally open (L , R ) and normally closed (L , R ) of the
The power supply connected at VDD or the 5V_Supply pin
provides power to the ISL54405 part. The ISL54405 is a single
supply device that was designed to be operated with a 3.3V
±10% DC supply connected at the VDD pin or a 5V ±10% DC
supply connected at the 5V_Supply pin.
2
2
1
1
SPDT switches are T-Type switches that have a typical r of
ON
1.9and an off-isolation of >120dB. The low on-resistance
(1.9and r flatness (0.003) provide very low insertion loss
ON
and minimal distortion to applications that require hi-fidelity
signal reproduction.
It was specifically designed to accept ground referenced
The SPDT switch cells have internal charge pumps that allow
for signals to swing below ground. They were specifically
designed to pass audio signals that are ground referenced and
2V
(± 2.828V
) audio signals at its signal pins while
RMS
PEAK
driving either 10k/20k receiver loads or 32 headphone
loads.
have a swing of ± 2.828V
(receiver) or 32 (headphone) loads.
while driving either 10k/20k
PEAK
When using the part in a 3.3V application the 5V_Supply pin
should be left floating. A 0.1µF decoupling capacitor should be
connected from the VDD pin to ground to minimize power
supply noise and transients. This capacitor should be located
as close to the pin as possible.
Each switch cell incorporates special circuitry to gradually
decrease the switch resistance when transitioning from the
OFF-state (high impedance) to the ON-state (1.9). The
gradual decrease in the switch resistance provides for a slow
ramp of the voltage at the load side of the switch which helps
to eliminate clicks and pops in the speaker by suppressing the
transient during switching events. The output voltage ramp
time is determined by the capacitor value of the soft-start
capacitor connected at the CAP_SS pin. With a 0.1µF ceramic
chip capacitor the ramp time is approximately 4.6V/s. The
slow ramping of the signal at the output can be disabled by
floating the CAP_SS pin.
The part also has a 5V supply pin (5V_Supply) to allow it to be
used in 5V ±10% applications. Special circuitry within the
device converts the 5V, connected at the 5V_Supply pin, too
3.3V to properly power the internal circuitry of the device.
When using the part in a 5V application the VDD pin should be
left floating. A 0.1µF decoupling capacitor should be
connected from the 5V_Supply pin to ground to minimize
power supply noise. This capacitor should be located as close
to the pin as possible.
In addition to the slow ramp feature (soft-start feature) of the
in line switches, the part has special click and pop (C/P) shunt
circuitry at each of the signal pins (L, R, L , L , R , and R ). A
pin’s C/P shunt circuitry is activated or deactivated depending
on the logic levels applied at the AC/DC and DIR_SEL control
pins. This shunt circuitry serves two functions:
Grounding of the ISL54405 should follow a star configuration
(see Figure 8). All grounds of the IC should be directly
connected to the power supply ground return without
cascading to other grounds. This configuration isolates shunt
currents of the Click and Pop transients from the IC ground
and optimizes device performance.
1
2
1
2
1. In an AC coupled application they are activated and
directed to the source side of the switch to suppress or
eliminate click/pop noise in the speaker load when
powering up or down of the audio CODEC drivers.
+3.3V
VDD
2. For superior muting the C/P shunt circuitry is activated and
directed to the load side of the switch which gives >120dB
of OFF-Isolation when driving a 10k/20k receiver load
with an audio signal in the range of 20Hz to 22kHz.
MUTE
GND2
SEL
LOGIC
CONTROL
GND3
AC/DC
0.1µF
DIR_SEL
If the AC/DC pin is driven LOW, all C/P shunt circuitry at all the
signal pins (L, R, L1, R1, L2, and R2) are deactivated and not
operable.
L1
L2
L
R
R1
R2
If the AC/DC pin is driven HIGH, then the logic at the DIR_SEL
pin will determine whether the L and R (COM) C/P shunt
circuitry is activated or the L1, L2, R1, and R2 (NOx, NCx) C/P
shunt circuitry is activated. When the DIR_SEL is driven LOW,
the L1, R1, L2, R2 C/P shunt circuitry will be activated while
the L and R C/P shunt circuitry will be deactivated. When the
DIR_SEL is driven HIGH, the L and R C/P shunt circuitry will be
activated while the L1, R1, L2, R2 C/P shunt circuitry will be
deactivated. Note: Shunt circuitry that is activated will be
turned ON when a switch cell is turned OFF and will be OFF
when a switch cell is turned ON.
ISL54405
GND1
FIGURE 8. STAR GROUNDING CONFIGURATION
Mute Operation
When the MUTE logic pin is driven HIGH the part will go into the
mute state. In the mute state all switches of the SPDTs are
open while the T-Shunt switches are closed. In addition any
activated click and pop shunt circuitry at the signal pins is
turned on. See “Logic Control” on page 10 for more details.
to the ON-state in the following sequence:
MUTE TO ON
When the MUTE pin is driven LOW, the ISL54405 will transition
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ISL54405
1. All active shunt switches turn off quickly.
determine the location of the C/P (click/pop) shunt circuitry
and if it will be active or not. See “Truth Table” on page 3.
2. The resistance of the switches selected by the SEL pin will
gradually decrease in resistance. They will decrease from
their high OFF-resistance to their ON-resistance of 1.9.
This gradual decrease in resistance will allow for the
voltage at the load to increase gradually. The voltage ramp
rate at the load is determined by the value of the capacitor
connected at the CAP_SS pin, see Figures 28 and 29 on
page 16.
The ISL54405 logic is 1.8V CMOS compatible (Low 0.5V and
High 1.4V) over a supply range of 3.0V to 3.6V at the VDD pin
or 4.5V to 5.5V at the 5V_Supply pin. This allows control via
1.8V or 3V µ-controller.
SEL, MUTE CONTROL PINS
The state of the SPDT switches of the ISL54405 device is
determined by the voltage at the MUTE pin and the SEL pin.
Table 1 indicates how the signal ramp rate at the load changes
as you change the CAP_SS capacitor value. It also shows how
the mute turn-on time is affected.
The SEL control pin is only active when MUTE is logic “0”. The
MUTE has an internal pull-up resistor to the internal 3.3V
supply rail and can be driven HIGH or tri-stated (floated) by the
µ-processor.
TABLE 1. SIGNAL RAMP-RATE LOAD CHANGE WITH CAP SS
CAPACITOR VALUE
No Capacitor
0.05µF
RAMP RATE
6250V/s
10.3V/s
TURN-ON TIME
65µs
These pins are 1.8V logic compatible. When powering the part
by the VDD pin the logic voltage can be as high as the V
DD
30ms
voltage which is typically 3.3V. When powering the part by the
5V_Supply pin the logic voltage can be as high as the
5V_Supply voltage which is typically 5V.
0.1µF
4.6V/s
58ms
Logic Levels:
ON TO MUTE
MUTE = Logic “0” (Low) when 0.5V
MUTE = Logic “1” (High) when 1.4V or floating
SEL = Logic “0” (Low) when 0.5V
SEL = Logic “1” (High) when 1.4V
When the MUTE pin is driven HIGH, the switches will turn off
quickly (50ns) and the active shunt switches will turn on
quickly. Note: There is no gradual ramping of the switch
resistance in this direction.
AC/DC AND DIR_SEL CONTROL PINS
OFF-ISOLATION IN THE MUTE STATE
The ISL54405 contains C/P (click/pop) shunt circuitry on its
COM pins (L, R) and on its signal pins (L1, R1, L2, R2). The
activation of this circuitry and whether it is located on the COM
or signal side of the switch is determined by the logic levels
applied at the AC/DC and DIR_SEL pins. The DIR_SEL control
pin is only active when AC/DC is logic “1”. Note: Any activated
C/P shunt circuitry is ON when in the mute state (MUTE = Logic
“1”) and OFF in the audio state (MUTE = Logic “0”).
When in the mute state, the level of OFF-Isolation across the
audio band is dependent on the signal amplitude, external
loading, and location of the activated C/P (click/pop) shunt
circuitry. During muting, the logic of the ISL54405 can be
configured to activate the C/P shunt circuitry on the load side
of the switch or on the source side of the switch, or deactivated
on both sides of the switch.
With a 0.707V
RMS
signal driving a 32 headphone load, the
When AC/DC is logic “0”, all of the C/P shunt circuitry on both
sides of the switch is deactivated and not operable.
location of the C/P shunt circuitry has little effect on the
off-isolation performance (>120dB of off-isolation in all
configurations), see Figure 12 on page 13.
When AC/DC is logic “1” then the DIR_SEL logic level
determines whether the shunt circuitry will be activated on the
COM side of the switch or on the signal side of the switch.
When DIR_SEL = Logic “1” the C/P shunts on the COM side
(L,R) are activated and inoperable on the signal side (L1, R1,
L2, R2) of the switch. When DIR_SEL = Logic “0” the C/P
shunts are activated on the signal side (L1, R1, L2, R2) and
inoperable on the COM side (L, R).
With a 2V
RMS
signal driving a 20k amplifier load, the best
OFF-Isolation is achieved by placing the C/P shunt circuitry on
the load side of the switch (>120dB across the audio band).
The OFF-Isolation decreases when placing the C/P shunt
circuitry on the source side of the switch (>85dB across the
audio band), see Figure 11 on page 13.
Note: For AC coupled applications when powering up or down
of the audio drivers the C/P shunts should be activated on the
source side of the switch. See “Click and Pop Operation” on
page 11.
Logic Levels:
AC/DC, DIR_SEL = Logic “0” (Low) when 0.5V
AC/DC, DIR_SEL = Logic “1” (High) when 1.4V or Floating.
The AC/DC and DIR_SEL have internal pull-up resistors to the
internal 3.3V supply rail and can be driven HIGH or tri-stated
(floated by the µ-processor). They should be driven to ground
for a logic “0” (Low). Note: For 5V applications, the AC/DC and
DIR_SEL pins should never be driven to the external 5V rail.
They need to be driven with 1.8V logic or 3V logic circuit.
When using the switch for muting of the audio signal the C/P
shunt circuitry should be deactivated on the source side of the
switch and directed to the load side of the switch for best
possible OFF-Isolation.
Logic Control
The ISL54405 has four logic control pins; the AC/DC, DIR_SEL,
MUTE, and SEL. The MUTE and SEL control pins determine the
state of the switches. The AC/DC and DIR_SEL control pins
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ISL54405
and a high impedance load, (such as the impedance of a 20k
to 100k preamplifier stage) a DC offset voltage will be
present on the signal line in the range of 35mV to 135mV.
AC Coupled or DC Coupled Operation
The Audio CODEC drivers can be directly coupled to the
ISL54405 when the audio signals from the drivers are ground
referenced or do not have a significant DC offset voltage,
<50mV. Otherwise, the signal should be AC coupled to the
ISL54405 part.
When the switch is turned off, this offset voltage gets pulled to
ground. During switching, this change in the offset voltage can
cause a click and pop noise to be heard in the downstream
speaker.
CLICK AND POP OPERATION
Placing a 1kresistor from the output of the switch to ground
will lower the offset voltage to around 1.5mV, thereby
effectively eliminating the click and pop noise. The 1k
resistor is small enough to reduce the voltage offset
significantly while not increasing power dissipation
dramatically. Power consumption will need to be considered
when using a smaller impedance under this scenario.
The ISL54405 has special circuitry to eliminate click and pops
in the speakers during power-up and power-down of the Audio
CODEC Drivers and during removal and insertion of
headphones.
A different click and pop scheme is required depending on
whether the audio CODEC drivers are AC coupled or DC
coupled to the inputs of the ISL54405 part.
When connected to a low impedance load such as
AC COUPLED CLICK AND POP OPERATION
headphones (32), the current added to the signal line results
in a minimal DC offset voltage on the signal line and does not
cause click and pop noise when the switch is turned off.
Single supply audio drivers have their signal biased at a DC
offset voltage, usually at 1/2 the DC supply voltage of the
driver. As this DC bias voltage comes up or goes down during
power up or down of the driver a transient can be coupled into
the speaker load through the DC blocking capacitor (see the
“Sound Card AC Coupled Application Block Diagrams” on
page 8).
DC COUPLED CLICK AND POP OPERATION
The ISL54405 can pass ground referenced audio signals which
allows it to be directly connected to audio drivers that output
ground referenced audio signals, eliminating the need for a DC
blocking capacitor.
When a driver is off and suddenly turned on, the rapidly
changing DC bias voltage at the output of the driver will cause
an equal voltage at the input side of the switch due to the fact
that the voltage across the blocking capacitor cannot change
instantly. If the switch is in audio mode or there is no low
impedance path to discharge the capacitor voltage at the input
of the switch, before turning on the switch, a transient
discharge will occur in the speaker, generating a click and pop
noise.
Audio drivers that swing around ground, however, do generate
some DC offset, from a few millivolts to tens of millivolts.
When switching between audio channels or muting the audio
signal, these small DC offset levels of the drivers can generate
a transient that can cause unwanted clicks and pops in the
speaker loads.
In a DC coupled application the C/P shunt resistors placed at
the source side of the switch have no effect in eliminating the
transients at the speaker loads when transitioning in and out
of the mute state or switching between channels. In fact,
having these C/P shunts active on the source side
unnecessarily increases the power consumption. So, for DC
coupled connection, the C/P shunt circuitry should not be
applied at the source (driver) side of the switch.
Proper elimination of a click/pop transient at the speaker load
while powering up or down of the audio driver requires that the
ISL54405 have its C/P shunts activated on the source side of
the switch and then placed in mute mode. This allows the
transient generated by the audio drivers to be discharged
through the click and pop shunt circuitry.
For DC coupled applications the ISL54405 has a special
soft-start feature that slowly ramps the DC offset voltage from
the audio driver to the speaker load when turning on a switch
channel. The ramp rate at the load is determined by the
capacitor value connected at the CAP_SS pin.
Once the driver DC bias has reached VDD/2 and the transient
on the switch side of the DC blocking capacitor has been
discharged to ground through the C/P shunt circuitry, the
switches can be turned on and connected through to the
speaker loads without generating an undesirable click/pop in
the speakers.
Lab experimentation has shown that if you can slow the
voltage ramp rate at the speaker to <10V/s, you can eliminate
click/pop noise in a speaker. A soft-start capacitor value of
0.1µF provides for 4.5V/s ramp rate and is recommended. See
Figures 28 and 29 on page 16. See “MUTE to ON” on page 9
for more detail of how soft-start works.
With a typical DC blocking capacitor of 220µF and the C/P
shunt circuitry designed to have a resistance of 40allowing
a 100ms wait time to discharge the transient before placing
the switch in the audio mode will prevent the transient from
getting through to the speaker load. See Figures 26 and 27 on
page 15.
Supply Sequencing and Overvoltage
Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
CLICK AND POP ELIMINATION WHEN CONNECTED TO
HIGH IMPEDANCE SOURCE AND LOAD
By design, in order to flatten the RON resistance of the switch
across the signal range (±3V) a current gets added to the
signal path. When the ISL54405 part is connected to a high
impedance source (i.e. AC coupled to the input of the switch)
ESD protection diodes or diode stacks from the pin to V and
DD
to GND (see Figure 9). To prevent forward biasing these diodes,
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ISL54405
.
V
must be applied before any input signals, and the signal
DD
voltages must remain between V and -3V and the logic
DD
voltage must remain between V and ground.
OPTIONAL
SCHOTTKY
DIODE
DD
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin goes below ground by
V
DD
OPTIONAL
PROTECTION
RESISTOR
LOGIC
INPUT
V
V
NX
COM
more than -3V or above the V rail and the logic pin goes
DD
below ground or above the V rail.
DD
GND
Logic inputs can be protected by adding a 1k resistor in
series with the logic input (see Figure 9). The resistor limits the
input current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
OPTIONAL
SCHOTTKY
DIODE
FIGURE 9. OVERVOLTAGE PROTECTION
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the purpose
High-Frequency Performance
In 50 systems, the ISL54405 has a -3dB bandwidth of
230MHz (see Figure 30). The frequency response is very
consistent over varying analog signal levels.
of using a low r switch. Connecting Schottky diodes to the
ON
signal pins, as shown in Figure 9 will shunt the fault current to
the supply or to ground thereby protecting the switch. These
Schottky diodes must be sized to handle the expected fault
current and to clamp when the voltage reaches the
overvoltage limit.
An OFF-switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feed-through from a switch’s input to its output. OFF-Isolation
is the resistance to this feed-through, while crosstalk indicates
the amount of feed-through from one switch to another.
Figure 31 details the high OFF-Isolation and crosstalk rejection
provided by this part. At 1MHz, Off-Isolation is about 100dB in
50 systems, decreasing approximately 20dB per decade as
frequency increases. Higher load impedances decrease
OFF-Isolation and crosstalk rejection due to the voltage divider
action of the switch off impedance and the load impedance.
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ISL54405
Typical Performance Curves
T
= +25°C, Unless Otherwise Specified
A
80
90
3.0
V
R
= 3.3V OR V_Supply = 5V
DD
V
= 3.3V
C/P SHUNT ON SIGNAL SIDE
DD
= 20k
LOAD
VSIGNAL = 2V
+85°C
I
= 80mA
COM
RMS
2.5
2.0
1.5
1.0
0.5
0
100
110
120
130
140
150
160
170
+25°C
-40°C
NO C/P SHUNT
C/P SHUNT ON LOAD SIDE
-3
-2
-1
0
1
2
3
20
50
100 200
500 1k
2k
5k
10k 20k
V
(V)
COM
FREQUENCY (Hz)
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 11. OFF-ISOLATION, 2V
SIGNAL, 20kLOAD
RMS
80
90
-80
-85
-90
V
= 3.3V OR V_Supply = 5V
DD
V
= 3.3V
DD
R
= 32
LOAD
R
= 20k
LOAD
VSIGNAL = 2V
-95
VSIGNAL = 0.707V
RMS
100
110
120
130
140
150
160
170
180
RMS
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-155
-160
-165
-170
C/P SHUNT ON SIGNAL SIDE
NO C/P SHUNT
C/P SHUNT ON LOAD SIDE
20
50
100 200
500 1k
2k
5k
10k 20k
20
50
100 200
500 1k
2k
5k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 12. OFF-ISOLATION, 0.707V
SIGNAL, 32LOAD
FIGURE 13. CHANNEL-TO-CHANNEL CROSSTALK
RMS
-80
-85
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0.000
V
= 3.3V
DD
V
= 3.3V
DD
-90
-95
R
= 20k
LOAD
R
= 32
LOAD
VSIGNAL = 0.707V
V
= 2V
RMS
SIGNAL
RMS
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
20
50 100 200
500 1k 2k
5k 10k 20k
20
100
1k
FREQUENCY (Hz)
10k 20k
FREQUENCY (Hz)
FIGURE 14. CHANNEL-TO-CHANNEL CROSSTALK
FIGURE 15. INSERTION LOSS vs FREQUENCY
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ISL54405
Typical Performance Curves
T
= +25°C, Unless Otherwise Specified (Continued)
A
0.020
0.015
0.010
0.005
0
0.05
V
= 3.3V
DD
V
= 3.3V
DD
R
= 20k
0.04
0.03
LOAD
R
= 20k
LOAD
VSIGNAL = 2V
VSIGNAL = 2V
RMS
RELATIVE TO 1kHz
RMS
0.02
L2 AND R2
L1 AND R1
0.01
0.00
-0.01
-0.02
-0.03
-0.04
-0.05
-0.005
-0.010
-0.015
-0.020
20
100
1k
FREQUENCY (Hz)
10k 20k
20
100
1k
10k 20k
FREQUENCY (Hz)
FIGURE 16. GAIN vs FREQUENCY
FIGURE 17. STEREO IMBALANCE vs FREQUENCY
-90
0.0020
V
DD
= 3.3V
= 32
V
R
= 3.3V
= 32
DD
-92
-94
R
LOAD
LOAD
A-WEIGHTED FILTER
A-WEIGHTED FILTER
-96
0.0010
0.0009
0.0008
-98
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
0.0007
0.0006
0.0005
1V
P-P
1V
P-P
0.0004
510mV
P-P
0.0003
0.0002
510mV
P-P
0.0001
20
50
100 200
500
1k
2k
5k
10k 20k
20
50 100 200
500
1k
2k
5k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 18. THD+N vs SIGNAL LEVELS vs FREQUENCY
FIGURE 19. THD+N vs SIGNAL LEVELS vs FREQUENCY
0.0010
0.0009
0.0008
-100
V
R
= 3.3V
V
= 3.3V
-101
-102
-103
-104
-105
-106
-107
-108
-109
-110
-111
-112
-113
-114
-115
-116
-117
-118
-119
-120
DD
DD
= 20k
LOAD
A-WEIGHTED FILTER
R
= 20k
LOAD
A-WEIGHTED FILTER
0.0007
0.0006
2V
RMS
0.0005
0.0004
2V
RMS
1.9V
0.0003
0.0002
RMS
1.9V
RMS
1.8V
1.5V
1.8V
RMS
RMS
1.5V
RMS
RMS
0.0001
20
50
100 200
500 1k
2k
5k
10k 20k
20
50
100 200
500 1k
2k
5k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 20. THD+N vs SIGNAL LEVELS vs FREQUENCY
FIGURE 21. THD+N vs SIGNAL LEVELS vs FREQUENCY
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Typical Performance Curves
T
= +25°C, Unless Otherwise Specified (Continued)
A
0.00100
0.00095
0.00090
0.00085
0.00080
0.00075
0.00070
0.00065
0.00060
0.00055
0.00050
0.00045
0.00040
0.00035
0.00030
0.00025
0.00020
0.00015
0.00010
-100
V
R
= 3.3V
= 20k
V
R
= 3.3V
= 20k
DD
-101
-102
-103
-104
-105
-106
-107
-108
-109
-110
-111
-112
-113
-114
-115
-116
-117
-118
-119
-120
DD
2V
RMS
LOAD
10Hz TO 30k FILTER
LOAD
10Hz to 30k FILTER
1.9V
RMS
2V
RMS
1.7V
TO 1.8V
RMS
RMS
1.9V
RMS
1.7V
TO 1.8V
RMS
RMS
1.6V
RMS
1.5V
RMS
1.6V
1.5V
RMS
RMS
20
50
100 200
500 1k
2k
5k 10k 20k
20
50
100 200
500 1k
2k
5k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 22. THD+N vs SIGNAL LEVELS vs FREQUENCY
FIGURE 23. THD+N vs SIGNAL LEVELS vs FREQUENCY
-60
-65
-50
-55
-60
-65
-70
-75
-80
-85
-90
5V_Supply = 5VDC + 100MV
SIGNAL
V
= 3.3VDC + 100mV
SIGNAL
RMS
DD
RMS
-70
R
= 20k OR 32
R
= 20k OR 32
LOAD
INPUTS GROUNDED
LOAD
-75
INPUTS GROUNDED
-80
-85
-90
-95
AUDIO MODE
-100
-105
-110
-115
-120
-125
-130
-135
-140
-95
-100
-105
-110
-115
-120
-125
-130
-135
-140
AUDIO MODE
MUTE MODE
(C/P SHUNT ON LOADSIDE)
MUTE MODE
(C/P SHUNT ON LOADSIDE)
20
50 100 200
500 1k
2k
5k 10k 20k 40k
20
50 100 200
500 1k 2k
FREQUENCY (Hz)
5k 10k 20k 40k
FREQUENCY (Hz)
FIGURE 24. PSRR vs FREQUENCY
FIGURE 25. PSRR vs FREQUENCY
7
6
7
6
2V/DIV
2V/DIV
2V/DIV
2V/DIV
MUTE
VDD/2
MUTE
VDD/2
5
5
4
4
3
3
2
2
1
1
0
0
L
200mV/DIV
L
200mV/DIV
IN
IN
-1
-2
-3
-4
-5
-6
-7
-1
-2
-3
-4
-5
-6
-7
L
200mV/DIV
OUT
L
200mV/DIV
OUT
-0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1
0
0.1 0.2 0.3 0.4
-0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1
0
0.1 0.2 0.3 0.4
TIME (s) 100ms/DIV
TIME (s) 100ms/DIV
FIGURE 26. 20k AC COUPLED CLICK/POP REDUCTION
FIGURE 27. 32 AC COUPLED CLICK/POP REDUCTION
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Typical Performance Curves
T
= +25°C, Unless Otherwise Specified (Continued)
A
80
80
60
40
20
0
LEFT INPUT
LEFT INPUT
60
40
4.6V/s
10.3V/s
10.3V/s
LEFT OUTPUT
RIGHT OUTPUT
LEFT OUTPUT
20
0
RIGHT OUTPUT
-20
-40
-60
-80
-20
-40
-60
-80
4.6V/s
RIGHT INPUT
= 3.3V
RIGHT INPUT
= 3.3V
V
DD
V
DD
CAP_SS = 0.05µF
-100 -80 -60 -40 -20
TIME (ms)
CAP_SS = 0.1µF
-100 -80 -60 -40 -20
TIME (ms)
0
20
40
60
80
100
0
20
40
60
80 100
FIGURE 29. SOFT-START (0.05µF) CLICK/POP REDUCTION
FIGURE 28. SOFT-START (0.1µF) CLICK/POP REDUCTION
0
0
V
R
= 3.3V
= 50
DD
LOAD
V
R
= 3.3V
= 50
DD
LOAD
0
-1
-2
-3
20
-20
40
-40
CROSSTALK
60
-60
80
-80
ISOLATION
100
120
-100
-120
1k
10k
100k
1M
10M
100M 500M
1
10
100
300
FREQUENCY (Hz)
FREQUENCY (MHz)
FIGURE 31. CROSSTALK AND OFF-ISOLATION
FIGURE 30. FREQUENCY RESPONSE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
3376
PROCESS:
Submicron CMOS
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ISL54405
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
FN6699.2
CHANGE
May 6, 2014
Updated entire datasheet to new format.
Updated Ordering Information on page 3.
Updated Θ and Θ for the TSSOP package on page 4.
JA JC
Added section, “Click and POP Elimination When Connected to High Impedance Source and Load” on page 11
Replaced the PODs with the latest revision.
June 5, 2008
May 15, 2008
FN6699.1
FN6699.0
Updated typo in Figure 28 on page 16 - changed "CAP_SS = 0.5µF" to be "CAP_SS = 0.05µF" to match value in
title.
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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ISL54405
Package Outline Drawing
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
5.00 ±0.10
SEE DETAIL "X"
9
16
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
8
B
0.09-0.20
0.65
TOP VIEW
END VIEW
1.00 REF
-
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25 +0.05/-0.06
0.25
5
0.10
C B A
M
0.10 C
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
(5.65)
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
(0.65 TYP)
(0.35 TYP)
6. Dimension in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
7. Conforms to JEDEC MO-153.
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ISL54405
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
L16.2.6x1.8A
D
A
B
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
6
INDEX AREA
SYMBOL
MIN
0.45
NOMINAL
MAX
0.55
NOTES
N
E
A
A1
A3
b
0.50
-
2X
0.10 C
1 2
-
-
0.05
-
2X
0.10 C
0.127 REF
-
TOP VIEW
0.15
2.55
1.75
0.20
0.25
2.65
1.85
5
D
2.60
-
0.10 C
E
1.80
-
C
A
0.05 C
SEATING PLANE
e
0.40 BSC
-
K
0.15
0.35
0.45
-
0.40
0.50
16
4
-
0.45
0.55
-
A1
L
-
SIDE VIEW
L1
N
-
2
e
Nd
Ne
3
PIN #1 ID
L1
K
1 2
4
3
NX L
0
-
12
4
5
NX b
16X
Rev. 6 1/14
(DATUM B)
(DATUM A)
NOTES:
0.10 M C A B
0.05 M C
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
BOTTOM VIEW
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
C
L
(A1)
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX (b)
5
L
e
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
SECTION "C-C"
TERMINAL TIP
C C
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
3.00
1.80
1.40
0.90
1.40
2.20
0.40
0.20
0.40
0.20
0.50
10
LAND PATTERN
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ISL54405
Package Outline Drawing
L16.3x3A
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 7/11
4X 1.5
16X 0.50
3.00
A
6
B
PIN #1
INDEX AREA
13
16
6
PIN 1
INDEX AREA
1
12
1 .50 ± 0 . 15
9
4
(4X)
0.15
8
5
0.10 M C A B
+ 0.07
- 0.05
TOP VIEW
4
16X 0.23
16X 0.40 ± 0.10
BOTTOM VIEW
SEE DETAIL "X"
C
0.10 C
BASE PLANE
0 . 75 ± 0.05
( 2. 80 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
(
1. 50 )
( 12X 0 . 5 )
( 16X 0 . 23 )
( 16X 0 . 60)
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
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