ISL55111 [RENESAS]
Dual, High Speed MOSFET Driver;
| 型号： | ISL55111 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Dual, High Speed MOSFET Driver |
| 文件： | 总18页 (文件大小：815K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL55110, ISL55111
Dual, High Speed MOSFET Driver
FN6228
Rev 8.00
January 29, 2015
The ISL55110 and ISL55111 are dual high speed MOSFET
drivers intended for applications requiring accurate pulse
generation and buffering. Target applications include
ultrasound, CCD imaging, piezoelectric distance sensing and
clock generation circuits.
Features
• 5V to 12V pulse amplitude
• High current drive 3.5A
• 6ns minimum pulse width
With a wide output voltage range and low ON-resistance, these
devices can drive a variety of resistive and capacitive loads
with fast rise and fall times, allowing high-speed operation
with low skew, as required in large CCD array imaging
applications.
• 1.5ns rise and fall times, 100pF load
• Low skew
• 3.3V and 5V logic compatible
• In-phase (ISL55110) and anti-phase outputs (ISL55111)
• Small QFN and TSSOP packaging
• Low quiescent current
The ISL55110, ISL55111 are compatible with 3.3V and 5V
logic families and incorporate tightly controlled input
thresholds to minimize the effect of input rise time on output
pulse width. The ISL55110 has a pair of in-phase drivers while
the ISL55111 has two drivers operating in anti-phase.
• Pb-free (RoHS compliant)
Applications
• Ultrasound MOSFET driver
• CCD array horizontal driver
• Clock driver circuits
ISL55110 and ISL55111 have a power-down mode for low
power consumption during equipment standby times, making
it ideal for portable products.
The ISL55110 and ISL55111 are available in 16 Ld Exposed
pad QFN packaging and 8 Ld TSSOP. Both devices are
specified for operation over the full -40°C to +85°C
temperature range.
Related Literature
• AN1283, “ISL55110_11EVAL1Z, ISL55110_11EVAL2Z
Evaluation Board User's Manual”
ISL55110 AND ISL55111 DUAL DRIVER
o
VDD
VH
o
OA
o
IN-A
o
o
ENABLE-QFN*
OB
o
IN-B
**
o
o
GND
o
PD
*ENABLE AVAILABLE IN QFN PACKAGE ONLY
**ISL55111 IN-B IS INVERTING
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
FN6228 Rev 8.00
January 29, 2015
Page 1 of 18
ISL55110, ISL55111
Pin Configurations
ISL55110
(16 LD QFN)
TOP VIEW
ISL55111
(16 LD QFN)
TOP VIEW
16 15 14 13
16 15 14 13
OB
VDD
ENABLE
PD
12
11
10
9
1
2
3
4
OB
VDD
1
12
11
10
9
GND
VH
GND
VH
ENABLE
2
EP
EP
PD
3
OA
IN-B
OA
IN-B
4
5
6
7
8
5
6
7
8
ISL55110
(8 LD TSSOP)
TOP VIEW
ISL55111
(8 LD TSSOP)
TOP VIEW
VDD
PD
1
2
3
4
8
7
6
OB
VDD
1
2
3
4
8 OB
GND
VH
PD
IN-B
IN-A
7
6
GND
VH
IN-B
IN-A
5
OA
5
OA
Pin Descriptions
16 LD QFN
8 LD TSSOP
PIN
VDD
VH
FUNCTION
1
1
6
7
Logic power.
10
11
Driver high rail supply.
GND
Ground, return for both VH rail and VDD logic supply. This is also the potential of the QFN’s exposed
pad (EP).
3
2
2
-
PD
Power-down. Active logic high places part in power-down mode.
ENABLE
QFN packages only. When the ENABLE pin is low, the device will operate normally (outputs controlled
by the inputs). When the ENABLE pin is tied high, the output will be tri-stated. In other words, it will
act as if it is open or floating regardless of what is on the IN-x pins. This provides high-speed enable
control over the driver outputs.
5
4
4
3
5
8
-
IN-A
IN-B, IN-B
OA
Logic level input that drives OA to VH rail or ground. Not inverted.
Logic level input that drives OB to VH rail or ground. Not inverted on ISL55110, inverted on ISL55111.
Driver output related to IN-A.
9
12
OB
Driver output related to IN-B.
6, 7, 8, 13, 14,
15, 16
NC
No internal connection.
EP
-
EP
Exposed thermal pad. Connect to GND and follow good thermal pad layout guidelines.
FN6228 Rev 8.00
January 29, 2015
Page 2 of 18
ISL55110, ISL55111
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL55110IRZ
55110IRZ
-40 to +85
-40 to +85
-40 to +85
-40 to +85
16 Ld QFN
L16.4x4A
ISL55110IVZ
ISL55111IRZ
55110 IVZ
8 Ld TSSOP
16 Ld QFN
8 Ld TSSOP
M8.173
L16.4x4A
M8.173
55111IRZ
ISL55111IVZ
55111 IVZ
ISL55110EVAL1Z
ISL55110EVAL2Z
ISL55111EVAL1Z
ISL55111EVAL2Z
NOTES:
TSSOP Evaluation Board
QFN Evaluation Board
TSSOP Evaluation Board
QFN Evaluation Board
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL55110, ISL55111. For more information on MSL please see techbrief
TB363.
FN6228 Rev 8.00
January 29, 2015
Page 3 of 18
ISL55110, ISL55111
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
V
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.0V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Thermal Resistance
16 Ld (4x4) QFN Package (Notes 5, 6) . . .
8 Ld TSSOP Package (Notes 4, 7) . . . . . . .
(°C/W)
45
140
JC
(°C/W)
3.0
46
H
JA
DD
VIN-A, VIN-B, PD, ENABLE . . . . . . . . . . . . . . . . (GND - 0.5V) to (V + 0.5V)
DD
OA, OB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.5) to (VH + 0.5V)
Maximum Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA
ESD Rating
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kV
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Drive Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 13.2V
H
Logic Supply Voltage (V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
DD)
Ambient Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
A
Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
J
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
5. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
6. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
7. For , the “case temp” location is taken at the package top center.
JC
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise
noted, all tests are at the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
DC Electrical Specifications
V
= +12V, V = 2.7V to 5.5V, T = +25°C, unless otherwise specified.
H
DD
A
MIN
MAX
PARAMETER
DESCRIPTION
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNITS
LOGIC CHARACTERISTICS
VIX_LH
VIX_HL
VHYS
VIH
Logic Input Threshold - Low-to-High
Logic Input Threshold - High-to-Low
Logic Input Hysteresis
l
l
= 1µA: VIN-A, VIN-B
= 1µA: VIN-A, VIN-B
1.32
1.12
1.42
1.22
0.2
1.52
1.32
V
V
IH
IL
VIN-A, VIN-B
V
Logic Input High Threshold
Logic Input Low Threshold
Logic Input High Threshold
Logic Input Low Threshold
Input Current Logic High
Input Current Logic Low
PD
2.0
0
VDD
0.8
VDD
0.8
20
V
VIL
PD
V
VIH
ENABLE - QFN only
ENABLE - QFN only
VIN-A, VIN-B = VDD
VIN-A, VIN-B = 0V
PD = VDD
2.0
0
V
VIL
V
IIX_H
IIX_L
II_H
10
10
10
10
nA
nA
nA
nA
µA
nA
20
Input Current Logic High
Input Current Logic Low
20
II_L
PD = 0V
15
II_H
Input Current Logic High
Input Current Logic Low
ENABLE = VDD (QFN only)
ENABLE = 0V (QFN only)
12
II_L
-25
DRIVER CHARACTERISTICS
r
Driver Output Resistance
Driver Output DC Current (>2s)
Peak Output Current
OA, OB
3
6
Ω
mA
A
DS
I
100
3.5
DC
I
Design Intent; verified via
simulation.
AC
VOH to VOL
Driver Output Swing Range
OA or OB = “1”, voltage
referenced to GND
3
13.2
V
FN6228 Rev 8.00
January 29, 2015
Page 4 of 18
ISL55110, ISL55111
DC Electrical Specifications
V
= +12V, V = 2.7V to 5.5V, T = +25°C, unless otherwise specified. (Continued)
H
DD
A
MIN
MAX
PARAMETER
DESCRIPTION
TEST CONDITIONS
(Note 8)
TYP
4.0
(Note 8)
UNITS
SUPPLY CURRENTS
I
Logic Supply Quiescent Current
Logic Supply Power-down Current
Driver Supply Quiescent Current
Driver Supply Power-down Current
PD = Low
6.0
12
15
mA
µA
µA
µA
DD
I
PD = High
DD-PDN
IH
PD = Low, outputs unloaded
PD = High
IH_PDN
2.5
AC Electrical Specifications V = +12V, V = +3.6V, T = +25°C, unless otherwise specified.
H
DD
A
MIN
MAX
PARAMETER
DESCRIPTION
TEST CONDITIONS
(Note 8)
TYP
1.2
(Note 8)
UNITS
ns
SWITCHING CHARACTERISTICS
t
Driver Rise Time
Figure 2, OA, OB:
R
CL = 100pF/1k
10% to 90%, VOH - VOL = 12V
t
Driver Fall Time
Figure 2, OA, OB:
1.4
ns
F
CL = 100pF/1k
10% to 90%, VOH - VOL = 12V
t
Driver Rise Time
Driver Fall Time
Figure 2, OA, OB: CL = 1nF
10% to 90%, VOH - VOL = 12V
6.2
6.9
ns
ns
R
t
Figure 2, OA, OB: CL = 1nF
F
10% to 90%, VOH - VOL = 12V
tpdR
tpdF
Input to Output Propagation Delay
Input to Output Propagation Delay
Input to Output Propagation Delay
Input to Output Propagation Delay
Input to Output Propagation Delay
Input to Output Propagation Delay
Figure 3, load 100pF/1k
Figure 3, load 330pF
Figure 3, load 680pF
10.9
10.7
12.8
12.5
14.5
14.1
<0.5
ns
ns
ns
ns
ns
ns
ns
tpdR
tpdF
tpdR
tpdF
tSkewR
Channel-to-Channel tpdR Spread with Same Figure 3, All loads
Loads Both Channels
tSkewF
Channel-to-Channel tpdF Spread with Same Figure 3, All loads
Loads Both Channels
<0.5
ns
FMAX
TMIN
Maximum Operating Frequency
Minimum Pulse Width
70
6
MHz
ns
PD
Power-down to Power-on Time
650
40
ns
EN
PD
Power-on to Power-down Time
ns
DIS
t
Enable time; ENABLE switched high to low.
Disable time; ENABLE switched low to high.
40
ns
EN
t
40
ns
DIS
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN6228 Rev 8.00
January 29, 2015
Page 5 of 18
ISL55110, ISL55111
VH = 12V
+3V
INPUT
0.1µF
4.7µF
IN-X
0.4V
INPUT
INPUT RISE AND
FALL TIMES ≤2ns
OUTPUT
C
ISL55110
L
t
t
f
r
12V
IN
90%
90%
OUTPUT
0V
10%
10%
FIGURE 2. TEST CIRCUIT; OUTPUT RISE (t )/FALL (t ) TIMES
R
F
VH = 12V
+3V
INPUT
50%
50%
0.1µF
4.7µF
IN-X
IN
0.4V
tpdF
tpdR
50%
INPUT
OUTPUT
INPUT RISE AND
FALL TIMES ≤2ns
C
ISL55110
L
12V
50%
OUTPUT OA AND OB ISL55110
OUTPUT OA ISL55111
0V
12V
OUTPUT OB ISL55111
50%
50%
0V
t
R = |tpdR CHN A - tpdR CHN B|
SKEW
FIGURE 3. TEST CIRCUIT; PROPAGATION (tPD) DELAY
Typical Performance Curves (See “Typical Performance Curves Discussion” on page 11)
7.0
6.3
5.6
4.9
4.2
3.5
2.8
2.1
1.4
0.7
0.0
7.0
6.3
5.6
4.9
4.2
3.5
2.8
2.1
1.4
0.7
0.0
V
= 3.6V
= -50mA
V
= 3.6V
= +50mA
DD
DD
I
I
OUT
OUT
+85°C
+85°C
+25°C
+25°C
-40°C
11
-40°C
11
3
4
5
6
7
8
9
10
12
13
3
4
5
6
7
8
9
10
12
13
V , DRIVE RAIL (V)
V , DRIVE RAIL (V)
H
H
FIGURE 4. DRIVER r vs V VOLTAGE (SOURCING CURRENT)
ON
FIGURE 5. DRIVER r vs V VOLTAGE (SINKING CURRENT)
ON
H
H
FN6228 Rev 8.00
January 29, 2015
Page 6 of 18
ISL55110, ISL55111
Typical Performance Curves (See “Typical Performance Curves Discussion” on page 11) (Continued)
4.00
3.66
3.33
2.66
2.33
2.00
4.00
3.66
3.33
2.66
2.33
2.00
I
= +50mA
I
= -50mA
OUT
OUT
V
= 5V
H
V
= 5V
V
= 12V
V = 12V
H
H
H
2.5
3.5
4.5
5.5
2.5
3.5
4.5
5.5
V
(V)
V
(V)
DD
DD
FIGURE 6. r vs V VOLTAGE (SOURCING CURRENT)
ON DD
FIGURE 7. r vs V VOLTAGE (SINKING CURRENT)
ON DD
5.0
4.6
4.2
3.8
3.4
3.0
10
9
8
7
6
5
4
3
2
1
0
V
= 3.6V
DD
V
= 5V TO 12V
H
2.5
3.5
4.5
5.5
4
8
12
V
(V)
V , DRIVE RAIL (V)
DD
H
FIGURE 8. QUIESCENT I vs V
DD
FIGURE 9. OPERATING I vs V AT 50MHz (NO LOAD)
DD
DD
H
100
90
80
70
60
50
40
30
20
10
0
200
180
160
140
120
100
80
V
= 3.6V
V
= 3.6V
DD
DD
60
40
20
0
4
8
12
4
8
12
V , DRIVE RAIL (V)
V , DRIVE RAIL (V)
H
H
FIGURE 10. QUIESCENT I vs V
FIGURE 11. OPERATING I vs V AT 50MHz (NO LOAD)
H H
H
H
FN6228 Rev 8.00
January 29, 2015
Page 7 of 18
ISL55110, ISL55111
Typical Performance Curves (See “Typical Performance Curves Discussion” on page 11) (Continued)
15.0
13.5
12.0
10.5
9.0
7.5
6.0
4.5
3.0
1.5
0
200
180
160
140
120
100
80
V
= 5.0V
= 3.6V
H
V
DD
60
40
V
= 5.0V
= 3.6V
H
20
V
DD
0
50
66
100
124
128
50
66
100
124
128
TOGGLE FREQUENCY (MHz)
TOGGLE FREQUENCY (MHz)
FIGURE 12. I vs FREQUENCY (DUAL CHANNEL, NO LOAD)
DD
FIGURE 13. IH vs FREQUENCY (DUAL CHANNEL, NO LOAD)
1.5
1.5
1.4
1.4
-40°C
+85°C
-40°C
1.3
1.3
1.2
1.1
1.0
1.2
1.1
+85°C
1.0
2.5
3.5
4.5
5.5
2.5
3.5
4.5
5.5
V
(V)
V
(V)
DD
DD
FIGURE 14. VIH LOGIC THRESHOLDS vs V
FIGURE 15. VIL LOGIC THRESHOLDS vs V
DD
DD
10
10
9
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
1
680pF
V
= 12.0V
= 3.6V
680pF
H
V
DD
330pF
330pF
V
= 12.0V
H
V
= 3.6V
DD
0
-40
0
-40
-10
+20
+50
+85
-10
+20
+50
+85
PACKAGE TEMPERATURE (°C)
PACKAGE TEMPERATURE (°C)
FIGURE 16. t vs TEMPERATURE
FIGURE 17. t vs TEMPERATURE
F
R
FN6228 Rev 8.00
January 29, 2015
Page 8 of 18
ISL55110, ISL55111
Typical Performance Curves (See “Typical Performance Curves Discussion” on page 11) (Continued)
20
20
18
16
14
12
10
8
680pF
18
16
14
12
10
8
680pF
330pF
330pF
6
6
4
4
V
= 12.0V
= 3.6V
V
= 12.0V
= 3.6V
H
H
2
2
V
V
DD
DD
0
0
-40
-10
+20
PACKAGE TEMP (°C)
+50
+85
5.5
12
-40
-10
+20
PACKAGE TEMP (°C)
+50
+85
FIGURE 18. tpdR vs TEMPERATURE
FIGURE 19. tpdF vs TEMPERATURE
10
10
V
= 12.0V
H
9
8
7
6
5
4
3
2
9
8
7
6
5
4
3
2
1000pF
680pF
680pF
100pF/1k
1000pF
330pF
100pF/1k
330pF
1
0
2.5
1
0
2.5
V
= 12.0V
H
3.5
4.5
3.5
4.5
5.5
V
(V)
V
(V)
DD
DD
FIGURE 20. t vs V
FIGURE 21. t vs V
F DD
R
DD
12.0
12.0
10.8
9.6
8.4
7.2
6.0
4.8
3.6
2.4
1.2
0.0
100pF/1k
330pF
680pF
100pF/1k
330pF
10.8
9.6
8.4
7.2
6.0
4.8
3.6
2.4
1.2
0.0
1000pF
680pF
1000pF
V
= 3.3V
V
= 3.3V
DD
DD
3
6
9
12
3
6
9
V
(V)
V (V)
H
H
FIGURE 22. t vs V
FIGURE 23. t vs V
F H
R
H
FN6228 Rev 8.00
January 29, 2015
Page 9 of 18
ISL55110, ISL55111
Typical Performance Curves (See “Typical Performance Curves Discussion” on page 11) (Continued)
20
20
V
= 12.0V
V
= 12.0V
H
H
18
16
14
12
18
16
14
12
10
8
10
8
1000pF
100pF/1k
100pF/1k
1000pF
6
6
4
4
2
0
2
0
2.5
3.5
4.5
5.5
2.5
3.5
4.5
5.5
V (V)
DD
V
(V)
DD
FIGURE 25. tpdF vs V
FIGURE 24. tpdR vs V
DD
DD
20
20
V
DD
= 3.3V
V
= 3.3V
DD
18
16
14
12
18
16
14
12
10
8
10
8
100pF/1k
1000pF
100pF/1k
1000pF
6
6
4
4
2
0
2
0
3
6
9
12
3
6
9
12
V
(V)
V
(V)
H
H
FIGURE 26. tpdR vs V
FIGURE 27. tpdF vs V
H
H
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
V
= 12.0V
= 3.6V
V
= 12.0V
= 3.6V
H
H
V
V
DD
DD
330pF
330pF
680pF
680pF
0.0
-40
0.0
-40
-10
+20
PACKAGE TEMP (°C)
+50
+85
-10
+20
PACKAGE TEMP (°C)
+50
+85
FIGURE 28. tSkewR vs TEMPERATURE
FIGURE 29. tSkewF vs TEMPERATURE
FN6228 Rev 8.00
January 29, 2015
Page 10 of 18
ISL55110, ISL55111
Typical Performance Curves (See “Typical Performance Curves Discussion” on page 11) (Continued)
1.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
V
= 12.0V
V
= 12.0V
H
H
0.9
0.8
0.7
0.6
680pF
0.5
0.4
0.3
0.2
680pF
330pF
0.1
0.0
2.5
330pF
3.5
2.5
3.5
4.5
5.5
4.5
5.5
V
(V)
V
(V)
DD
DD
FIGURE 30. tSkewR vs V
FIGURE 31. tSkewF vs V
DD
DD
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
V
= 3.3V
V
= 3.3V
DD
DD
680pF
680pF
330pF
6
330pF
6
3
9
12
3
9
12
V
(V)
V
(V)
H
H
FIGURE 33. tSkewF vs V
FIGURE 32. tSkewR vs V
H
H
probe or differential probe. “TP - IN_A/_B” test points are used
for monitoring pulse input stimulus. “TP - OA/OB” allows
Typical Performance Curves
Discussion
monitoring of driver output waveforms. C and C are the
6
7
usual placement for driver loads. R and R are not populated
3
4
r
and are provided for user-specified, more complex load
characterization.
ON
The r source is tested by placing the device in constant drive
ON
high condition and connecting a -50mA constant current
source to the driver output. The voltage drop is measured from
Pin Skew
V
to driver output for r calculations.
Pin skew measurements are based on the difference in
propagation delay of the two channels. Measurements are
made on each channel from the 50% point on the stimulus
point to the 50% point on the driver output. The difference in
the propagation delay for Channel A and Channel B is
considered to be skew.
H
ON
The r sink is tested by placing the device in constant driver
ON
low condition and connecting a +50mA constant current
source. The voltage drop from driver out to ground is measured
for r calculations.
ON
Dynamic Tests
Both rising propagation delay and falling propagation delay are
measured and report as tSkewR and tSkewF.
All dynamic tests are conducted with ISL55110 and ISL55111
evaluation board(s) (ISL55110_11EVAL2Z). Driver loads are
soldered to the evaluation board. Measurements are collected
with P6245 active FET Probes and TDS5104 oscilloscope.
Pulse stimulus is provided by HP8131 pulse generator.
50MHz Tests
50MHz Tests reported as no load actually include evaluation
board parasitics and a single TEK 6545 FET probe. However, no
driver load components are installed and C through C and
6
9
The ISL55110 and ISL55111 evaluation boards provide test
point fields for leadless connection to either an active FET
R through R are not populated.
3
6
FN6228 Rev 8.00
January 29, 2015
Page 11 of 18
ISL55110, ISL55111
3. The ambient tests are repeated with V of 3.3V and V
DD
General
H
data points of 3V, 6V, 9V and 12V.
The most dynamic measurements are presented in three
ways:
1. Over-temperature with a V of 3.6V and V of 12V.
DD
H
2. At ambient with V set to 12V and V data points of 2.5V,
H
DD
3.5V, 4.5V and 5.50V.
FIGURE 34. ISL55110_11EVAL2Z (QFN) EVALUATION BOARD
FN6228 Rev 8.00
January 29, 2015
Page 12 of 18
ISL55110, ISL55111
Bypassing
Detailed Description
The rapid charging and discharging of the load capacitance
requires very high current spikes from the power supplies. A
parallel combination of capacitors, which have a low impedance
over a wide frequency range should be used. A 4.7µF tantalum
capacitor in parallel with a low inductance 0.1µF capacitor is
usually sufficient bypassing.
The ISL55110 and ISL55111 are dual high-speed MOSFET
drivers intended for applications requiring accurate pulse
generation and buffering. Target applications include ultrasound,
CCD imaging, automotive piezoelectric distance sensing and
clock generation circuits.
With a wide output voltage range and low ON-resistance, these
devices can drive a variety of resistive and capacitive loads with
fast rise and fall times, allowing high-speed operation with low
skew as required in large CCD array imaging applications.
Output Damping
Ringing is a common problem in any circuit with very fast rise or
fall times. Such ringing will be aggravated by long inductive lines
with capacitive loads. Techniques to reduce ringing include:
The ISL55110 and ISL55111 are compatible with 3.3V and 5V
logic families and incorporate tightly controlled input thresholds
to minimize the effect of input rise time on output pulse width.
The ISL55110 has a pair of in-phase drivers while the ISL55111
has two drivers operating in anti-phase. Both channels of the
device have independent inputs to allow external time phasing if
required.
1. Reduce inductance by making printed circuit board traces as
short as possible.
2. Reduce inductance by using a ground plane or by closely
coupling the output lines to their return paths.
3. Use small damping resistor in series with the output of the
ISL55110 and ISL55111. Although this reduces ringing, it will
also slightly increase the rise and fall times.
In addition to driving power MOSFETs, the ISL55110 and
ISL55111 are well suited for other applications such as bus,
control signal and clock drivers for large memory arrays on
microprocessor boards, where the load capacitance is large and
low propagation delays are required. Other potential applications
include peripheral power drivers and charge pump voltage
inverters.
4. Use good bypassing techniques to prevent supply voltage
ringing.
Power Dissipation Calculation
The Power dissipation equation has three components:
Input Stage
1. Quiescent power dissipation.
2. Power dissipation due to internal parasitics.
3. Power dissipation because of the load capacitor.
The input stage is a high impedance buffer with rise/fall
hysteresis. This means that the inputs will be directly compatible
with both TTL and lower voltage logic over the entire V range.
DD
Power dissipation due to internal parasitics is usually the most
difficult to accurately quantitize. This is primarily due to crowbar
current which is a product of both the high and low drivers
conducting effectively at the same time during driver transitions.
Design goals always target the minimum time for this condition
to exist. Given that how often this occurs is a product of
frequency, crowbar effects can be characterized as internal
capacitance.
The user should treat the inputs as high-speed pins and keep rise
and fall times to <2ns.
Output Stage
The ISL55110 and ISL55111 outputs are high-power CMOS
drivers swinging between ground and V . At V = 12V, the output
H
H
impedance of the inverter is typically 3.0Ω. The high peak current
capability of the ISL55110 and ISL55111 enables it to drive a
330pF load to 12V with a rise time of <3.0ns over the full
temperature range. The output swing of the ISL55110 and
Lab tests are conducted with driver outputs disconnected from
any load. With design verification packaging, bond wires are
removed to aid in the characterization process. Based on
laboratory tests and simulation correlation of those results,
Equation 1 defines the ISL55110 and ISL55111 power
dissipation per channel:
ISL55111 comes within <30mV of the V and Ground rails.
H
Application Notes
Although the ISL55110 and ISL55111 are simply dual level
shifting drivers, there are several areas to which careful attention
must be paid.
2
2
P = V
3.3e-3 + 10pF V
f + 135pF VH f+
DD
DD
2
CL VH f (Watts/Channel)
(EQ. 1)
• Where 3.3mA is the quiescent current from the V . This
DD
Grounding
forms a small portion of the total calculation. When figuring
two channel power consumption, only include this current
once.
Since the input and the high current output current paths both
include the ground pin, it is very important to minimize any
common impedance in the ground return. Since the ISL55111
has one inverting input, any common impedance will generate
negative feedback and may degrade the delay times and rise
and fall times. Use a ground plane if possible or use separate
ground returns for the input and output circuits. To minimize any
common inductance in the ground return, separate the input and
output circuit ground returns as close to the ISL55110 and
ISL55111 as possible.
• 10pF is the approximate parasitic capacitor (inverters, etc.),
which the V drives.
DD
• 135pF is the approximate parasitic at the D
and its buffers.
OUT
This includes the effect of the crowbar current.
• C is the load capacitor being driven.
L
FN6228 Rev 8.00
January 29, 2015
Page 13 of 18
ISL55110, ISL55111
The maximum power dissipation actually produced by an IC is
the total quiescent supply current times the total power supply
voltage, plus the power in the IC due to the loads. Power also
depends on number of channels changing state and frequency of
operation. The extent of continuous active pulse generation will
greatly effect dissipation requirements.
Power Dissipation Discussion
Specifying continuous pulse rates, driver loads and driver level
amplitudes are key in determining power supply requirements,
as well as dissipation/cooling necessities. Driver output patterns
also impact these needs. The faster the pin activity, the greater
the need to supply current and remove heat.
The user should evaluate various heatsink/cooling options in
order to control the ambient temperature part of the equation.
This is especially true if the user’s applications require
As detailed in the “Power Dissipation Calculation” on page 13,
power dissipation of the device is calculated by taking the DC
current of the V (logic) and V current (driver rail) times the
DD
H
continuous, high-speed operation. A review of the ratings of
JA
respective voltages and adding the product of both calculations.
the TSSOP and QFN packages clearly show the QFN package to
have better thermal characteristics.
The average DC current measurements of I and IH should be
DD
done while running the device with the planned V and V
DD
H
levels and driving the required pulse activity of both channels at
the desired operating frequency and driver loads.
The reader is cautioned against assuming a calculated level of
thermal performance in actual applications. A careful inspection
of conditions in your application should be conducted. Great care
must be taken to ensure die temperature does not exceed
+150°C Absolute Maximum Thermal Limits.
Therefore, the user must address power dissipation relative to
the planned operating conditions. Even with a device mounted
per Notes 4 or 5 under “Thermal Information”, given the high
speed pulse rate and amplitude capability of the ISL55110 and
ISL55111, it is possible to exceed the +150°C “absolute
maximum junction temperature”. Therefore, it is important to
calculate the maximum junction temperature for the application
to determine if operating conditions need to be modified for the
device to remain in the safe operating area.
Important Note: The ISL55110 and ISL55111 QFN package metal
plane is used for heat sinking of the device. It is electrically
connected to ground (i.e., pin11).
Power Supply Sequencing
Apply V , then V .
DD
H
The maximum power dissipation allowed in a package is
determined according to Equation 2:
Power-Up Considerations
Digital inputs should never be undriven. Do not apply slow analog
ramps to the inputs. Again, place decoupling caps as close to the
T
- T
AMAX
JMAX
(EQ. 2)
--------------------------------------------
P
=
DMAX
JA
package as possible for both V and especially V .
DD
H
Where:
Special Loading
With most applications, the user will usually have a special load
requirement. Please contact Intersil for evaluation boards.
• T
• T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
AMAX
• = Thermal resistance of the package
JA
• P
= Maximum power dissipation in the package
DMAX
FN6228 Rev 8.00
January 29, 2015
Page 14 of 18
ISL55110, ISL55111
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN6228.8
CHANGE
January 29, 2015
Page 1, "Description" section, 4th sentence, removed the word "automotive" before the word piezoelectric".
"Applications", removed 3rd bullet item: "Automotive piezo driver applications"
May 30, 2014
FN6228.7
Throughout document, changed “HIZ” to “ENABLE” and “PDN” pin references to “PD”.
Page 2, “Pin Descriptions” table; Changed “Function” entries for GND and ENABLE pins. Added EP row.
Page 3, “Ordering Info” table; Added “TSSOP” or “QFN” to the Evaluation board entries to clarify.
Page 4 and page 5; Changed “Driver Output Swing Range” Test Conditions entry from “VH voltage to Ground”
to “OA or OB = “1”, Voltage referenced to GND and changed “Driver Supply Quiescent Current” “Test
Conditions” entry from “No resistive load D
” to “Outputs Unloaded”. Added “Figure 1” reference to the
OUT
driver rise and fall time “Test Conditions”.
Page 5; Changed “t ” and “t ” descriptions.
EN DIS
Figure 2 on page 6: changed “Thresholds” to “Times” in title. Figure 3 on page 6: in “tSKEWR” equation,
changed “CHN 1” and “CHN 2” to “CHN A” and “CHN B” and added “absolute value” indicator. Figures 4 and 5:
changed “Resistance” to “Voltage” in titles.
Figures 6 and 7: changed “Resistance” to “Voltage” in titles. Figures 9 and 11: added “Operating” to titles.
Figure 12: Fixed Y-axis scale. Figures 14 and 15: Added “vs. VDD” to titles.
Figures 32 and 33: changed X-axis Label from “V ” to “VH”.
DD
Figure 34: Added “QFN” to title.
“Power Dissipation Discussion” on page 14, changed “It is electrically connected to the negative supply
potential ground” to “It is electrically connected to ground (i.e., pin11)” and, in the “Special Loading” section,
removed text “or to request a device characterization to your requirements in our lab”.
August 8, 2013
July 9, 2012
FN6228.6
FN6228.5
FN6228.4
Page 4 In Electrical Spec Table changed units from mA to µA
II_H Input Current Logic
High
ENABLE = VDD
(QFN only)-
Page 4- Removed “Recommended Operating Conditions table”, which was located above dc electrical spec.
table and placed in the abs max ratings table to meet Intersil standards.
Page 5 - DC Electrical Spec: Modified IH-PDN parameter (Driver Supply Power-Down Current) Max limit value
from 1µ to 2.5µ.
Added Revision History table on page 15.
February 9, 2011
February 4, 2011
For 8 ld TSSOP, added theta JC value of 46C/W. Added foot note that for TSSOP package theta JC the case
temp location is measured in the center of the top of the package.
Page 1: Added following sentence to 3rd paragraph: "Both inputs of the device have independent inputs to
allow external time phasing if required.”
Updated Tape & Reel note in Ordering Information on page 3 from “Add "-T" suffix for tape and reel.” to new
standard “Add "-T*" suffix for tape and reel.” The "*" covers all possible tape and reel options
Added MSL note to Ordering Information
Page 5: Updated over temp note in Min Max column of spec tables from “Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.” to new standard “Compliance to datasheet limits is assured
by one or more methods: production test, characterization and/or design.”
Page 13: Changed Equation 1 from:
P VDD?3.3e-= 3+10pF?VDD2?f+135pF?VH2?f+ (EQ. 1)
CL?VH2?f (Watts/Channel) To P VDD 3.3e-= × 3+10pF × VDD2 × f+135pF × VH2 × f+ CL × VH2
(Watts/Channel) (EQ. 1)
Page 14: Removed the following sentence from “Power Supply Sequencing”:
“The ISL55110, ISL55111 references both VDD and the VH driver supplies with respect to Ground. Therefore,
apply VDD, then VH.”
Replaced with: “Apply VDD, then VH.”
Added subsection “Power Up Considerations” and moved text that was in the “Power Supply Sequencing”
section to this section. (“Digital Inputs should…especially VH.”)
Page 18- Updated POD M8.173 as follows:
Updated to new POD standards as follows: Moved dimensions from table onto drawing. Added Land Pattern.
No dimension changes.
March 14, 2008
FN6228.0
Initial Release
FN6228 Rev 8.00
January 29, 2015
Page 15 of 18
ISL55110, ISL55111
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2006-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6228 Rev 8.00
January 29, 2015
Page 16 of 18
ISL55110, ISL55111
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.4x4A
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGD-10)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
0.90
-
-
-
-
-
-
9
0.20 REF
9
0.18
2.30
2.30
0.25
0.30
2.55
2.55
5, 8
D
4.00 BSC
-
D1
D2
E
3.75 BSC
9
2.40
7, 8
4.00 BSC
-
E1
E2
e
3.75 BSC
9
2.40
7, 8
0.50 BSC
-
k
0.25
0.30
-
-
-
-
L
0.40
0.50
0.15
8
L1
N
-
16
4
4
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
q
-
9
Rev. 2 3/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & q are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present.
L minus L1 to be equal to or greater than 0.3mm.
FN6228 Rev 8.00
January 29, 2015
Page 17 of 18
ISL55110, ISL55111
Package Outline Drawing
M8.173
8 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 01/10
A
2
4
3.0 ±0.5
SEE DETAIL "X"
8
5
6.40
C
4.40 ±0.10
L
3
4
PIN 1
ID MARK
1
4
0.20 CBA
B
0.09-0.20
0.65
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
6
SEATING
PLANE
GAUGE
PLANE
0.25
0.25 +0.05/-0.06
0.10 C B A
0.10 C
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
DETAIL "X"
SIDE VIEW
(1.45)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimension does not include mold flash, protrusions or
gate burrs. Mold flash, protrusions or gate burrs shall
not exceed 0.15 per side.
(5.65)
PACKAGE BODY
OUTLINE
3. Dimension does not include interlead flash or protrusion.
Interlead flash or protrusion shall not exceed 0.15 per side.
4. Dimensions are measured at datum plane H.
5. Dimensioning and tolerancing per ASME Y14.5M-1994.
6. Dimension on lead width does not include dambar protrusion.
Allowable protrusion shall be 0.08 mm total in excess of
dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm.
(0.35 TYP)
(0.65 TYP)
TYPICAL RECOMMENDED LAND PATTERN
7. Conforms to JEDEC MO-153, variation AC. Issue E
FN6228 Rev 8.00
January 29, 2015
Page 18 of 18
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