ISL6131IRZA-T [RENESAS]
4-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24, 4 X 4 MM, ROHS COMPLIANT, PLASTIC, MO-220, QFN-24;
| 型号： | ISL6131IRZA-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24, 4 X 4 MM, ROHS COMPLIANT, PLASTIC, MO-220, QFN-24 |
| 文件： | 总15页 (文件大小：756K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL6131, ISL6132
Multiple Voltage Supervisory ICs
FN9119
Rev 6.00
February 11, 2014
The ISL6131 and ISL6132 are a family of high-accuracy,
multi-voltage supervisory ICs designed to monitor voltages
greater than 0.7V in applications ranging from
microprocessors to industrial power systems. The ISL6131 is
an undervoltage four-supply supervisor, and the ISL6132 is a
two-voltage supervisor monitoring for undervoltage (UV) and
overvoltage (OV) conditions.
Features
• Operates from 1.5V to 5.5V Supply Voltage
• Four Adjustable Voltage Monitoring Thresholds
• 150ms STATUS/PGOOD Stability Time Delay
• Four Individual Open Drain STATUS Outputs
• Guaranteed STATUS/PGOOD Valid to V <1V
DD
Both ICs feature four external resistor programmable voltage
monitoring (VMON) inputs, each with a related STATUS output
that individually reports the related monitor input condition. In
addition, there is a Power-Good (PGOOD) signal that asserts
high when the STATUS outputs are in their correct state. A
stability delay of approximately 160ms ensures that the
monitored supply is stable before STATUS and PGOOD are
released to go high. The PGOOD and STATUS outputs are
open-drain to allow OR’ing of the signals and interfacing to a
wide range of logic levels.
• V and VMON Glitch Immunity
DD
• V Lock-Out
DD
• 4mm X 4mm QFN Package
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves PCB
efficiency and has a thinner profile
• Pb-Free (RoHS Compliant)
STATUS and PGOOD outputs are guaranteed to be valid with IC
bias lower than 1V, eliminating concern about STATUS and
PGOOD outputs during IC bias up and down. VMON inputs are
designed to ignore momentary transients on the monitored
supplies.
Applications
• Multivoltage DSPs and Processors
• µP Voltage Monitoring
• Embedded Control Systems
• Graphics Cards
• Intelligent Instruments
• Medical Equipment
• Network Routers
• Portable Battery-Powered Equipment
• Set-Top Boxes
• Telecommunications Systems
Ru
V
DD
V
UVMON_1
UVMON_2
OVMON_1
OVMON_2
DD
VMON_A
VMON_B
VMON_C
VMON_D
Rm
GROUND
GROUND
PGOOD
Rl
PGOOD1
PGOOD2
EN1 EN2
EN
FIGURE 1. ISL6131 TYPICAL APPLICATION USAGE
FIGURE 2. ISL6132 TYPICAL APPLICATION USAGE
FN9119 Rev 6.00
February 11, 2014
Page 1 of 15
ISL6131, ISL6132
Pin Configuration
Ordering Information
ISL6131, ISL6132
PART
TEMP.
RANGE
(°C)
(24 LD QFN)
TOP VIEW
NUMBER
(Notes 2, 3)
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
24 23 22 21 20 19
ISL6131IRZA
(Note 1)
61 31IRZ
61 32IRZ
-40 to +85 24 Ld 4x4 QFN L24.4x4
18
17
16
15
14
13
1
2
3
4
5
6
ISL6132IRZA
(Note 1)
-40 to +85 24 Ld 4x4 QFN L24.4x4
ISL6131EVAL1Z
ISL6132EVAL1Z
NOTES:
Evaluation Board
Evaluation Board
PD
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
7
8
9
10 11 12
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL6131, ISL6132. For more information on MSL, please see
Tech Brief TB363.
Pin Descriptions
PIN
6131 6132
PIN NAME
FUNCTION DESCRIPTION
23
10
20
12
17
14
NA
NA
NA
NA
24
23
10
NA
NA
NA
NA
12
20
17
14
24
V
Bias IC from nominal 1.5V to 5V
IC ground
DD
GND
VMON_A
VMON_B
VMON_C
VMON_D
OVMON_1
UVMON_1
UVMON_2
OVMON_2
PGOOD
On the ISL6131, these inputs provide a programmable UV threshold referenced to an internal 0.633V. The related
STATUS output asserts when the related input > internal reference voltage.
On the ISL6132, these inputs provide a programmable UV and OV threshold referenced to an internal 0.633V
reference. In the ‘AB’ pair, VMON_A is the UV input, and VMON_B is the OV input. In the ‘CD’ pair, VMON_C is the UV
input, and VMON_D is the OV input.
These inputs have a 30µs glitch filter to prevent PGOOD reset caused by a transient.
On the ISL6131, PGOOD is the Boolean AND function of all four STATUS outputs.
On the ISL6132, PGOOD is for the AB pair and signals high when the monitored voltage is within the specified window
and the A and B STATUS output states are correct.
This is an open-drain output and is to be pulled high to the appropriate level with an external resistor to a V
maximum level.
DD
NA
9
PGOOD2
PGOOD2 is for the CD pair and signals high when the monitored voltage is within the specified window and when the
C and D STATUS output states are correct.
This is an open-drain output and is to be pulled high to the appropriate level with an external resistor to a V
maximum level.
DD
FN9119 Rev 6.00
February 11, 2014
Page 2 of 15
ISL6131, ISL6132
Pin Descriptions (Continued)
PIN
6131 6132
PIN NAME
STATUS_A
STATUS_B
STATUS_C
STATUS_D
OVSTATUS_1
UVSTATUS_1
UVSTATUS_2
OVSTATUS_2
EN1
FUNCTION DESCRIPTION
2
5
NA
NA
NA
NA
5
On the ISL6131, each STATUS provides a high signal through pull-up resistors about 160ms after its related VMON
has continuously been > Vuv_vth. This delay is for stabilization of monitored voltages. STATUS de-asserts and pulls
low upon VMON not being satisfied for about 30µs.
On the ISL6132, the STATUS outputs indicate compliance with a high output state for each pair of monitors.
6
7
NA
NA
NA
NA
1
2
6
7
1
On the ISL6131, this pin provides four voltage UV functions for enabling/disabling input. Internally pulled up to V
.
DD
Controls monitor 1 (AB pair) on ISL6132.
NA
11
-
EN2
PD
On the ISL6132, this pin controls monitor 2 (CD pair) voltage and voltage monitoring function enabling input; pulled
up to V
.
DD
-
Thermal Pad. Should be electrically connected to GND.
NC
3, 4, 8, 13, 15, 16, 18, No Connect
19, 21, 22
FN9119 Rev 6.00
February 11, 2014
Page 3 of 15
ISL6131, ISL6132
Absolute Maximum Ratings
Thermal Information
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Thermal Resistance (Typical, Notes 4, 5)
4x4 QFN Package. . . . . . . . . . . . . . . . . . . . .
(°C/W)
48
JC
(°C/W)
9
DD
JA
VMON, ENABLE, STATUS, PGOOD . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3V
DD
ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV (HBM)
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
V
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.5V to +5.5V
DD
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
6. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications Nominal V = 1.5V to +5V, T = T = -40°C to +85°C, unless otherwise specified. Boldface limits apply
DD
A
J
over the operating temperature range, -40°C to +85°C.
MIN
MAX
PARAMETER
VMON/ENABLE INPUTS
SYMBOL
TEST CONDITIONS
(Note 7)
TYP
(Note 7)
UNIT
VMON Falling Threshold
VMON Threshold Temp. Coeff.
VMON Hysteresis
V
T = +25°C
619
633
40
10
30
8
647
mV
V/°C
mV
s
VMONvth
J
TC
T from -40°C to +85°C
-
-
-
-
-
-
VMONvth
J
V
VMONhys
Tfil
VMON Glitch Filter
VMON Minimum Input Impedance
ENABLE L2H, Delay to STATUS & PGOOD
EN H2L, Delay to PGOOD
EN H2L, Delay to STATUS
ENABLE Pull-up Voltage
ENABLE Threshold Voltage
STATUS/PGOOD OUTPUTS
STATUS Pull-Down Current
STATUS/PGOOD Delay after VMON Valid
STATUS/PGOOD Output Low
BIAS
Zin_min
T = +40°C, VMON within 63mV of V
M
ms
s
J
VMONvth
VMON valid, EN high to STATUS and PG high
EN low to PGOOD low
-
-
-
-
-
160
-
-
0.1
EN low to STATUS low
13
-
-
-
s
EN open
V
V
DD
V
V
/2
V
ENVTH
DD
I
RST = 0.1V
-
-
-
88
-
-
mA
ms
V
RSTpd
T
VMON > V
to STATUS = 0.2V
UVvth
160
delST
Vol
Measured at V = 1.0V
0.04
0.1
DD
IC Supply Current
I
I
I
V
V
V
V
V
= 5V
-
-
-
-
-
170
145
100
0.89
0.91
-
-
A
A
A
V
VDD_5.5V
VDD_3.3V
VDD_1.5V
DD
DD
DD
DD
DD
IC Supply Current
= 3.3V
IC Supply Current
= 1.5V
-
V
V
Power On
V
_POR
DD
high to low
low to high
1
-
DD
DD
Power On Lock Out
V
_LO
V
DD
NOTE:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN9119 Rev 6.00
February 11, 2014
Page 4 of 15
ISL6131, ISL6132
input > VMON Vth continuously for ~160ms, its associated
STATUS output releases high, indicating that the minimum
voltage condition has been met. As both UVMON and OVMON
inputs are satisfied, the PGOOD output is released to go high,
indicating that the monitored voltage is within the specified
window. Figure 18 shows this performance for a 4V to 5V
window.
Description and Operation
The ISL6131 is a four-voltage, high-accuracy, supervisory IC
designed to monitor multiple voltages greater than 0.7V relative
to Pin 10 of the IC.
Upon V bias power-up, the STATUS and PGOOD outputs are
DD
held correctly low once V is as low as 1V. Once biased to 1.5V,
DD
the IC continuously monitors from one to four voltages
independently through external resistor dividers, comparing each
voltage monitoring (VMON) pin voltage to an internal 0.633V
When VMON does not satisfy its voltage high or low criteria for
more than the glitch filter time, the associated STATUS and
PGOOD are pulled low. Figures 19 and 20 show this performance
for a 4V to 5V compliant window.
(V
) reference.
VMONvth
With the EN input driven high or open, as each VMON input rises
above V , a timer is set to ensure ~160ms of continuous
compliance. Then the related STATUS output is released to be
pulled high. The STATUS outputs are open-drain to allow OR’ing of
Figures 21 through 23 show the VMON glitch filter timing to
STATUS and PGOOD notification and transient immunity.
VMONvth
The ENABLE input, when pulled low, allows the monitoring and
reporting functions to be disabled. Figure 24 shows ENABLE high
to PGOOD timing for compliant voltage.
these signals and interfacing to a logic high level up to V . The
DD
STATUS outputs are designed to reject short transients (~30s)
on the VMON inputs. Once all STATUS outputs are high, a
Power-Good (PGOOD) output signal is generated high to indicate
that all monitored voltages are greater than minimum
compliance level.
When choosing resistors for the divider, remember to keep the
current through the string bounded by power loss tolerance at the
top end and noise immunity at the bottom end. For most
applications, total divider resistance in the 10k -100krange
is advisable, with 1% tolerance resistors being used to reduce
monitoring error.
Once any VMON input falls below V
VMONvth
for longer than the
glitch filter time, both the PGOOD and the related STATUS output
are pulled low. The other STATUS outputs remain high as long as
their corresponding VMON voltage remains valid and the PGOOD
validation process is reset.
Figures 1 and 2 show that choosing the two resistor values is
straightforward for the ISL6131, because the ratio of resistance
should equal the ratio of the desired trip voltage to the internal
reference, 0.633V.
Figure 1 shows the ISL6131 typical application schematic, and
Figure 3 is an operational timing diagram. See Figures 10 to 17 for
ISL6131 function and performance. Figures 10 and 11 show the
For the ISL6132, two dividers of two resistors each can be
employed to monitor the OV and UV levels for each voltage.
Otherwise, use a single three-resistor string for each voltage. In
the three-resistor divider string, the ratio of the desired
overvoltage trip point to the internal reference is equal to the
ratio of the two upper resistors to the lowest (GND connected)
resistor. The desired undervoltage trip point ratio to the internal
reference voltage is equal to the ratio of the uppermost (voltage
connected) resistor to the two lower resistors, as shown in the
following example:
V
rising along with STATUS and PGOOD response. Figures 12
DD
and 13 illustrate VMON falling below V
, and Figure 14
VMONvth
with STATUS and PGOOD
shows VMON rising above V
VMONvth
response. Figure 15 shows V failing, with STATUS and PGOOD
DD
response. Figures 16 and 17 show ENABLE to STATUS and PGOOD
timing.
If less than four voltages are being monitored, connect the
unused VMON pins to V for proper operation. All unused
DD
STATUS outputs can be left open.
1. Establish lower and upper trip level: 3.3V ±20% or 2.64V (UV)
and 3.96V (OV)
The ISL6132 is a dual voltage monitor for undervoltage and
overvoltage compliance. Figure 2 shows the typical ISL6132
implementation schematic, and Figure 4 is the operational timing
diagram.
2. Establish total resistor string value: 10kIr = divider current
3. (Rm + Rl) * Ir = 0.623V @ UV and Rl * Ir = 0.633V @ OV
4. Rm + Rl = 0.623V/Ir @ UV => Rm + Rl =
There are two pairs of monitors, each with an undervoltage
(UVMON) input and an overvoltage (OVMON) input, along with
associated STATUS and PGOOD outputs.
0.623V/(2.64V/10kΩ) = 2.359kΩ
5. Rl = 0.633V/Ir @ OV => Rl = 0.633V/(3.96V/10kΩ) = 1.598kΩ
6. Rm = 2.359kΩ - 1.598kΩ = 0.761kΩ
Upon V bias power-up, the STATUS and PGOOD outputs are
DD
7. Ru = 10kΩ - 2.397kΩ = 7.641kΩ
held correctly low, once V is as low as 1V. Once biased to 1.5V,
DD
Choose standard value resistors that most closely approximate
these ideal values. Choosing a different total divider resistance
value may yield a more ideal ratio with available resistors values.
the IC continuously monitors the voltage through external resistor
dividers, comparing each VMON pin voltage to an internal 0.633V
reference. At proper bias, OVSTATUS is pulled high, and
UVSTATUS and PGOOD are pulled low. Once the UVMON
FN9119 Rev 6.00
February 11, 2014
Page 5 of 15
ISL6131, ISL6132
A
B
C
D
C
D
VMONVth
VMON
INPUT
VOLTAGE
STSDLY
STSDLY
<Tfil
>Tfil
STSDLY
STSDLY
STSDLY
B
C
A
C
D
STATUS OUTPUTS
PGOOD OUTPUT
EN INPUT
FIGURE 3. ISL6131 OPERATIONAL TIMING DIAGRAM
OVERVOLTAGE
LIMIT
OV
TdelST
Tfil
<Tfil
UNDERVOLTAGE
LIMIT
TdelST
Tfil
MONITORED VOLTAGE
RAMPING UP & DOWN
OVSTATUS
UVSTATUS
PGOOD OUTPUT
FIGURE 4. ISL6132 OPERATIONAL DIAGRAM
Typical Performance Curves
634
0.30
0.25
633
V
= 5V
DD
632
631
630
629
628
627
626
0.20
0.15
V
= 1.5V
DD
0.1
0.05
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 5. UV THRESHOLD
FIGURE 6. V CURRENT
DD
FN9119 Rev 6.00
February 11, 2014
Page 6 of 15
ISL6131, ISL6132
Applications Usage
Using the ISL6131EVAL1Z and
ISL6132EVAL1Z Platforms
VIN
EN
VOUT
DC-DC_A
The ISL6131EVAL1Z platform is set up to monitor and report an
undervoltage condition on each of 12V, 5V, 3.3V and 1.2V
supplies to a -20% tolerance.
VIN
EN
VOUT
DC-DC_B
Each monitored supply has an individual STATUS output and an
AND’ed PGOOD output signal for all four supplies. An OFF LED is
the PGOOD indicator for all four supplies. The ENABLE input
enables or disables the voltage monitoring function. See Figures
10 to 17 for performance and function examples.
VIN
EN
VOUT
DC-DC_C
The ISL6132EVAL1Z platform is set up to monitor and report
either an undervoltage or an overvoltage condition on 5V and
12V supplies to a ±10% tolerance. There is an OV and a UV
STATUS output for each of the two supplies and individual
AND’ed PGOOD outputs when each voltage is within the
programmed voltage range. An OFF LED indicates compliance to
the voltage range upper and lower limits.
ABC
STATUS
VMON_A
VMON_D
PGOOD
VMON_C
VMON_B
ISL6131
VDD
ENABLE
The ENABLE inputs enable or disable the voltage monitoring
functions for each monitor supply.
GND
See Figures 18 to 24 for performance and function examples.
Figures 25 and 26 illustrate the ISL6131EVAL1Z and
ISL6132EVAL1Z platforms respectively in image and schematic.
FIGURE 7. ISL6131 “LOSSLESS” SEQUENCING CONFIGURATION
Using the ISL6131 for System Voltage and
Over-Temperature Monitoring
Using the ISL6131, ISL6132 for Negative
Voltage Monitoring Applications
As a multi-voltage monitoring IC, the ISL6131 can monitor
over-temperature as well as voltage for more complete coverage
of system stability. Using a Negative Temperature Coefficient
(NTC) passive device in place of one of the resistors in a VMON
divider provides over-temperature monitoring either locally or
remotely.
The ISL6131, ISL6132 can be used for -V monitoring because it
monitors any voltage that is more positive relative to its GND pin.
With correct bias differential, these parts can monitor any
voltage, regardless of polarity or amplitude.
Using the ISL6131 for “Lossless” Sequencing
Applications
The ISL6131 can be used in a “lossless” sequencing application
in which a monitored output voltage determines the start of the
next sequenced turn-on. As shown in Figure 7, VMON_A input
Evaluations of this application configuration have involved the
QT0805T-202J, QT0805Y-502J and QT0805Y-103J NTCs from
Quality Thermistor.
ISL6131 over-temperature monitoring is not as accurate as
specific temperature monitor ICs, but this implementation
provides a cost-efficient solution with 5% tolerances achievable.
looks at the common V of several DC-DC converters and
IN
enables DC-DC_A with STATUS _A, once both V and ENABLE are
IN
satisfied. VMON_B monitors the output of DC-DC_A, and when
the acceptable output voltage is reached, DC-DC_B is enabled
with STATUS_B output. This sequencing pattern continues until
all DC-DC outputs are on, at which time PGOOD signal is
See Figures 8 and 9 for over-temperature sensing configuration
and operation results. In this example, the desired maximum
temperature is 100°C. The QT0805Y-103J NTC was placed at the
end of 3 feet of twisted pair wire to emulate a remote sensing
application. According to the Quality Thermistor data sheet, this
NTC device has a +25°C value of 10K and a +100°C value of
0.923K. An accompanying standard value resistor of 3.83K was
chosen for the divider so that at 100°C, VMON ~0.633V with the
bias voltage at 3.3V.
released. A delay of 160ms from VMON > V
to STATUS
VMONVth
high ensures stability at each step prior to subsequent turn-on.
Additional ISL6131s can be employed in parallel to sequence any
number of DC-DC convertors in this fashion.
The resulting falling VMON trip point with the configuration
shown is ~0.634V, with ~0.642V for rising, which equates to
~95°C for under-temperature and ~97°C for over-temperature,
respectively. Choosing the standard resistor value above and
below R1 allows for small adjustments in the temperature trip
point.
FN9119 Rev 6.00
February 11, 2014
Page 7 of 15
ISL6131, ISL6132
The low ISL6131 VMON temperature coefficient makes it a
viable and low-cost addition to complete system monitoring.
TEMP (°C)
25
VMON (V)
2.36
TEMP STATUS
H = Under Temp
H = Under Temp
H = Under Temp
H = Under Temp
L = Over Temp
L = Over Temp
TEMP INDICATOR
STATUS
50
1.61
75
1.01
3.3V
VDD
95
0.67
3.83k
R1
100
105
0.61
0.54
VMON
T
VMON 0.1V/DIV
ISL6131
QT0805Y-103J
(REMOTE HEAT
GND
SOURCE LOCATION)
FIGURE 8. ISL6131 OVER-TEMP SENSING CONFIGURATION
LOW = OVER TEMP
TEMP STATUS 5V/DIV
10s/DIV
FIGURE 9. ISL6132 OVER-TEMP SENSING RESULT
FN9119 Rev 6.00
February 11, 2014
Page 8 of 15
ISL6131, ISL6132
Functional and Performance Waveforms
STATUS OUTPUTS PULLED UP TO 1.5V
V
RISING
DD
STATUS OUTPUTS TO V
DD
V
RISING
DD
PGOOD
PGOOD
1V/DIV
100s/DIV
1V/DIV
200s/DIV
FIGURE 10. ISL6131 V
RISING
FIGURE 11. ISL6131 V
RISING WITH PULL-UP
DD
DD
VMON FALLING BELOW UV Vth (0.1V/DIV)
UNRELATED STATUS OUTPUTS
VMON FALLING BELOW UV Vth (0.1V/DIV)
UV Vth 0.63V
UV Vth 0.63V
UNRELATED STATUS OUTPUTS
RELATED STATUS OUTPUT
RELATED STATUS OUTPUT
PGOOD
PGOOD
1V/DIV
40ms/DIV
1V/DIV
10ms/DIV
FIGURE 12. ISL6131 VMON FALLING TO PGOOD
FIGURE 13. ISL6131 VMON FALLING TO PGOOD
VMON RISING ABOVE UV Vth (0.1V/DIV)
UV Vth 0.63V
V
FALLING
DD
UNRELATED STATUS OUTPUTS
STATUS OUTPUTS
RELATED STATUS OUTPUT
PGOOD
PGOOD
1V/DIV
20ms/DIV
1V/DIV
40ms/DIV
FIGURE 14. ISL6131 UV RISING TO PGOOD
FIGURE 15. ISL6131 V
FALLING
DD
FN9119 Rev 6.00
February 11, 2014
Page 9 of 15
ISL6131, ISL6132
Functional and Performance Waveforms(Continued)
ENABLE
STATUS
ENABLE
STATUS
PGOOD
PGOOD
2V/DIV
20ms/DIV
2V/DIV
2µs/DIV
FIGURE 16. ISL6131 ENABLE L2H TO PGOOD
FIGURE 17. ISL6131 EN H2L TO PGOOD
MONITORING 4V TO 5V
MONITORING 4V TO 5V
OV STATUS
V
RISING
DD
MONITORED VOLTAGE FALLING
UV/PGOOD
STATUS RISING
PGOOD AND UV
OV STATUS RISING
STATUS PULLED LOW
1V/DIV
40ms/DIV
1V/DIV
10ms/DIV
FIGURE 18. ISL6132 TURN-ON
FIGURE 19. ISL6132 IN UV CONDITION
MONITORING 4V TO 5V
MONITORING 4V TO 5V
UV STATUS
VMON FALLING (1V/DIV)
4V MIN LIMIT
MONITORED VOLTAGE RISING
UV STATUS
OV STATUS
PGOOD AND OV
STATUS PULLED LOW
PGOOD
1V/DIV
10ms/DIV
5V/DIV
10µs/DIV
FIGURE 20. ISL6132 IN OV CONDITION
FIGURE 21. ISL6132 UV GLITCH FILTER TIMING
FN9119 Rev 6.00
February 11, 2014
Page 10 of 15
ISL6131, ISL6132
Functional and Performance Waveforms(Continued)
MONITORING 4V TO 5V
5V MAX LIMIT
VMON RISING (1V/DIV)
VMON 5.5V TO 3.5V
UV STATUS
OV STATUS
UV, OV STATUS & PGOOD
5V
OUT
PGOOD
5V/DIV
10µs/DIV
8µs/DIV
FIGURE 22. ISL6132 OV GLITCH FILTER TIMING
FIGURE 23. ISL6132 GLITCH FILTER TRANSIENT IMMUNITY
ENABLE
PGOOD
OV, UV STATUS
20ms/DIV
1V/DIV
FIGURE 24. ISL6132 ENABLE TO PGOOD
FN9119 Rev 6.00
February 11, 2014
Page 11 of 15
ISL6131, ISL6132
ISL6131EVAL1Z and ISL6132EVAL1Z Descriptions
5V
R11
10k
R12
10k
1.2V
5V STATUS
12V STATUS
3.3V
12V
R10
10k
R9
10k
1.2V STATUS
3.3V STATUS
2
5
6
7
D
A
B
C
STATUS
R4
R2
R3
R1
23
V
DD
C1
1µF
53.6k 5.11k
31.6k 140k 12
VMONB
VMOND
VMONC
VMONA
14
17
R13
5.11k
R8
R6
10k
ISL6131
D1
10k
20
R7
10k
24
R5
10k
PGOOD
PGOOD
GND
10
EP
1
EN1
FIGURE 25. ISL6131EVAL1Z SCHEMATIC AND PHOTOGRAPH
FN9119 Rev 6.00
February 11, 2014
Page 12 of 15
ISL6131, ISL6132
5V
R11
10k
R12
10k
5V OV STATUS
5V UV STATUS
R9
10k
R10
10k
12V
12V OV STATUS
12V UV STATUS
2
5
6
7
OV2
UV1 OV1 UV2
STATUS
23
V
DD
R4
76.8k
R3
61.9k
R2
196k
R1
158k
C1
1µF
12
20
14
17
OVMON1
UVMON1
OVMON2
UVMON2
R13
10k
R14
10k
R8
10k
R7
10k
D1
D2
ISL6132
R6
10k
24
9
R5
5V PGOOD
PGOOD
10k
12V PGOOD
PGOOD2
GND
10
EP
1
11
EN1
EN2
FIGURE 26. ISL6132EVAL1Z SCHEMATIC AND PHOTOGRAPH
TABLE 1. ISL6131EVAL1Z, ISL6132EVAL1Z COMPONENT LISTING
COMPONENT
DESIGNATOR
COMPONENT FUNCTION
COMPONENT DESCRIPTION
U1
ISL6131, Quad Undervoltage Supervisor
12V Upper Divider Resistor
Intersil, ISL6131IR Quad Undervoltage Supervisor
R1
140kΩ
R2
1.2V Upper Divider Resistor
5.11kΩ
R3
3.3V Upper Divider Resistor
31.6kΩ
R4
5V Upper Divider Resistor
53.6kΩ
U1
ISL6132, Dual Over & Undervoltage Supervisor
12V Upper UV Divider Resistor
12V Upper OV Divider Resistor
5V Upper UV Divider Resistor
5V Upper OV Divider Resistor
Lower Divider Resistors
Intersil, ISL6132IR Dual Overvoltage & Undervoltage Supervisor
R1
158kΩ
196kΩ
61.9kΩ
76.8kΩ
10kΩ
R2
R3
R4
R5, R6, R7, R8
R9, R10, R11, R12 STATUS Pull-up Resistors
10kΩ
C1
Decoupling Capacitor
PGOOD# INDICATOR
1µF
D1, D2
SMD RED LED
FN9119 Rev 6.00
February 11, 2014
Page 13 of 15
ISL6131, ISL6132
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
FN9119.6
CHANGE
February 11, 2014
• On page 5 - right hand column, paragraph 5 that starts with: "For the ISL6131, two dividers of two resistors
each can be employed to monitor the OV and UV levels for each voltage. Otherwise, use a single three-resistor
string for each voltage." Changed ISL6131 to ISL6132.
• On page 14 - Updated Products section to updated About Intersil verbiage
July 18, 2011
FN9119.5
• On page 2, Ordering Information: added ISL6131EVAL1Z and ISL6132EVAL1Z Evaluation Boards.
• On page 7: changed "Using the ISL613XSUPEREVAL2 Platform" section to "Using the ISL6131EVAL1Z and
ISL6132EVAL1Z Platforms" and rewrote text.
• On page 12: replaced Fig. 25, “ISL613XSUPEREVAL2 PHOTOGRAPH” with “ISL6131EVAL1Z SCHEMATIC AND
PHOTOGRAPH.“
• On page 13: replaced Fig. 26, “ISL613XSUPEREVAL2 CHANNEL 1 SCHEMATIC” with “ISL6132EVAL1Z
SCHEMATIC AND PHOTOGRAPH.”
• Converted to latest datasheet template.
August 17, 2010
FN9119.4
• P1: Removed prenotification part ISL6132IR & Obsolete part ISL6131IR from Order Info. Added Part Marking
column to Order Info. Updated Pb-free bullet in Features and Pb-free note in Ordering Information based on lead
finish. Added TB347 link to ordering information for reel specifications.
• P3: Per customer request, added "PD" label to Pinout and description to Pin Descriptions table, which states
"Thermal Pad. Should be electrically connected to GND".
• P4: Updated Caution statement in Abs Max. Removed Max Lead Soldering Temp from Thermal Info and
replaced with Pb-Free Reflow link. Added standard temp range note to spec table MIN MAX columns.
• P13: Updated POD to latest released. Changes were to convert to new QFN format and correct Note 4
(corrected “0.015mm and 0.30mm” to “0.15mm and 0.30mm”).
July 22, 2005
FN9119.3
• Added additional application usage text to clarify component choice. Corrected typographical errors in spec
table.
August 18, 2004
March 5, 2004
July 15, 2003
FN9119.2
FN9119.1
FN9119.0
• Added Pb-free parts.
• Added application information.
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
© Copyright Intersil Americas LLC 2003-2014. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9119 Rev 6.00
February 11, 2014
Page 14 of 15
ISL6131, ISL6132
Package Outline Drawing
L24.4x4
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 10/06
4X
2.5
4.00
A
20X
0.50
PIN #1 CORNER
(C 0 . 25)
B
19
24
PIN 1
INDEX AREA
1
18
2 . 10 ± 0 . 15
13
0.15
(4X)
12
24X 0 . 4 ± 0 . 1
7
0.10 M C
A B
TOP VIEW
+ 0 . 07
24X 0 . 23
4
- 0 . 05
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
0 . 90 ± 0 . 1
C
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
0.08
SIDE VIEW
C
(
2 . 10 )
( 20X 0 . 5 )
5
C
0 . 2 REF
( 24X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN9119 Rev 6.00
February 11, 2014
Page 15 of 15
相关型号：
ISL6132IR
4-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24, 4 X 4 MM, PLASTIC, MO-220VGGD-2, QFN-24
RENESAS
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