ISL6144IVZAT_技术文档

ISL6144

Data Sheet

October 6, 2011

FN9131.7

High Voltage ORing MOSFET Controller

Features

The ISL6144 ORing MOSFET Controller and a suitably sized

N-Channel power MOSFET(s) increases power distribution

efficiency and availability when replacing a power ORing diode

in high current applications.

• Wide Supply Voltage Range +9V to +75V

• Transient Rating to +100V

• Reverse Current Fault Isolation

• Internal Charge Pump Allows the use of N-Channel

MOSFET

In a multiple supply, fault tolerant, redundant power distribution

system, paralleled similar power supplies contribute equally to

the load current through various power sharing schemes.

Regardless of the scheme, a common design practice is to

include discrete ORing power diodes to protect against reverse

current flow should one of the power supplies develop a

catastrophic output short to ground. In addition, reverse current

can occur if the current sharing scheme fails and an individual

power supply voltage falls significantly below the others.

• HS Comparator Provides Very Fast <0.3µs Response

Time to Dead Shorts on Sourcing Supply. HS Comparator

also has Resistor-adjustable Trip Level

• HR Amplifier allows Quiet, <100µs MOSFET Turn-off for

Power Supply Slow Shut Down

• Open Drain, Active Low Fault Output with 120µs Delay

• Provided in Packages Compliant to UL60950 (UL1950)

Creepage Requirements

Although the discrete ORing diode solution has been used for

some time and is inexpensive to implement, it has some

drawbacks. The primary downside is the increased power

dissipation loss in the ORing diodes as power requirements for

systems increase. Another disadvantage when using an ORing

diode would be failure to detect a shorted or open ORing diode,

jeopardizing power system reliability. An open diode reduces

the system to single point of failure while a diode short might

pose a hazard to technical personnel servicing the system

while unaware of this failure.

• QFN Package:

- Compliant to JEDEC PUB95 MO-220

QFN - Quad Flat No Leads - Package Outline

- Near Chip Scale Package footprint, which improves

PCB efficiency and has a thinner profile

• Pb-Free (RoHS Compliant)

Applications

The ISL6144 can be used in 9V to 75V systems having similar

power sources and has an internal charge pump to provide a

floating gate drive for the N-Channel ORing MOSFET. The High

Speed (HS) Comparator protects the common bus from

individual power supply shorts by turning off the shorted feed’s

ORing MOSFET in less than 300ns and ensuring low reverse

current.

• ORing MOSFET Control in Power Distribution Systems

• N + 1 Redundant Distributed Power Systems

• File and Network Servers (12V and 48V)

• Telecom/Datacom Systems

An external resistor-programmable detection level for the HS

Comparator allows users to set the N-Channel MOSFET

“V

- V ” trip point to adjust control sensitivity to power

OUT

IN

supply noise.

The Hysteretic Regulating (HR) Amplifier provides a slow turn-

off of the ORing MOSFET. This turn-off is achieved in less than

100μs when one of the sourcing power supplies is shutdown

slowly for system diagnostics, ensuring zero reverse current.

This slow turn-off mechanism also reacts to output voltage

droop, degradation, or power-down.

An open drain FAULT pin will indicate that a fault has occurred.

The fault detection circuitry covers different types of failures;

including dead short in the sourcing supply, a short of any two

ORing MOSFET terminals, or a blown fuse in the power

distribution path.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ISL6144

Ordering Information

PART NUMBER

(Notes 2, 3)

PART

MARKING

TEMP. RANGE

PACKAGE

(Pb-free)

PKG.

DWG. #

(°C)

ISL6144IVZA (Note 1)

ISL6144IRZA (Note 1)

ISL6441EVAL1Z

NOTES:

ISL61 44IVZ

-40 to +105

16 Ld TSSOP

20 Ld 5x5 QFN

M16.173

L20.5x5

ISL6144 IRZ

Evaluation Platform

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin

plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6144. For more information on MSL please see techbrief TB363.

Pinouts

ISL6144

(16 LD TSSOP)

TOP VIEW

ISL6144

(20 LD 5x5 QFN)

TOP VIEW

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GATE

VIN

VOUT

COMP

VSET

NC

20 19 18 17 16

1

2

3

4

5

15

14

13

VIN

HVREF

NC

VOUT

COMP

VSET

HVREF

NC

12 NC

11 NC

NC

6

7

8

9

10

FAULT

GND

Pin Descriptions

TSSOP

PIN #

QFN

PIN #

SYMBOL

FUNCTION

DESCRIPTION

1

2

3

8

9

19

1

GATE

VIN

External FET Gate Drive

Power Supply Connection

Allows active control of external N-Channel FET gate to perform ORing function.

Chip bias input. Also provides a sensing node for external FET control.

2

HVREF Chip High Voltage Reference Low side of floating high voltage reference for all of the HV chip circuitry.

7

GND

Chip Ground Reference

Chip ground reference point.

9

FAULT Fault Output

Provides an open drain active low output as an indication that a fault has

occurred: GATE is OFF (GATE < V + 0.37V) or other types of faults

IN

resulting in V - V

IN

> 0.41V.

OUT

14

15

16

13

14

15

VSET

Low Side Connection for

Trip Level

Resistor connected to COMP provides adjustable “Vd - Vs” trip level along

with pin COMP.

COMP High Side Connection for HS Resistor connected to V

provides sense point for the adjustable Vd - Vs

OUT

trip level along with pin VSET.

Comparator Trip Level

VOUT

NC

Chip Bias and Load

Connection

Provides the second sensing node for external FET control and chip output

bias.

4, 5, 6, 7, 3, 4, 5, 6, 8,

No Connection

10, 11,

12, 13

10, 11, 12,

16, 17,

18, 20

FN9131.7

October 6, 2011

2

ISL6144

General Application Circuit

+

-

DC/DC

1

AC/DC

1

GATE

VIN

VOUT

COMP

VSET

VIN

VOUT

ISL6144

HVREF

COMP

5V

FAULT

VSET

GND

AC/DC

N + 1

DC/DC

N + 1

GATE

VIN

VOUT

ISL6144

VIN

VOUT

ISL6144

HVREF

COMP

HVREF

COMP

5V

FAULT

VSET

GND

NOTES:

4. AC/DC 1 through (N + 1) are multistage AC/DC converters which include AC/DC rectification stage and a DC/DC Converter with a +48VDC

output (also might include a Power Factor Correction stage).

5. DC/DC Converter 1 through (N + 1) are DC/DC converters to provide additional Intermediate Bus.

6. Load “+12V” and Load “+48V” might include other DC/DC converter stages to provide lower voltages such as ±15V, ±5V, +3.3V, +2.5V,

+1.8V etc.

7. Fuse location might vary depending on power system architecture.

FIGURE 1. ISL6144 GENERAL APPLICATION CIRCUIT IN A DISTRIBUTED POWER SYSTEM

FN9131.7

October 6, 2011

3

ISL6144

Simplified Block Diagram

D *

2

SOURCE 2

9V TO 75V

F2**

R

C

2

C

1

VIN GATE

VOUT

COMP

HVREF

ISL6144

R

2

VSET

FAULT

GND

* D , D PARASITIC DIODES

1

2

**F1, F2 FUSES COULD ALSO BE PLACED

ON THE INPUT SIDE BEFORE THE VIN PIN. THIS

PLACEMENT DEPENDS ON POWER SYSTEM

ARCHITECTURE.

D *

1

F1**

SOURCE 1

VIN

GATE

9V TO 75V

LOAD

VOUT

GATE LOGIC AND

CHARGE PUMP

C

1

FAULT

DETECTION

R

C

2

1

HIGH

VOLTAGE

PASS

5.3V

0.1mA

5.5V

20mV

AND

-

CLAMPING

+

LEVEL

SHIFT

+

REG

AMPLIFIER

COMP

VSET

-

2A*

5mA

R

2

+

HS

HVREF

FAULT

COMP

-

0.6V

BIAS

AND

REF

DELAY

100µs

+

UV

COMP

0.2mA

1.5mA

GND

1.5mA

FN9131.7

October 6, 2011

4

ISL6144

Absolute Maximum Ratings (Note 8) T = +25°C

Thermal Information

A

V

, V

OUT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +100V

Thermal Resistance (Typical)

θ

(°C/W)

θ

(°C/W)

JC

JA

IN

GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V +12V

HVREF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V -5V

IN

COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

VSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

IN

TSSOP Package (Note 9) . . . . . . . . . .

QFN Package (Notes 10, 11). . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

90

35

N/A

5

OUT

-5V

OUT

Operating Conditions

Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . +9V to +75V

Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . -40°C to +105°C

A

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

8. All voltages are relative to GND, unless otherwise specified.

9. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

10. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

11. For θ , the "case temp" location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications

V

= 48V, T = -40°C to +105°C, Unless Otherwise Specified. Boldface limits apply over the operating

A

IN

temperature range, -40°C to +105°C.

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 12)

TYP

(Note 12) UNITS

BIAS “V

”

IN

POR Rising

POR

V

Rising to V > V + 7.5V

GATE IN

8.9

-

V

L2H

IN

12V Bias Current

48V Bias Current

75V Bias Current

GATE

I

= 12V, V

= 48V, V

= 75V, V

= V + V

IN

-

3.5

4.5

5

mA

12V

GATE

GQP

= V + V

IN

48V

75V

= V + V

IN

Charge Pump Voltage

Gate Low Voltage Level

Low Pull Down Current

High Pull Down Current

Slow Turn-off Time

Fast Turn-off Time

V

= 12V to 75V

V

+ 9

V

+ 10.5

V

+ 12

V

GQP

IN

V

- V

< 0V

-0.3

V

IN

V

+ 0.5

GL

OUT

IN

I

Cgs = 39nF, I

Cgs = 39nF

= Cgs*dVgs/T

tofs

-

5

-

mA

A

PDL

I

= Cgs*dVgs/T

2

-

PDH

toff

t

100

µs

ns

toffs

t

Turn-off from V

= V + V

IN

to V + 1V with

IN

250

300

toff

GATE

GQP

Cgs = 39nF (includes HS Comparator delay time)

Start-up “Turn-On” Time

t

I

Turn-on from V = V to V + 7.5V into 39nF

-

1

-

ms

ON

GATE

= 9V to 75V

IN IN

GATE Turn-On Current

V

mA

IN

CONTROL AND REGULATION I/O

HR Amplifier Forward Voltage

Regulation

V

ISL6144 controls voltage across FET Vds to

during static forward operation at loads

10

0

20

30

mV

V

FWD_HR

V

FWD_HR

resulting in I * r

< V

DS(ON)

FWD_HR

HS COMP Externally

V

Externally programmable threshold for noise

0.05

5.3

TH(HS)

Programmable Threshold

sensitivity (system dependent), typical 0.05V to 0.3V

HS Comparator Offset Voltage

V

-40

0

25

mV

µA

OS(HS)

Comp Input Current

(Bias Current)

I

-

1.1

-

COMP

HVREF Voltage (V - HVREF)

IN

HV

V

= 9V to 75V

IN

-

5.5

-

V

REF(VZ)

FN9131.7

October 6, 2011

5

ISL6144

Electrical Specifications

V

= 48V, T = -40°C to +105°C, Unless Otherwise Specified. Boldface limits apply over the operating

IN

A

temperature range, -40°C to +105°C.

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

= 9V to 75V

(Note 12)

TYP

(Note 12) UNITS

VSET Voltage (V

- VSET)

V

-

5.3

-

0.5

-

V

OUT

REF(VSET)

IN

Fault Low Output Voltage

Fault Sink Current

V

- V

< 0V, V

= V

-

FLT_L

FLT_SINK

OUT

GATE

GL

, V

I

FAULT = V

, V < V

= V

4

-

mA

µA

FLT_L IN

OUT GATE

GL

Fault Leakage Current

I

FAULT = ”V ”, V > V

, V

= V

+

10

FLT_LEAK

FLT_H IN

OUT GATE

IN

V

GQP

GATE = V to FAULT V

=

Fault Delay - Low to High

NOTES:

t

-

120

-

µs

FLT

GL

FLT_L

12. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

FAULT

Functional Pin Descriptions

Open-Drain pull-down FAULT Output with internal on-chip

filtering (t_FLT). The ISL6144 fault detection circuitry will

pull-down this pin to GND as soon as it detects a fault.

Different types of faults and their detection mechanisms are

discussed in more detail in the “Functional Block Description”

on page 6.

GATE

This is the Gate Drive output of the external N-Channel

MOSFET generated by the IC internal charge pump. Gate

turn-on time is typically 1ms.

VIN

Input bias pin connected to the sourcing supply side (ORing

MOSFET Source). Also serves as the sense pin to

determine the sourcing supply voltage. The ORing MOSFET

will be turned off when VIN becomes lower than VOUT by a

value more than the externally set threshold.

GND

IC ground reference.

Detailed Description

The ISL6144 and a suitably sized N-Channel power

MOSFET(s) increases power distribution efficiency and

availability when replacing a power ORing diode in high current

applications. Refer to “Application Considerations” on page 8

for power saving when using ISL6144 with an N-channel ORing

MOSFET compared to a typical ORing diode.

VOUT

Connected to the Load side (ORing MOSFET Drain). This is

the VOUT sense pin connected to the load. This is the

common connection point for multiple paralleled supplies.

VOUT is compared to VIN to determine when the ORing

FET has to be turned off.

Functional Block Description

HVREF

Regulating Amplifier-Slow (Quiet) Turn-off

Low side of the internal IC High Voltage Reference used by

internal circuitry, also available as an external pin for

additional external capacitor connection.

A Hysteretic Regulating (HR) Amplifier is used for a

Quiet/Slow turn-off mechanism. This slow turn-off is initiated

when the sourcing power supply is turned off slowly for

system diagnostics. Under normal operating conditions as

COMP

V

pulls up to 20mV below V (V - 20mV > V ), the

This is the high side connection for the HS Comparator trip

OUT

IN IN OUT

HR Amplifier regulates the gate voltage to keep the 20mV

(V_{FWD_HR}) forward voltage drop across the ORing MOSFET

(Vs - Vd). This will continue until the load current exceeds

the MOSFET ability to deliver the current with Vsd of 20mV.

In this case, Gate will be charged to the full charge pump

level setting (V

). Resistor R , connected between

along with resistor R , provides adjustable

2

TH(HS)

1

COMP and V

OUT

- V trip level (0V to 5V). This provides flexibility to

V

OUT

IN

externally set the desired level depending on particular

system requirement.

voltage (V

) to fully enhance the MOSFET. At this point,

GQP

VSET

the MOSFET will be fully enhanced and behave as a

constant resistor valued at the r . Once V starts to

Low side connection for the HS Comparator trip level setting

A second resistor R connected between VSET and COMP

provides adjustable “V - V

IN

DS(ON)

IN

drop below V

, regulation cannot be maintained and the

2

OUT

output of the HR Amp is pulled high and the gate is pulled

” level along with R .

1

OUT

down to V slowly in less than a 100µs. As a result, the

IN

ORing FET is turned off, avoiding reverse current as well as

voltage and current stresses on supply components.

FN9131.7

October 6, 2011

6

ISL6144

The slow turn-off is achieved in two stages. The first stage

The fault can be detected and isolated by using the ISL6144

and an N-Channel ORing MOSFET. V is compared to

starts with a slow turn-off action and lasts for up to 20µs. The

gate pull down current for the first stage is 2mA. The second

slow turn-off stage completes the gate turn-off with a 10mA

pull down current. The 20µs delay filters out any false trip off

due to noise or glitches that might be present on the supply

line.

IN

V

, and whenever:

COMP

V

< V

;

where

IN

COMP

= V

– V

(EQ. 2)

COMP

TH(HS)

OUT

TH(HS)

is defined below

The gate turn-on and gate turn-off drivers have a 50kHz filter

to reduce the variation in FET forward voltage drop (and FET

gate voltage) due to normal SMPS system switching noises

(typically higher than 50kHz). These filters do not affect the

total turn-on or slow turn-off times.

The fast turn-off mechanism will be activated and the

MOSFET(s) will be turned off very quickly. The speed of this

turn-off depends on the amount of equivalent gate loading

capacitance. For an equivalent Cgs = 39nF. The gate turn-off

time is <300ns and gate pull down current is 2A.

Special system design precautions must be taken to insure

that no AC mains related low frequency noise will be present

at the input or output of ISL6144. Filters and multiple power

conversion stages, which are part of any distributed DC

power system, normally filter out all such noise.

The level of V

(HS Comparator trip level) is adjustable

TH(HS)

by means of external resistors R and R to a value

1

2

theoretically ranging from 0V to 5.3V. Typical values are

0.05V to 0.3V. This is done in order to avoid false turn-off

due to noise or minor glitches present in the DC switching

power supply. The threshold voltage is calculated as

Equation 3:

HS Comparator-Fast Turn-off

There is a High Speed (HS) Comparator used for fast turn-

off of the ORing MOSFET to protect the common bus

against hard short faults at a sourcing power supply output

(refer to Figure 1).

R

1

-------------------------

V

=

V

(EQ. 3)

TH(HS)

REF(VSET)

(R + R )

1

2

Where V

is an internal zener reference (5.3V

REF(VSET)

During normal operation the gate of the ORing MOSFET is

charge pumped to a voltage that depends on whether it is in

the 20mV regulation mode or fully enhanced. In this case:

typical) between V

and VSET pins. R and R must be

1 2

OUT

chosen such that their sum is about 50kΩ. An external

capacitor, C , is needed between V and COMP pins to

2

OUT

provide high frequency decoupling. The HS comparator has

an internal delay time on the order of 50ns, which is part of

the <300ns overall turn-off time specification (with

Cgs = 39nF).

(EQ. 1)

V

= V – I

• r

OUT DS(ON)

OUT

IN

If a dead short fault occurs in the sourcing supply, it causes

to drop very quickly while V is not affected as more

V

IN

OUT

than one supply are paralleled. In the absence of the

ISL6144 functionality, a very high reverse current will flow

from Output to the Input supply pulling down the common

DC Bus, resulting in an overall “catastrophic” system failure.

Gate Logic and Charge Pump

The IC has two charge pumps. The first charge pump

generates the floating gate drive for the N-Channel

MOSFET. The second charge pump output current opposes

the pull down current of the slow turn-off transistor to provide

regulation of the GATE voltage.

FROM

TO SHARED

LOAD

SOURCING

SUPPLY

The presence of the charge pump allows the use of an

N-Channel MOSFET with a floating gate drive. The

GATE

VOUT

VIN

N-Channel MOSFETs normally have lower r

mention cost saving) compared to P-Channel MOSFETs,

allowing further reduction of conduction losses.

(not to

VIN

V

DS(ON)

TH(HS)

R

1

COMP

C

2

HV PASS

AND

CLAMP

-

R

2

+

VSET

BIAS

2A*

BIAS and REF

5.3V

HS

COMP

DRIVER

Bias currents for the two internal zener supplies (HVREF

and VSET) is provided by this block. This block also

provides a 0.6V band-gap reference used in the UV

detection circuit.

R

+ R = 50kΩ

2

1

Undervoltage Comparator

FIGURE 1. HS COMPARATOR

The undervoltage comparator compares HVREF to 0.6V

internal reference. Once it falls below this level the UV

circuitry pulls and holds down the gate pin as long as the

HVREF UV condition is present. Voltage at both VIN and

HVREF pins track each other.

FN9131.7

October 6, 2011

7

ISL6144

Application Considerations

High Voltage Pass and Clamp

A high voltage pass and clamping circuit prevents the high

output voltage from damaging the comparators in case of

ORing MOSFET Selection

Using an ORing MOSFET instead of an ORing diode results

in increased overall power system efficiency as losses

across the ORing elements are reduced. The use of ORing

MOSFETs becomes more important at higher current levels,

as power loss across the traditionally used ORing diode is

very high. The high power dissipation across these diodes

requires special thermal design precautions such as heat

sinks and forced airflow.

quick drop in V . The comparators are running from the 5V

supply between HVREF and V . These devices are rated

IN

for 5V and will be damaged if V

is allowed to be present

OUT

(as the output is powered from other parallel supplies), and

does not fall when V is falling. For example, if V falls to

IN IN

30V, V

remains at 48V and the differential Voltage

OUT

between the “-” and “+” terminals of the comparator would be

18V, exceeding the rating of the devices and causing

permanent damage to the IC.

For example, in a 48V, 40A (1+1) redundant system with

current sharing, using a Schottky diode as the ORing

(auctioneering) device (see Figure 3), the forward voltage

drop is in the 0.4V to 0.7V range. Let us assume it is 0.5V,

power loss across each diode is as shown in Equation 4:

Fault Detection Block

The fault detection block has two monitoring circuits (refer to

Figure 2):

I

1. Gate monitoring detects when the GATE < V + 0.37V

IN

OUT

2

--------------

P

= P

=

⋅ V = 20A ⋅ 0.5V = 10W

loss(D1)

loss(D2)

F

2. V

OUT

monitoring detects when V - 0.41V > V

IN OUT

(EQ. 4)

These two outputs are ORed, inverted, level shifted, and

delayed using an internal filter (t

Total power loss across the two ORing diodes is 20W.

)

FLT

DC/DC

#1

D

INPUT BUS 1

1

The following failures can be detected by the fault detection

circuitry:

0.5V@ 20A

36VDC TO 75 VDC

+OUT1 = 48V

+IN

PC

+OUT

R

10

pb1

C

CIN1

100µF

d1

+S

1. ORing FET off due to dead short in the sourcing supply,

220nF

C

(Note 11)

Figure 14

cs1

1nF

SC

leading to V < V

IN OUT

PR

-IN

2. Shorted terminals of the ORing FET

3. Blown fuse in the power path of the sourcing supply

4. Open Gate terminal

-S

VOUT

(40A)

-OUT

5. HVREF UV

SECONDARY

GROUND

DC/DC

#2

The FAULT pin is not latched off and the pull down will shut

off as soon as the fault is removed and the pin becomes high

impedance. Typically, an external pull-up resistor is

connected to an external voltage source (for example 5V,

3.3V) to pull the pin high, an LED can be used to indicate the

presence of a fault.

INPUT BUS 2

36VDC TO 75 VDC

+OUT2 = 48V

+IN

+OUT

D

R

2

0.5V@ 20A

pb2

C

IN2

100µF

d2

220nF

10

+S

PC

(Note 11)

Figure 14

SC

C

cs2

1nF

PR

-IN

-S

GATE

-

+

-OUT

+

-

FAULT

PRIMARY GROUND

0.37V

VIN

+

-

FIGURE 3. 1 + 1 REDUNDANT SYSTEM WITH DIODE ORing

DELAY

120µs

+

-

If a 5mΩ single MOSFET per feed is used, the power loss

across each MOSFET is as shown in Equation 5:

0.41V

VOUT

LEVEL SHIFT

2

I

OUT

2

⎛

⎝

⎞

⎠

--------------

P

= P

=

⋅ r

DS(ON)

(EQ. 5)

loss(M1)

loss(M2)

FIGURE 2. FAULT DETECTION BLOCK

2

= (20A) ⋅ 5mΩ = 2W

loss(M1)

Total power loss across the two ORing MOSFETs is 4W.

In case of failure of current sharing scheme, or failure of

DC/DC #1, the full load will be supplied by DC/DC #2. ORing

MOSFET M2 or ORing Diode D will be conducting the full

2

FN9131.7

October 6, 2011

8

ISL6144

load current. Power loss across the ORing devices is as

shown in Equation 6:

On the other hand, the most common failures caused by

diode ORing include open circuit and short circuit failures. If

one of these diodes (Feed A) has failed open, then the other

Feed B will provide all of the power demand. The system will

continue to operate without any notification of this failure,

reducing the system to a single point of failure. A much more

dangerous failure is where the diode has failed short. The

system will continue to operate without notification that the

short has occurred. With this failure, transients and failures

on Feed B propagate to Feed A. Also, this silent short failure

could pose a significant safety hazard for technical

(EQ. 6)

P

= I

⋅ V = 40A ⋅ 0.5V = 20W

loss(D2)

loss(M2)

OUT

F

2

= (I

)

⋅ r

= (40A) ⋅ 5mΩ = 8W

DS(ON)

OUT

This shows that worst-case failure scenario has to be

accounted for when choosing the ORing MOSFET. In this

case we need to use two MOSFETs in parallel per feed to

reduce overall power dissipation and prevent excessive

temperature rise of any single MOSFET. Another alternative

personnel servicing these feeds.

would be to choose a MOSFET with lower r

).

DS(ON

“ISL6144 + ORing FET” vs “Discrete ORing FET”

Solution

The final choice of the N-Channel ORing MOSFET depends

on the following aspects:

If we compare the ISL6144 integrated solution to discrete

ORing MOSFET solutions, the ISL6144 wins in all aspects.

The main ones are: PCB real estate saving, cost savings,

and reduction in the MTBF of this section of the circuit as the

overall number of components is reduced.

1. Voltage Rating: The drain-source breakdown voltage

V

has to be higher than the maximum input voltage

DSS

including transients and spikes. Also the gate to source

voltage rating has to be considered, The ISL6144

maximum Gate charge voltage is 12V, make sure the

used MOSFET has a maximum V

rating >12V.

In brief, the solution offered by this IC enhances power

system performance and protection while not adding any

considerable cost. This solution provides both a PCB board

real estate savings and a simple to implement integrated

solution.

GS

2. Power Losses: In this application the ORing MOSFET is

used as a series pass element, which is normally fully

enhanced at high load currents; switching losses are

negligible. The major losses are conduction losses, which

depend on the value of the on-state resistance of the

Setting the External HS Comparator Threshold

Voltage

MOSFET r

, and the per feed load current. For an

DS(ON)

N + 1 redundant system with perfect current sharing, the

per feed MOSFET losses are as shown in Equation 7:

In general, paralleled modules in a redundant power system

have some form of active current sharing, to realize the full

benefit of this scheme, including lower operating

2

I

LOAD

⎛

⎝

⎞

⎠

----------------

(EQ. 7)

P

=

⋅ r

DS(ON)

loss(FET)

N + 1

temperatures, lower system failure rate, and better transient

response when load step is shared. Current sharing is

realized using different techniques; all of these techniques

will lead to similar modules operating under similar

The r

valuealso depends on junction temperature;

DS(ON)

a curve showing this relationship is usually part of any

MOSFET’s data sheet. The increase in the value of the

r

over temperature has to be taken into account.

DS(ON)

conditions in terms of switching frequency, duty cycle, output

voltage and current. When paralleled modules are current

sharing, their individual output ripple will be similar in

amplitude and frequency and the common bus will have the

same ripple as these individual modules and will not cause

any of the turn-off mechanisms to be activated, as the same

3. Current handling capability, steady state and peak, are

also two important parameters that must be considered.

The limitation on the maximum allowable drain current

comes from limitation on the maximum allowable device

junction temperature. The thermal board design has to be

able to dissipate the resulting heat without exceeding the

MOSFET’s allowable junction temperature.

ripple will be present on both sensing nodes (V and

IN

Another important consideration when choosing the ORing

MOSFET is the forward voltage drop across it. If this drop

V

). This would allow setting the high speed comparator

OUT

threshold (V

) to a very low value. As a starting point, a

TH(HS)

approaches the 0.41V limit, which is used in the V

fault

V

of 50mV could be used, the final value of this TH

OUT

TH(HS)

monitoring mechanism, then this will result in a permanent

fault indication. Normally the voltage drop would be chosen

not to exceed a value around 100mV.

will be system dependent and has to be finalized in the

system prototype stage. If the gate experiences false turn-off

due to system noise, the V

has to be increased.

TH(HS)

“ISL6144 + ORing FET” vs “ORing Diode” Solution

The reverse current peak can be estimated as:

V

+ V

SD OS(HS)

“ISL6144 + ORing FET” solution is more efficient, which will

result in simplified PCB and thermal design. It will also

eliminate the need for a heat sink for the ORing diode. This

will result in cost savings. In addition, the ISL6144 solution

provides a more flexible, reliable and controllable ORing

functionality and protects against system fault scenarios

(refer to “Fault Detection Block” on page 8).

TH(HS)

(EQ. 8)

------------------------------------------------------------------------

I

=

reverseP

r

DS(ON)

where:

is the MOSFET forward voltage drop.

V

SD

V

_OS(HS)is the voltage offset of HS Comparator.

FN9131.7

October 6, 2011

9

ISL6144

The duration of the reverse current pulse is a few hundred

nanoseconds and is normally kept well below current rating

of the ORing MOSFET.

Protecting VIN and VOUT from High dv/dt Events

In hot swap applications lacking adequate VIN and VOUT

bulk capacitance and where the ISL6144 is directly

connected to a prebiased bus exposing either the VIN or

VOUT pins directly to high dv/dt transients, these pins must

be filtered to prevent catastrophic damage caused by the

high dv/dt transients. A simple RC filter using a pin 2 series

resistor, of 10 -100Ω and the 100nF or greater best design

practices decoupling capacitor to ground. This will provide a

>1µs rise time on the VIN pin to protect it. A resistor of ~3.3

times the value should be added in series with the VOUT pin

to reduce the introduced HS Vth error.

Reducing the value of V

current amplitude and reduces transients on the common

bus output voltage.

results in lower reverse

TH(HS)

HVREF and COMP Capacitor Values

HVREF CAPACITOR (C1)

this capacitor is necessary to stabilize the HV

and a value of 150nF is sufficient. Increasing this value will

result in gate turn-on time increase.

supply

REF(VZ)

Alternately, the programmed HS Vth can be adjusted upward

COMP CAPACITOR (C2)

by the voltage across R

as described on page 9.

VIN

Placed between V

and COMP pins to provide filtering

OUT

Hot Swapped

Input

Q

1

and decoupling. A 10nF capacitor is adequate for most

cases.

R

in

R

out

~3.3X R

10-100

in

2

16

15

14

VOUT

COMP

VSET

VIN

3

8

HVREF

GND

C

1 >

100nF

ISL6144

FN9131.7

October 6, 2011

10

ISL6144

Typical Performance Curves and Waveforms

12

11

10

32

28

24

75V

48V

75V

48V

12V

10V AND 12V

9

8

7

20

16

12

10V

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (°C)

FIGURE 4. CHARGE PUMP VOLTAGE (V

TEMPERATURE

) vs

GQP

FIGURE 5. REG. AMP FORWARD REGULATION

5.4

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

75V

48V

75V

5.3

5.2

5.1

5.0

48V

10V AND 12V

1122VV

10V

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (°C)

FIGURE 7. VSET VOLTAGE

FIGURE 6. I BIAS CURRENT vs TEMPERATURE

HV

REF(VZ)

6.000

1V/DIV

75V

48V

10V/DIV

5.875

5.750

5.625

5.500

5.375

5.250

V

G

V

IN

10V/DIV

10A/DIV

10V AND 12V

I

IN

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (°C)

FIGURE 9. FIRST SUPPLY START-UP

FIGURE 8. HVREF VOLTAGE

FN9131.7

October 6, 2011

11

Typical Performance Curves and Waveforms (Continued)

r

= 19mΩ, QTOT = 70nC,

r

= 19mΩ, QTOT = 70nC,

DS(ON)

EXTERNAL C

DS(ON)

EXTERNAL C

= 33nF, V

= 55mV

= 33nF, V

= 55mV

GS

TH(HS)

GS

TH(HS)

I

IN2

5A/DIV

V

OUT

IN2

10V/DIV

V

IN2

V

10V/DIV

5V/DIV

10V/DIV

5V/DIV

V

GS2

V

GS2

FIGURE 11. HIGH SPEED TURN-OFF, V = 48V, COMMON

IN

FIGURE 10. HIGH SPEED TURN-OFF, V = 48V, COMMON

IN

LOAD IS SMPS (C

= 100µF) WITH

LOAD IS SMPS (C

= 100µF) WITH

LOAD

EQUIVALENT 4A LOAD

EQUIVALENT 1.3A LOAD

I

IN2

2A/DIV

V

OUT

V

OUT

2V/DIV

10V/DIV

V

IN2

V

GS2

V

IN2

5V/DIV

2A/DIV

V

GS2

5V/DIV

I

IN2

FIGURE 13. SLOW SPEED TURN-OFF, V = 12V, COMMON

IN

FIGURE 12. SLOW SPEED TURN-OFF, V = 48V, COMMON

IN

LOAD IS SMPS (C

= 100µF) WITH

LOAD IS SMPS (C

= 100µF) WITH

LOAD

EQUIVALENT 4A LOAD

Application Circuit

FN9131.7

October 6, 2011

12

ISL6144

(NOTE 13)

DC/DC

#1

INPUT BUS 1

36V TO 75VDC

F1 (NOTE 12)

15A

D (NOTE 10)

1

+OUT1 = 48V

+IN +OUT

R

Sa

pb1

10

Q

1

Sb

C

100µF

C

22µF

IN1

pb1

FDB3632

+S

SC

-S

PC

PR

-IN

C

1

d1

220nF

cs1

1nF

FROM

CB

GATE

150nF

VIN

VOUT

COMP

R

C

2

10nF

1

499

HVREF U1

COMMON BUS “CB”

10A

5V

R

2

47.5k

-OUT

R

ISL6144

3

VSET

FAULT

GND

4.99k

(NOTE 13)

DC/DC

#2

D

(NOTE 10)

F2 (NOTE 12)

15A

INPUT BUS 2

2

+OUT2 = 48V

Sa

36V TO 75VDC

+IN +OUT

R

pb2

10

Q

2

Sb

C

pb2

C

IN2

FDB3632

+S

PC

100µF

22µF

C

FROM

CB

C

3

d2

220nF

SC

GATE

150nF

VIN

VOUT

COMP

C

4

10nF

R

5

499

PR

-S

C

cs2

1nF

U1

ISL6144

HVREF

FAULT

5V

R

6

47.5k

-IN

-OUT

R

4

VSET

GND

4.99k

SECONDARY

PRIMARY

NOTES:

10. D , D are parasitic MOSFET diodes.

1

2

11. Remote Sense pin (+S) on both DC/DC converters has to be connected either directly at the module output (Sa closed) or to the CB point (Sb

closed). Connecting to CB is not recommended as it might cause Fault propagation in case of short circuit on a PS output.

12. F1, F2 are optional and can be eliminated depending on power system configuration and requirements.

13. DC/DC #1, 2 configuration is based on Vicor V48B48C250AN3.

FIGURE 14. APPLICATION CIRCUIT FOR A 1 + 1 REDUNDANT 48V SYSTEM

FN9131.7

October 6, 2011

13

ISL6144

A circuit fault condition is indicated on an open drain FAULT

Using the ISL6144EVAL1Z High Voltage

ORing MOSFET Controller Evaluation

Board

pin. The fault detection circuitry covers different types of

failures; including dead short in the sourcing supply, a

dead-short of any two ORing MOSFET terminals, or a blown

fuse in the power distribution path.

In a multiple supply, fault tolerant, redundant power

distribution system, paralleled power supplies contribute

equally to the load current through various power sharing

schemes. Regardless of the scheme, a common design

practice is to include discrete ORing power diodes to protect

against reverse current flow should one of the power

supplies develop a catastrophic output short to ground. In

addition, reverse current can occur if the current sharing

scheme fails and an individual power supply voltage falls

significantly below the others.

Typical Application

VIN1

9V TO 75V

Q

1

PS_1

C *

DC/DC

1

6

C *

5

GATE

R

C

1

2

V

PU

VIN

VOUT

COMP

VSET

U1

ISL6144

C1

R

3

HVREF

VOUT

R

2

LED1

Although the discrete ORing diode solution has been used

for some time and is inexpensive to implement, it has some

drawbacks. The primary downside is the increased power

dissipation loss in the ORing diodes as power requirements

for systems increase. In some systems this lack of efficiency

results in a cost that surpasses the cost of the ISL6144 and

power FET implementation. The power loss across a typical

ORing diode with 20A is about 10W. Many diodes will be

paralleled to help distribute the heat. In comparison, a FET

with 5mΩ on-resistance dissipates 2W, which constitutes an

80% reduction. When multiplied by the number of paralleled

supplies, the power savings are significant. Another

disadvantage when using an ORing diode would be failure to

detect a shorted or open ORing diode, jeopardizing power

system reliability. An open diode reduces the system to a

single point of failure while a diode short might pose a

hazard to technical personnel servicing the system while

unaware of this failure.

CS

FAULT

GND

RED

VIN2

9V TO 75V

Q

1

PS_2

DC/DC

2

C *

7

C *

8

GATE

U2

ISL6144

HVREF

R

6

V

4

PU

VIN

VOUT

COMP

VSET

C

3

4

R

7

LED2

FAULT

GND

RED

R

= R = 499Ω (5%)

1

6

= R = 47.5kΩ (5%)

2

3

7

= R = 1.21kΩ (5%)

4

C

= C = 150nF (10V)

2

1

3

= C = 10nF (10V)

4

The ISL6144 ORing MOSFET Controller and a suitably

sized N-Channel power MOSFET(s) increase power

distribution efficiency and availability when replacing a

power ORing diode in high current applications. It can be

used in +9V to +75V systems and has an internal charge

pump to provide a floating gate drive for the N-Channel

ORing MOSFET.

C * TO C * = 100nF *(100V) Optional Decoupling Caps

5

8

- LED1, LED2 are red LEDs to indicate a fault, different interfaces

are possible to the FAULT pin.

- V

PU

is an external pull up voltage source. Also, V

can be

OUT

used as the pull up source. In this case if it is higher than 16V,

use a zener diode from the FAULT pin to GND with a clamping

voltage less than the rating of the FAULT pin which is 16V.

The input/output differential trip point “V

OUT

- V ” can be

IN

programmed by two external resistors (R , R or R , R ).

This trip point can be adjusted to avoid false gate trip off due

1

2

6

7

Related Literature

• TB389 (PCB Land Pattern Design and Surface Mount

Guidelines for QFN (MLFP) Packages)

to power supply noise.

The high speed comparator action protects the common bus

from being affected due to individual power supply shorts by

turning off the ORing MOSFET of the shorted feed in less

than 300ns (when using an ORing MOSFET with equivalent

gate to source capacitance equal to 39nF).

• Manufacturer’s MOSFET data sheets

The Hysteretic Regulating (HR) Amplifier provides a slow

turn-off of the ORing MOSFET. This turn-off is achieved in

less than 100µs when one of the sourcing power supplies is

shutdown slowly for system diagnostics, ensuring zero

reverse current. This slow turn-off mechanism also reacts to

output voltage droop, degradation, or power-down.

FN9131.7

October 6, 2011

14

ISL6144

DC/DC CONVERTERS (NOT PART OF THE EVAL BOARD)

ISL6144EVAL1Z CONTROL BOARD

FIGURE 15. TEST SETUP USING DC/DC MODULES

the current if their respective voltages are close to each

ISL6144 Evaluation Board Overview

other). ORing MOSFET’s gate drive voltage, control and

monitoring for each of these feeds are implemented using

the ISL6144.

This section of the data sheet serves as an instruction

manual for the ISL6144EVAL1Z board. It also provides

design guidelines and recommendations for using the

ISL6144 for ORing MOSFET control. The ISL6144EVAL1Z

Control Board has two parallel feeds connected to each

other through N-channel ORing MOSFETs. Each ORing

MOSFET has an ISL6144 connected to it. This board

demonstrates the operation of Intersil’s ISL6144 HV ORing

MOSFET Controller IC in a typical 1 + 1 redundant power

system.

The board has the following features:

• Evaluation of the ISL6144 in a 1 + 1 redundant power

system using a single board

• Has footprint for a total of three parallel MOSFETs per

feed. Number of MOSFETs used will depend on the load

current (on the standard ISL6144EVAL1Z board only one

MOSFET is populated per feed)

To demonstrate the functionality of the ISL6144, two power

supplies with identical output voltages are required as the

input to the ISL6144EVAL1Z board. This will show the ability

of the ISL6144 to provide the gate drive voltage for the

ORing N-Channel MOSFET. The ISL6144 also monitors the

• Allows the user to test turn-on, slow turn-off, fast turn-off

and different fault scenarios

• Visual fault indication with Red LEDs

• Banana Connectors and test points for all inputs, outputs

and IC pins

drain (V

), source (V ) and gate voltages in order to

OUT

IN

provide reverse current protection and protection against

power feeds’ related faults.

• Can be easily connected to the power system prototype

for initial evaluation

Figure 15 shows a test setup used in the characterization of

ISL6144 in a 1 + 1 redundant power system.

Note that the board was designed to handle high load

currents (up to 20A per feed) with the appropriate MOSFET

selection.

ISL6144EVAL1Z Control Board (Rev C)

This board is configured with two input power feeds

connected in parallel for redundancy using ORing

MOSFETs. The ISL6144 allows the two rails to operate in

active ORing mode (This means that both feeds can share

FN9131.7

October 6, 2011

15

ISL6144

(depending on the output capacitance value of the power

supply/module, a local loading resistor might be needed to

help discharge the BPS output capacitor). An output

Input Voltage Range (+9V to +75V)

The ISL6144 can operate in equipment with voltages in the

+9V to +75V range. The ISL6144 can also be used in

systems with negative voltages -9V to -75V, but it has to be

placed on the return (high) side. For example, in ATCA

systems, an ORing of both the low (-48V) and high (-48V

Return) sides is required. In this case the ISL6144 can be

used on the high side.

capacitor C

(equivalent to the capacitor that will be used

OUT

in the final power system solution) is connected to the

Common Bus point (V ). Different types of loads can be

OUT

used (power resistors, electronic load or simply another

DC/DC converter).

Option 2: Using a custom designed DC/DC converter Power

Board which consists of two DC/DC modules connected in

current sharing configuration, each DC/DC module output

can be turned off slowly using the ON/OFF pin or can be

shorted using on-board Power MOSFET (Refer to

The ISL6144 draws bias from both the input and output

sides. External bias voltage rail is not needed and cannot be

used. As soon as the Input voltage reaches the minimum

operational voltage, the internal charge pump turns on and

provides gate voltage to turn-on the ORing FET.

Figure 17). In this case also, similar considerations for C

and type of load apply as in option 1.

OUT

Multiple Feed ORing (ISL6144EVAL1Z)

In today’s high availability systems, two or more power

supplies can be paralleled to provide redundancy and fault

tolerance. These paralleled power supplies operate in an

active ORing mode where all of these supplies share the

load current, depending on the redundancy scheme

implemented in the particular system. The power system

must be able to continue its normal operation, even in the

event of one or more failures of these power supplies. Faults

occurring on the power supply side need to be isolated from

the common bus point connected to the system critical

loads. This fault isolation device is known as the ORing

device. The function of the ORing device is to pass the

forward supply current flowing from the power supply side

and block the reverse fault current. A fault current might flow

if a short occurs on the input side (typically this could be a

power supply output capacitor short). In this case, the input

voltage drops and current may flow in the reverse direction

from the load to the input, causing the common bus to drop

and the system to fail. Although ORing diodes are simple to

implement in such systems, they suffer from many

USED ONLY FOR POWERING THE LEDS

AUX PS*

5V

+

-

PS1_V1 = V

IN1

J4

V

+

J1

5V_AUX

Q

SHORT

IN1

PS1

+48V

PS1_V1RTN

J6

J2

L

GND

C

-

OUT

V

O

A

D

OUT

J3

J7

PS2_V2 = V

IN2

+

V

GND

IN2

PS2

+48V

J8

PS2_V2RTN

GND

ISL6144EVAL1Z

BENCH POWER

SUPPLIES

CONTROL

BOARD

*Auxiliary power supply is used to power the LED circuit. If V

is

OUT

(J5). If V

less than 16V, J1 can be connected directly to V

OUT

higher than 16V, we still can use V

to replace AUX PS, but a

OUT

zener diode has to be connected from FAULT to GND to clamp the

voltage across the pin to 16V or lower.

FIGURE 16. TEST SETUP USING BENCH PS

.

drawbacks, as outlined earlier.

USED ONLY FOR POWERING THE LEDs

+

AUX PS

The ISL6144 (with an external N-Channel MOSFET)

provides an integrated solution to perform the ORing

function in high availability systems, while increasing power

system efficiency at the same time.

-

PS1_V1

J4

V

J4

J1

+

J1

J2

5V_AUX

V

IN1

OUT1

PS1

+48V

DC/DC 1

PS1_V1RTN

J6

J2

J6

GND

L

O

A

D

-

PRI_GND

CS

V

Operating Instructions and Functional

Tests

Test setup for ISL6144EVAL1Z is shown in Figures 16 and

17 with two options for the input power sources.

C

OUT

GND

J7

PS2_V2

J3

J7

+

J3

V

IN2

GND

OUT2

PS2

+48V

DC/DC 2

J8

PS2_V2RTN

J8

-

J9

GND

ISL6144EVAL1Z

Option 1: Using two identical bench power supplies (BPS)

connected directly to the ISL6144EVAL1Z Control Board

(refer to Figure 16). Just make sure to program the voltages

on PS1_V1 and PS2_V2 to identical values so that they

GND

PRI_GND

BENCH POWER

SUPPLIES

POWER MODULES

BOARD*

CONTROL

BOARD

*Power Modules Board can be replaced by bench power supplies or

any discrete DC/DC modules. Just make sure to adjust both V

share the load current. A MOSFET (Q

) is connected at

short

OUT1

close to each other to allow current sharing between the

and V

the Input of one or both feeds as close as possible to the

input connectors of the ISL6144EVAL1Z board. Slow turn-off

of the input BPS can be performed by the on/off button

OUT2

two modules (Refer to option 1 and Figure17).

FIGURE 17. TEST SETUP USING DC/DC MODULES

FN9131.7

October 6, 2011

16

ISL6144

DC/DC Converter Power Board (not part of the

ISL6144EVAL1Z board)

Two-Feed Parallel Evaluation

Two Feed parallel operation verification can be performed

after completion of the single feed evaluations. Make sure

that the two Input power supplies connected to the

ISL6144EVAL1Z board are identical in voltage value.

Identical input voltages are needed to enable the two feeds

to share the load current (In real world power systems,

current sharing is most likely insured by the power

supplies/modules that have an active current sharing

feature).

The DC/DC converter board consists of two DC/DC

converters with independent input voltage rails. In reality, two

identical power supplies can be used in the test setup to

replace this board (contact Intersil Applications Engineering

if you need assistance in your test setup). This DC/DC

converter board is configured for operation at different output

voltage levels depending on the choice of DC/DC modules.

Most evaluation results are provided for a mix of +48V and

+12V input voltages. Any other voltage within the +9V to

+75V range can also be used.

1. Turn-on PS1 and PS2 in sequence (hot plugging is not

recommended). Adjust V

and V close to each

IN1

IN2

other. Verify the input current of both feeds to be within

acceptable current sharing accuracy (~10%). Current

sharing accuracy will be very poor at light loads and

becomes better with higher load currents.

Each DC/DC converter has a low r

DS(ON)

MOSFET

connected in parallel to the output terminals. This MOSFET

is normally off. When turned on it simulates a short across

the output. Another MOSFET is connected at the ON/OFF

pin of the modules to simulate a slow turn-off of the module.

2. Adjust the load current to different values and verify that

both V

(TP1 to TP2) and V

(TP4 to TP5) are close

SD1

SD2

Single-Feed Evaluation

to each other. These two voltages might be different

depending on the amount of load current passing through

each of the two feeds.

The ISL6144EVAL1Z is hooked up to two input power

supplies using test setup shown in Figure 16 or Figure 17.

Note that the ISL6144EVAL1Z is populated with one

FDB3632 MOSFET per feed (Nominal value of the

3. At light loads, I

* r is less than 20mV, the

Load DS(ON)

ISL6144 operates in the forward regulation mode and

gate voltage is modulated as a function of load current.

MOSFET’s r

DS(ON)

is approximately 8mΩ at V = 10V).

GS

When I

*r becomes higher than the regulated

Load DS(ON)

1. Connect the input power supplies, auxiliary 5V power

supply, load and output capacitor to the ISL6144EVAL1Z.

20mV, the charge pump increases and clamps the gate

voltage to the maximum possible charge pump voltage,

V

.

GQP

2. Connect test equipment (Oscilloscope, DMM) to the

signals of interest using on-board test points and scope

probe jacks.

4. Verify the Gate voltage of both MOSFETs V

(TP13 to

GS1

(TP14 to TP21) with different load

TP17) and V

currents.

GS2

3. Turn-on PS1 with V

IN1

= +48V (V can be any voltage

IN1

within +9V to +75V). Turn-on the auxiliary power supply

(AUX PS powering the LED circuit) with +5V. Adjust load

current to 2A. Verify the main operational parameters

such as the 20mV forward regulation at light loads, and

gate voltage as a function of load current.

5. Both LED1 and LED2 are off when both feeds are on.

6. For I = 4A, turn-off V and note that V has

Load

IN2

GS2

has increased from

turned off. LED2 is RED and V

GS1

around 4V to V

.

GQP

7. Turn V

IN2

back on and turn V

off. V is now off.

GS1

IN1

has increased to V

4. The forward voltage drop across the MOSFET terminals

LED1 is RED. V

.

GS2

GQP

V

(TP1-TP2) is equal to the maximum of the 20mV

SD1

forward regulated voltage drop across the source-drain

“V “ or the product of the load current and the

Performance Tests

FWD_HR

MOSFET on-state resistance “I

Performance tests can be carried out after the two feeds

have been verified and found to be operational in active,

1 + 1 redundancy (when two feeds share the load current,

current sharing is ensured by the incoming power supplies.)

These include gate turn-on at power supply start-up, fast

speed turn-off (in case of fast dropping input rail), slow

speed turn-off (in response to slow dropping input rail) and

fault detection in response to different faults.

* r

”.

Load DS(ON)

5. For I

= 2A, V

SD1

is equal to V = 20mV. The

Load

FWD_HR

gate-source voltage is modulated as a function of load

current and MOSFET transconductance. Gate-source

voltage V

(TP13 -TP17) is approximately 4V. In this

GS1

case, LED1 is off. LED2 will be RED as V

is still off.

IN2

6. Increase the load current I

to 4A. Note that V is

Load

DS1

and operation in the 20mV

increased to above V

FWD_HR

forward regulation cannot be maintained. The MOSFET

cannot deliver the required load current with a 20mV

Gate Start-Up Test

constant V

pumped to V

. In this case, gate voltage is fully charge-

(10.6V nominal).

FIRST-FEED START-UP

SD1

GQP

and turn-on V

When the first feed is turned on, as V

rises, conduction

IN1

7. Turn-off V

IN1

and repeat the same tests

occurs through the body diode of the MOSFET. This only

occurs for a short time until the MOSFET gate voltage can

be charge-pumped on. This conduction is necessary for

proper operation of the ISL6144. It provides bias for the gate

IN2

listed above. Make sure the ISL6144 is providing gate

voltage, which is modulated based on the load current.

V

is measured between (TP4-TP5), V is

GS2

SD2

measured between (TP14-TP21).

FN9131.7

October 6, 2011

17

ISL6144

hold off and other internal bias and reference circuitry. The

charge pump circuitry starts functioning as the input voltage

V

= 12V; RESISTIVE LOAD = 5A, C

= 33nF

IN

GSEXT

I

at the V pin reaches a value around 8V. The gate voltage

depends on the load current (as explained in previous

sections), The maximum gate voltage will be clamped to a

IN1

IN

5A/DIV

V

G1

maximum of V

when load current becomes too high to

GQP

5V/DIV

be handled with 20mV across the source-drain terminals.

Overall, it takes less than 1ms to reach the load-dependent

final gate voltage value. Note that the Input voltage cannot

V

be hot swapped and has to rise slowly. A rise time of at least

1ms is recommended for the voltage at VIN pin.

IN1

5V/DIV

V

= 48V; RESISTIVE LOAD = 4A, C

= 33nF

V

IN

GSEXT

WAVEFORMS

OUT

,V ,I

and HV

REF(VZ)

5V/DIV

IN1 G1 IN1

HV

REF(Vz)

5V/DIV

4A

I

IN1

2A/DIV

V

0A

G1

FIGURE 19. FIRST FEED V

START-UP (12V CASE)

IN1

10V/DIV

The start-up tests were done with the addition of an external

gate to source capacitor to demonstrate start-up time with a

total equivalent gate-source capacitance around 39nF.

V

IN1

10V/DIV

SECOND (CONSECUTIVE) FEED START-UP

In this case, the ISL6144 for the second (consecutive) feed

(U4) already has output bias voltage as the first parallel feed

WHEN V REACHES ~ 8V AND HVREF REACHES

IN

3V to 4V, GATE CHARGE PUMP ACTION STARTS

has been turned on and V

is present on the common bus.

OUT

As V

IN2

rises, V rises with it (V is GATE2 voltage with

G2 G2

respect to GND). When V

approaches V

value, Gate 2 is

IN2

IN1

turned. Second feed gate turn-on is faster than the first feed as

V

, V , I

IN1 G1 IN1

and V

WAVEFORMS

OUT

the HVREF capacitor (C ) is already charged.The second or

3

consecutive power supply to be started can be turned on faster

than the first power supply, a rise time of at least 200µs of the

second rail is recommended.

4A

I

IN1

5A/DIV

0A

V

= 48V; RESISTIVE LOAD = 4A, C

= 33nF

GS(EXT)

IN

V

OUT

20V/DIV

I

IN2

2A/DIV

V

OUT

20V/DIV

V

G1

20V/DIV

V

IN1

20V/DIV

IN THIS CASE GATE VOLTAGE IS MEASURED

BETWEEN GATE2 AND GND

V

SECOND GATE TURNS ON ONLY

WHEN V REACHES V

G2

20V/DIV

WHEN V REACHES ~ 8V

AND HVREF REACHES 3V TO 4V

IN

IN2 IN1

GATE CHARGE PUMP ACTION STARTS

V

IN2

20V/DIV

POWER SUPPLY

RELATED DELAY

FIGURE 18. FIRST FEED V

START-UP (48V CASE)

IN1

FIGURE 20. SECOND (CONSECUTIVE) FEED V

IN2

START-UP

FN9131.7

October 6, 2011

18

ISL6144

t

is the High Speed Comparator internal worst-

Gate Fast Turn-off Test

DELAY(HS)

case time delay. The setup in Figure 17 can be used to

perform the Input dead-short test; a pulse generator is

During normal operation, the ISL6144 provides gate drive

voltage for the ORing MOSFET when the Input voltage

exceeds the output voltage. The current flows in the forward

direction from the input to the output. Now, what happens if

the input voltage drops quickly below the output voltage as a

result of a failure on the input sourcing power supply while

the MOSFET remained on? The answer is: If the MOSFET is

kept on, current starts to flow in the reverse direction from

the output to the input. Of course this is not desired nor

acceptable. It will lead to effectively shorting the output and

causing an overall system failure. In order to block this

reverse current, the ISL6144 senses the voltage at both VIN

connected between Gate-Source of Q

(use pulse

SHORT1

mode single shot, set the frequency to <10Hz and pulse

width of approximately 10ms, t = 1µs). Follow steps 1

RISE

through 5 in the two feed parallel operation section. Make

sure that both feeds operate in parallel current sharing

mode. Proceed with the short test by applying the single

pulse to the gate of Q

. Once turned on, Q

SHORT1 SHORT1

shorts V

causing it to fall quickly (in less than 10µs).

IN1

Figures 21, 22 and 23 show the results for different

combinations of C and load current. Make sure to

GS1

shorting-MOSFET terminals as close as

connect the V

IN1

and COMP pins (this is V

voltage reduced by a resistor

OUT

programmable threshold (V

possible to the V -GND (J4 to J6) terminals on the EVAL

board to minimize lead impedance and reduce parasitic

ringing.

IN

), it is programmed to

TH(HS

55mV on the EVAL board and could be adjusted by

changing R₁, R values for both feeds. If V drops below

4

IN

COMP (V

- V

), the High Speed Comparator turns

OUT

TH(HS

V

= V

= 48V;

= 33nF

IN1

RESISTIVE LOAD = 6A, C

IN2

off the gate of the ORing MOSFET very quickly, the gate pull

down current I is 2A. As a result the reverse current flow

gs(ext)

I

IN1

PDH

2A/DIV

is prevented. The maximum turn-off time is less than 300ns

when using an ORing MOSFET(s) with an equivalent gate-

REVERSE CURRENT

source capacitance of 39nF (equivalent to Q

= 390nC at

TOT

V

= 10V).

V

GS

OUT

10V/DIV

On the ISL6144EVAL1Z board, FDB3632 has an equivalent

gate-source capacitance of 8.4nF, some of the tests are

performed while an external gate to source capacitance is

added to demonstrate gate current sink capability.

V

IN1

10V/DIV

V

GS1

5V/DIV

V

= V

= 48V; RESISTIVE LOAD = 4A, C = 0nF

GS(EXT)

IN1

IN2

0.1µs/DIV

V

G2

10V/DIV

FIGURE 22. FAST SPEED TURN-OFF (MOSFET WITH

V

OUT

Q

= 8.4nc) AND 33nF EXTERNAL C

TOT

GS

I

IN1

2A/DIV

10V/DIV

V

= V

= 48V;

= 33nF

GS1

IN1

RESISTIVE LOAD = 6A, C

IN2

2V/DIV

I

gs(ext)

IN1

2A/DIV

REVERSE CURRENT DISSAPPEARS

WHEN GATE IS COMPLETELY OFF

V

G2

10V/DIV

0.1µs/DIV

V

OUT

10V/DIV

FIGURE 21. FAST SPEED TURN-OFF

(MOSFET WITH Q = 8.4nc)

TOT

V

GS1

5V/DIV

Worst-case turn-off time can be calculated as:

V

⎛

⎞

⎟

⎠

0.1µs/DIV

GS

-------------

t

= t

+ C

⎜

toff(WC)

DELAY(HS)

GS

I

(EQ. 9)

⎝

PDH

12V

⎛

⎞

⎠

----------

= 50ns + 39nF

= 284ns

⎝

2A

FIGURE 23. FAST SPEED TURN-OFF (MOSFET WITH

= 8.4nc) AND 33nF EXTERNAL C

Q

TOT

gs

FN9131.7

October 6, 2011

19

ISL6144

The ISL6144EVAL1Z board has V

TH(HS)

of 55mV. It can be

Input Voltage is falling at a slow rate (Figure 24, top scope

shot shows a 20ms fall time for the input voltage).

changed if performance is found to be unacceptable with this

value. V can affect the amplitude of the reverse current

TH(HS)

(short pulse) that might flow before the gate is effectively

turned off (details on how to select V is included in a

V

(Common Bus) remains almost unchanged at around

OUT

48V. It drops by a value equivalent to the increase in the

portion of the load current passing through the remaining

TH(HS)

later section of this application note). The r

and internal

DS(ON)

feed multiplied by the MOSFET’s r

.

DS(ON)

At the beginning of the slow turn-off, the gate drive Voltage

V (measured between the Gate and Source of the

GS1

HS comp offset also contribute to the amplitude of the reverse

current pulse. A short event on a single feed may cause

ringing on the ground pins, the V , and on the V

pins.

IN OUT

This ringing may cause false turn-off on the healthy feeds.

Using decoupling capacitors both at the V and V pins

help in filtering this high frequency ringing and prevent false

turn-off of parallel feeds. Figure 23 shows that the gate of

ORing MOSFET using a differential probe) starts to drop at a

slower rate. This is attributed to the effect of the 20µs

filtering-delay. Afterwards a stronger pull down current starts

and finally the high-speed turn-off completes the gate turn-

off. Current through the turned off feed is also shown to be

positive and the turn-off is complete with no reverse current.

IN OUT

second feed V (measured with respect to ground) is not

G2

affected when feed 1 input is shorted.

Figure 25 shows the same slow turn-off for a 12V input

voltage case.

Power Supply Slow Turn-off

In many cases, a single power feed is turned off for

diagnosis, maintenance or replacement. The Input voltage

V

= V

= 12V

IN2

IN1

drops slowly (most probably in few ms). When voltage at V

IN

pin. The Hysteretic

pin starts dropping with respect to V

OUT

Regulating Amplifier starts pulling down current (I

)

PDL

opposite to the charge pump current. This reduces the gate

voltage gradually until the MOSFET is completely turned off.

The slow turn-off is accomplished with zero reverse current.

An internal 20µs delay filters out any false trip off due to

noise or glitches that might be present on the supply line.

The slow speed turn-off mechanism is shown in Figure 24:

5ms/DIV

V

= V

= 48V

IN2

IN1

ZOOMED IN VIEW

I

IN2

V

OUT

V

OUT

2V/DIV

V

GS2

IN2

V

IN1

2V/DIV

V

GS1 (DIFF PROBE)

5V/DIV

5ms/DIV

ZOOMED IN VIEW

I

IN2

2A/DIV

V

OUT

10V/DIV

I

IN1

2A/DIV

20µs/DIV

V

IN2

10V/DIV

V

GS2

5V/DIV

FIGURE 25. SLOW SPEED TURN-OFF (C

GSTOT

= 8.4nF + 33nF)

20µs/DIV

FIGURE 24. SLOW SPEED TURN-OFF (C

= 8.4nF + 33nF)

GSTOT

FN9131.7

October 6, 2011

20

ISL6144

Fault 3: MOSFET Gate to Source Dead Short

Detection of Power Feed Faults

GATE voltage will be equal to V , GATE <V + 0.37V and a

fault is indicated.

The ISL6144 have two built-in mechanisms that monitor

voltages at VIN, VOUT and GATE pins. The first mechanism

monitors GATE with respect to VIN (with a 410mV threshold)

IN IN

V

= 12V, FAULT PULLED TO +5V

and the second mechanism monitors V with respect to VOUT

IN

(with 370mV threshold). The open-drain FAULT pin will be

pulled low when any of the two above conditions is met.

FAULT

5V/DIV

V

Some of the typical system faults detected by the ISL6144 are:

G1

5V/DIV

Fault 1: Open Fuse at the Input Side

V

IN1

5V/DIV

(Fuse has to be placed before the V tap, between the

IN

power supply and the source of the ORing MOSFET), note

that the EVAL board does not have footprint for installing this

fuse. This feature can be tested by adding a fuse externally.

The open fuse results in near zero current flow through the

ORing MOSFET, only a very low current drawn by the IC

bias will flow. The voltage at VIN pin is effectively

V

OUT

5V/DIV

disconnected from the power source and will start dropping

slowly. The regulated source-drain voltage falls below its

20mV level and the gate of the MOSFET is pulled down and

turned off. GATE will become low and a fault is indicated with

TIME SCALE

100µs/DIV

FIGURE 27. MOSFET GATE TO SOURCE FAULT

internal built in delay (t

).

Fault 2: Drain to Source Short

In this case V is shorted to V , and in theory the voltage

FLT

Fault 4: ORing FET Off Condition

IN OUT

When V < V , the Gate is off to block reverse current

IN OUT

flow. This means that if an ORing feed is not sharing current,

a fault will be indicated. Also if a feed (PS) is off while bias is

drop across the shorted MOSFET terminals will be close to

0V. The Gate will be pulled down and a fault will be

indicated. The resistance of the Drain to Source short

multiplied by the Drain short current must be low enough to

applied from V

to that feed, then a fault is also indicated.

OUT

Fault 5: MOSFET Gate to Drain Dead Short

result in V < V

(refer to data sheet for worst case

values), Otherwise this fault cannot be detected.

SD FWD_HR

In this case, the following condition will be violated GATE

<V + 0.37V and a fault is issued.

IN

V

= 12V, FAULT PULLED TO +5V

IN

V

= 12V, FAULT PULLED TO +5V

IN

FAULT

5V/DIV

FAULT

5V/DIV

V

G1

5V/DIV

V

G1

5V/DIV

V

IN1

5V/DIV

V

IN1

5V/DIV

V

OUT

5V/DIV

V

OUT

5V/DIV

TIME SCALE

100µs/DIV

TIME SCALE

100µs/DIV

FIGURE 26. MOSFET DRAIN TO SOURCE FAULT

FIGURE 28. MOSFET GATE TO DRAIN FAULT

FN9131.7

October 6, 2011

21

ISL6144

For example, in a 48V, 32A (1 + 1) redundant system with

Fault 6: ORing FET Body Diode Conduction

(V - 0.41V > V ). If the voltage drop across the

MOSFET approaches 410mV, a fault will be indicated. Make

sure the selection of the ORing MOSFET takes this fact into

account.

current sharing, using a Schottky diode as the ORing device

(Refer to Figure 29), the forward voltage drop is in the 0.4V to

0.7V range, (let us assume it is 0.5V). The power loss across

each diode is shown in Equation 10:

IN OUT

I

OUT

--------------

Application Considerations and

Component Selection

P

= P

=

⋅ V = 16A ⋅ 0.5V = 8W

loss(D1)

loss(D2)

F

2

(EQ. 10)

“ISL6144 + ORing FET” vs “ORing Diode” Solution

The total power loss across the two ORing diodes is 16W.

“ISL6144 + ORing FET“ solution is more efficient than the

“ORing Diode” Solution, which will result in simplified PCB

and thermal design. It will also eliminate the need for a heat

sink for the ORing diode. This will result in cost savings. In

addition is the fact that the ISL6144 solution provides a more

flexible, reliable and controllable ORing functionality and

protects against system fault scenarios (Refer to the “Fault

Detection Block” on page 8.)

D

1

0.5V@ 16A

INPUT BUS 1

+IN1 = 48V

DC/DC

1

V

OUT

(32A)

CS

D

2

0.5V @ 16A

INPUT BUS 2

+IN2 = 48V

DC/DC

2

On the other hand the most common failures caused by

diode ORing include open circuit and short circuit failures. If

one of these diodes (Feed A) has failed open, then the other

Feed B will provide all of the power demand. The system will

continue to operate without any notification of this failure,

reducing the system to a single point of failure. A much more

dangerous failure is where the diode has failed short. The

system will continue to operate without notification that the

short has occurred. With this failure, transients and failures

on Feed B propagate to Feed A. Also, this silent short failure

could pose a significant safety hazard for technical

FIGURE 29. 1 + 1 REDUNDANT SYSTEM WITH DIODE ORING

If we use a 4.5mΩ MOSFET (refer to Figure 30), the nominal

Power loss across each MOSFET is:

2

I

OUT

2

⎛

⎝

⎞

⎠

--------------

P

= P

=

⋅ r

DS(ON)

loss(M1)

loss(M2)

(EQ. 11)

2

= (16A) ⋅ 4.5mΩ = 1.152W

lossNOM(M1)

The total power loss across the two ORing MOSFETs is

2.304W.

personnel servicing these feeds.

In case of failure of current sharing scheme, or failure of

DC/DC 1, the full load will be supplied by DC/DC 2. ORing

“ISL6144 + ORing FET” vs “Discrete ORing FET”

Solution

MOSFET M2 or ORing Diode D will be conducting the full

2

If we compare the ISL6144 integrated solution to discrete

ORing MOSFET solutions (with similar performance

parameters), the ISL6144 wins in all aspects, the main ones

being simplicity of an integrated solution, PCB real estate

saving, cost savings, and reduction in the MTBF of this section

of the circuit as the overall number of components is reduced.

load current. Power lost across the ORing devices are:

P

= I

⋅ V = 32A ⋅ 0.5V = 16W

(EQ. 12)

lossMAX(D2)

lossMAX(M2)

OUT

F

2

P

= (I

)

⋅ r

= (32A) ⋅ 4.5mΩ = 4.6W

DS(ON)

OUT

(EQ. 13)

In brief, the solution offered by this IC enhances power

system performance and protection while not adding any

considerable cost, on the contrary saving PCB board real

estate and providing a simple to implement integrated

solution.

M1

4.5mΩ

0.072V @ 16A

INPUT BUS 1

+IN1 = 48V

DC/DC

1

V

OUT

(32A)

CS

M2

ORing MOSFET Selection

4.5mΩ

0.072V@ 16A

Using an ORing MOSFET instead of an ORing diode results

in increased overall power system efficiency as losses across

the ORing elements are reduced. The benefit of using ORing

MOSFETs becomes even more significant at higher load

currents as power loss and forward voltage drop across the

traditionally used ORing diode is increased. The high power

dissipation across these diodes requires paralleling of many

diodes as well as special thermal design precautions such as

heat sinks (heat dissipating pads) and forced airflow.

INPUT BUS 2

+IN2 = 48V

DC/DC

2

FIGURE 30. 1+1 REDUNDANT SYSTEM WITH MOSFET ORING

FN9131.7

October 6, 2011

22

ISL6144

This shows that worst-case failure scenario has to be

accounted for when choosing the ORing MOSFET. In both

cases, more than one ORing MOSFET/diode has to be

paralleled on each feed. Using parallel devices reduces

power dissipation per device and limits the junction

temperature rise to acceptable safe levels. Another

• Current handling capability, steady state and peak, are

also two important parameters that must be considered.

The limitation on the maximum allowable drain current

comes from limitation on the maximum allowable device

junction temperature. The thermal board design has to be

able to dissipate the resulting heat without exceeding the

MOSFET’s allowable junction temperature.

alternative is to choose a MOSFET with lower r

(Refer to Tables 1 and 2 for some examples).

DS(ON)

Suppose P

= 1W in a D2PAK MOSFET, junction to

Loss

ambient thermal resistance R

2

= +43°C/W (with 1 inch

θJA

= +175°C, r

If parallel MOSFETs are used on each feed, make sure to

use the same part number. Also it is preferable to have parts

from the same lot to insure load sharing between these

paralleled devices.

copper pad area), T

= 4.5mΩ,

JMAX

DS(ON)

maximum ambient board temperature = +85°C.

We need to make sure that the MOSFET’s junction

temperature during operation does not exceed the maximum

allowable device junction temperature.

The final choice of the N-Channel ORing MOSFET depends

on the following aspects:

T = T

A_max

+ P

Loss

• R

θJA

J

• Voltage Rating: The drain-source breakdown voltage

V

has to be higher than the maximum input voltage,

T = +85°C+1W. +43°C/W = +128°C

J

DSS

including transients and spikes. Also, the gate to source

voltage rating has to be considered. The ISL6144

maximum Gate charge voltage is 12V. Make sure the used

T < T

J

JMAX

In the example of Figure 30 with a load of 32A, at least 3

MOSFETs with r = 4.5mΩ are paralleled to limit the

MOSFET has a maximum V

rating >12V.

GS

DS(ON)

dissipation to below 1W and operate with safe junction

temperature.

• Power Losses: In this application, the ORing MOSFET is

used as a series pass element, which is normally fully

enhanced at high load currents. Switching losses are

negligible. The major losses are conduction losses, which

depend on the value of the on-state resistance of the

Tables 1 and 2 show MOSFET selection for some typical

applications with different input voltages and load currents in

a 1 + 1 redundant power system (a maximum of 1W of

power dissipation across each MOSFET is assumed).

MOSFET r

, and the per feed load current. For an

DS(ON)

N + 1 redundant system with perfect current sharing, the

per feed MOSFET losses are:

For a 48V Input:

2

I

LOAD

N + 1

⎛

⎝

⎞

⎠

(EQ. 14)

----------------

P

=

⋅ r

DS(ON)

loss(FET)

TABLE 1. INPUT VOLTAGE = 48V

I

MOSFET PART NUMBER

N (Note 13)

Load_Max

• The final MOSFET selection has to be based on the worse

case current when the system is reduced to N parallel

supplies due to a permanent failure of one unit. The

remaining units have to provide the full load current. In this

case, losses across each remaining ORing MOSFET

become Equation 15:

8A

FDB3632 (Note 14)

SUM110N10-08 (Note 15)

1

16A

32A

FDB3632 (Note 14)

SUM110N10-08

FDB045AN08A0 (Note 16)

2

1

FDB3632 (Note 14)

SUM110N10-08

FDB045AN08A0

4

3

2

I

LOAD

N

⎛

⎝

⎞

⎠

----------------

P

=

⋅ r

DS(ON)

(EQ. 15)

loss(FET)

NOTES:

13. Number of parallel MOSFETs per feed

• In the particular cases illustrated in the previous examples

of Figures 29 and 30 with N = 1, each of the two ORing

feeds have to be able to handle the full load current.

14. V

15. V

16. V

= 100V;I = 80A; r

= 9mΩ

DSS

D

DS(ON)

= 100V; I = 110A; r

= 9.5mΩ

D

DS(ON)

= 4.5mΩ

DS(ON)

• The MOSFET’s r

DS(ON)

value also depends on junction

= 75V; I = 80A; r

D

temperature; a curve showing this relationship is usually

part of any MOSFET’s data sheet. The increase in the

value of the r

account.

over-temperature has to be taken into

DS(ON)

FN9131.7

October 6, 2011

23

ISL6144

For a 12V to 24V Input:

The duration of the reverse current pulse is in the order of a

few hundred nanoseconds and is normally kept well below

the current rating of the ORing MOSFET.

TABLE 2. INPUT VOLTAGE = 12V TO 24V

I

MOSFET PART NUMBER

N

Load_Max

Reducing the value of V

current amplitude and reduces transients on the common

bus voltage.

results in lower reverse

TH(HS)

15A

IRF1503S (Note 17)

SUM110N03-03P (Note 18)

STB100NF03L-03 (Note 19)

1

40A

75A

IRF1503S

SUM110N03-03P

STB100NF03L-03

2

Just a reminder, this is not an operating scenario, but it is

rather a fault scenario and should not occur frequently. As

explained above, different power supplies have different

IRF1503S

SUM110N03-03P

STB100NF03L-03

3

noise spectrum and might need adjustment of the V

.

TH(HS)

The following procedure can be used for V

selection:

TH(HS)

NOTES:

Choose a value of V

such that the net HS comparator

TH(HS)

threshold voltage is positive to allow turn-off only when V

17. V

18. V

19. V

= 30V; I = 190A; r

= 3.3mΩ

= 2.6mΩ

= 3.2mΩ

DSS

D

DS(ON)

IN

is lower than COMP. Take into account the worst-case of the

HS Comp offset (V = +25mV to -40mV). A good

= 30V; I = 110A; r

D

= 30V; I = 100A; r

D

OS(HS)

starting value is 55mV. The sum of R and R is not to

20. All Above listed r

DS(ON)

values are at V

= 10V

GS

1

2

exceed 50kΩ. It is suggested to choose R = 47.5kΩ and

2

Another important consideration when choosing the ORing

MOSFET is the forward voltage drop across the drain-

source. If this drop approaches the 0.41V limit, (which is

calculate R according to Equation 17:

1

V

TH(HS)

----------------------------------------------------------------

R

=

R

(EQ. 17)

1

2

V

– V

TH(HS)

used in the V

fault monitoring mechanism), this will

REF(VSET)

OUT

result in a permanent fault indication. Normally, this voltage

drop is chosen to be less than 100mV.

R = 499Ω

1

R resistor connected between VOUT and COMP pins

Setting the External HS Comparator

Threshold Voltage

1

R resistor connected between COMP and VSET pins

2

Typically, DC/DC modules used in redundant power systems

have some form of active current sharing to realize the full

benefit of this scheme including lower operating

V

= 5.3V

REF(VSET)

1. Operate all parallel feeds in current sharing mode (either

by using current sharing techniques or by simply

adjusting the voltages very close to each other for natural

current sharing).

temperatures, lower system failure rate, as well as better

transient response when load step is shared. Current

sharing is realized using different techniques; all of these

techniques will lead to similar modules operating under

similar conditions in terms of switching frequency, duty cycle,

output voltage and current. When paralleled modules are

current sharing, their individual output ripple will be similar in

amplitude and frequency and the common bus will have the

same ripple as these individual modules and will not cause

any of the turn-off mechanisms to be activated as the same

2. Vary the load current from 1A to its maximum value,

monitor the gate voltages, and make sure all gates are on

(note that at very light loads the current sharing scheme

might stop functioning and only one feed carries this light

current, at this point gate voltages will be just above the

gate threshold, and even maybe one gate will be on while

the others are not).

3. If at medium to maximum load currents all feeds have

ripple will be present on both sensing nodes (V and

IN

their gates on, then the chosen V

is suitable.

TH(HS)

V

). This would allow setting the high speed comparator

OUT

4. If only one feed has its gate on, the threshold value is too

low and the gate is turning off due to power supply noise

and needs to be increased. Also, the feeds may not be

sharing the load current due to discrepancy in output

voltages and current sharing failure.

threshold (V

) to a very low value. As a starting point, a

TH(HS)

V

of 55mV could be used, the final value of this TH

TH(HS)

will be system dependent and has to be finalized in the

system prototype stage. If the gate experiences false turn-off

due to system noise, the V

has to be increased.

TH(HS)

5. Verify the current sharing scheme and output voltages. If

the output voltages and currents of each feed are equal

The reverse current peak can be estimated as:

but one or more of the gates is still off, increase V

TH(HS)

by increasing R in 250Ω to 500Ω increments (this

V

+ V ±V

SD OS(HS)

1

TH(HS)

(EQ. 16)

----------------------------------------------------------------------

I

=

; where

REVERSEP

increases V

by 25mV to 50mV) until all feeds have

r

TH(HS)

DS(ON)

their FETs turned on.

V

is the MOSFET forward voltage drop

SD

V

_OS(HS)is the voltage offset of HS Comparator

FN9131.7

October 6, 2011

24

ISL6144

Q

1

PRIME_PS

START

= 55mV

C *

5

C *

6

SET V

R

TH(HS)

= 499Ω

GATE

R

1

VIN

VOUT

= 47.5kΩ

5V

2

C

2

C

ISL6144

R

1

HVREF

R

3

COMP

VSET

VOUT

R

2

LED1

FAULT

GND

RED

OPERATE ALL FEEDS IN

CURRENT SHARING MODE

Q

2

BACKUP_PS

C *

(V

IN1

= V

=...= V

)

INn

IN2

n = N+1

C *

7

8

GATE

VIN

VOUT

5V

C

ISL6144

HVREF

R

C

3

6

4

R

4

COMP

VSET

R

7

LED2

FAULT

GND

RED

INCREASE

NO

COMPARE GATE-SOURCE

VOLTAGES

V

TH(HS)

(BY INCREASING

R1 ONLY)

V

≅ V

GS2

≅...V

GS1

GSn

FIGURE 32. USING ISL6144 FOR BACKUP REDUNDANCY

Remote Sense in Redundant Power

Systems

YES

Remote output voltage sensing is a feature implemented in

most of today’s power supplies. This feature is used to

compensate for any resistive voltage drops between the

power supply output and the load-connection point. The

remote sensing pin (RS/+S) must be connected as close as

possible to the load in order to compensate for any resistive

voltage drops across the power path from the power supply

output to the load. The output of many such power supplies

can be connected in parallel to provide redundancy and fault

tolerance. An ORing device (MOSFET/Diode) is typically

used to provide the required isolation of any fault on the

power supply side from propagating to the load side. In this

case it is not recommended to connect the remote sense

pins of the parallel units to the Common Bus point (at load

terminals), as this can provide an alternative path for fault

currents. The remote sense pins can be connected on the

input side of the ORing device to compensate for any drop

prior to it. Using an ORing MOSFET (compared to an ORing

diode) reduces the forward voltage drop. By using a low

STOP

USE CURRENT VALUES of R

1

AND V

TH(HS)

FIGURE 31. SELECTING V

TH(HS)

VALUE

Configuring ISL6144 for Backup

Redundancy (Rail Selector)

The ISL6144 can be used as a rail selector in applications

with backup redundancy. In this case, the backup power

source voltage (for example battery) should be selected in

such a manner that it is lower than the prime source voltage.

Prime_PS

> Backup_PS

Also, the voltage difference between the two rails has to be

higher than the High Speed Comparator threshold voltage.

Prime_PS - Backup_PS >> V

TH(HS)

r

N-Channel ORing MOSFET in redundant power

DS(ON)

systems, the forward voltage drop can be reduced to less

than 100mV. This is another advantage over the ORing

diode solution (that has 400mV to 600mV drop) when tight

regulation is imposed on the Common Bus voltage. If remote

sense is absolutely required, one has to make sure that it will

not lead to fault propagation when one power supply output

is shorted. The remote sense configuration has to be looked

at and design precautions has to be made to make sure the

redundancy and fault tolerance are not compromised by the

remote sense connection to the Common Bus.

FN9131.7

October 6, 2011

25

ISL6144

SOURCE1 - TP1, TP17

PCB Layout Considerations

The ISL6144EVAL1Z uses a 4 layer PCB with 1oz external

layers and 2oz internal layers, dedicated ground and power

planes are used to insure good efficiency and EMC

performance. Other layer stack-up and thickness is possible

depending on the particular power system.

DRAIN1 - TP2, TP18

GATE1 - TP13

HVREF1 - TP9

COMP1 - TP11

VSET1 - TP10

FAULT1 - TP3

The power traces are designed to handle at least 20A of

load per feed. Power and ground planes are made of 2oz

copper and external signal/power layers are 1oz copper.

The loop area for all power traces is minimized to reduce

parasitic inductance.

V

2 - J7

IN

SOURCE2 - TP4, TP21

DRAIN2 - TP5, TP22

GATE2 - TP14

A ground island can be created under the IC and connected

to the power ground at a single point for reduction of noise

that may be injected from the power ground into the IC

ground.

HVREF2 - TP8

Component Selection Summary

COMP2 -TP12

Component selection is listed for one feed and is applicable

for all other parallel feeds.

VSET2 - TP7

FAULT2 - TP6

R , R - are resistors that define the HS comparator

1

2

V

- J2 and J5 (connect to J1 when V

replace LED

OUT

threshold voltage used in the high speed turn-off. The sum of

OUT

AUX PS)

R1+ R2 ≅ 50kΩ. R1 and R2 are found using Equation 17.

GND - J3, J6, J8, TP24-TP27

V+5V - (AUX PS for LEDs) - J1

R - is a pull-up resistor on the FAULT pin that can be used if

3

LED1 is not used. FAULT is an open drain that can be used

to interface with an optocoupler, LED or directly to a logic

circuit. This resistor is not populated on the EVAL board.

R - is the FAULT pin LED current limit resistor, R4 is chosen

4

to have an LED current of about 4mA.

C - is the HVREF Capacitor, placed between VIN and

1

HVREF pins, this capacitor is necessary to stabilize the

HV

supply and a value of 150nF is sufficient.

Increasing this value will result in gate turn-on time increase.

REF(VZ)

C - is the COMP Capacitor, Placed between VOUT and

2

COMP pins to provide filtering and decoupling. A 10nF

capacitor is adequate for most cases.

C , C - are VIN and VOUT local decoupling capacitors,

5

6

help immunize the pins against transients that might result in

case of fast speed gate turn-off.

Q -Q - are ORing MOSFET(s), number of paralleled

1

3

MOSFETs depends on device r

, maximum allowable

DS(ON)

losses and junction temperature of the ORing MOSFETs.

U3 - is Intersil’s ISL6144 High Voltage ORing MOSFET

Controller IC.

LED1 - is a red LED used to indicate first feed faults. When

V

1 is off while V and auxiliary 5V supply are present

OUT

IN

LED1 will be red.

List of Test Points and Connectors

1 - J4

V

IN

FN9131.7

October 6, 2011

26

ISL6144

ISL6144EVAL1Z Schematics

DNP

Q3

V

AUX1

J1

EXTERNAL 5V

DNP

V + 5V

Q

2

FDB3632

VIN1

DRAIN1

TP18

SOURCE1

Q

1

TP17

J4

GATE1

VIN1

FROM PS1

TP1

U3

TP2

TP13

2

VOUT

COMP

VIN

C

10nF

10V

R

499

2

1

V

AUX1

C

1

TP28

VIN1

4

150nF

15

14

13

12

3

10V

TP9

R

3

HVREF

2

R

3

4.99k

DNP

R

47.5k

TP11

2

1.21k

ISL6144

4

J6

LED1

VSET

NC8

NC1

NC2

NC3

NC4

GND

5

6

NC7

C

7

100nF

100V

TP10

11

NC6

NC5

C

5

7

8

100nF

100V

TP3

TP24

10

9

FAULT

VOUT

TP15

FAULT INDICATION

LED AND PULL UP

Q

DNP

6

2

4

VOUT

TP25 TP28

GND

Q

5

DNP

FDB3832

SOURCE2

VIN2

J7

Q

4

DRAIN2

TP22

VIN2

FROM PS2

TP4

TP21

TP5

GATE2

TP29

VIN2

4

2

TP14

U4

2

16

15

VOUT

COMP

VSET

VIN

V

AUX1

R

C

4

10nF

10V

C

6

3

J8

150nF

10V

499

R

3

4

9

R

47.5k

HVREF

7

R

1.21k

8

ISL6144

C

TP12

6

4.99k

DNP

14

100nF

C

8

NC1

NC2

NC3

NC4

GND

TP8

VOUT

LED2

13

12

11

100V

100nF

100V

J5

TP7

5

6

NC7

NC6

10

9

7

8

TP6

NC5

TP27

FAULT

FN9131.7

October 6, 2011

27

ISL6144

Bill of Materials

TABLE 3. BILL OF MATERIALS

SIZE, VALUE, RATING

COMPONENT

NAME

DESCRIPTION/COMMENTS

CONTROL BOARD BOM

R , R

V

Programming Resistor

499Ω, RNC55, 1/8W

47.5kΩ, 0603, 1/8W

4.99kΩ, 0603, 1/8W

TH on EVAL board, could be replaced by SMT

1

6

7

8

9

TH(HS)

R , R

SMT, 0603

2

R , R

FAULT Pull-up Resistor

SMT, 0603 (DNP)

3

R , R

FAULT LED Current Limit Resistor 1.21kΩ, 0603, 1/8W

SMT, 0603 (used with LED connected to +5V)

4

LED1

LED2

Feed 1 Fault Indication RED LED

Feed 2 Fault Indication RED LED

HVREF Capacitor

Red LED, 0805 ceramic

150nF, SM1206, 10V

SMT

C , C

1

3

4

6

8

3

C , C

COMP Decoupling Capacitor

10nF, SM0805, 10V

2

C , C

V

Pin Decoupling Capacitor

100nF, SM1206, 100V

FDB3632, 100V, 9mΩ, D2PAK

5

IN

C , C

V

Pin Decoupling Capacitor

OUT

7

Q -Q

Feed 1 ORing MOSFET(s)

Q2, Q3 - DNP (populate for higher current

applications if needed)

1

Q -Q

Feed 2 ORing MOSFET(s)

FDB3632, 100V, 9mΩ, D2PAK

Q5, Q6 - DNP (populate for higher current

applications if needed)

4

6

U , U

ORing MOSFET Controller

ISL6144IV, 10V to 75V

ISL6144IR, 10V to 75V

TSSOP16

3

4

U , U

20 Ld QFN 5x5 - DNP (alternative footprint)

5

6

NOTE: DNP = Do Not Populate

FN9131.7

October 6, 2011

28

ISL6144

Package Outline Drawing

M16.173

16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 2, 5/10

A

1

3

5.00 ±0.10

SEE DETAIL "X"

9

16

6.40

PIN #1

I.D. MARK

4.40 ±0.10

2

3

0.20 C B A

1

8

B

0.09-0.20

0.65

TOP VIEW

END VIEW

1.00 REF

-

0.05

H

C

0.90 +0.15/-0.10

1.20 MAX

SEATING

PLANE

GAUGE

PLANE

0.25 +0.05/-0.06

0.25

5

0.10

C B A

M

0.10 C

0°-8°

0.60 ±0.15

0.05 MIN

0.15 MAX

SIDE VIEW

DETAIL "X"

(1.45)

NOTES:

1. Dimension does not include mold flash, protrusions or gate burrs.

Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.

2. Dimension does not include interlead flash or protrusion. Interlead

flash or protrusion shall not exceed 0.25 per side.

3. Dimensions are measured at datum plane H.

(5.65)

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Dimension does not include dambar protrusion. Allowable protrusion

shall be 0.08mm total in excess of dimension at maximum material

condition. Minimum space between protrusion and adjacent lead

is 0.07mm.

(0.65 TYP)

(0.35 TYP)

6. Dimension in ( ) are for reference only.

TYPICAL RECOMMENDED LAND PATTERN

7. Conforms to JEDEC MO-153.

FN9131.7

October 6, 2011

29

ISL6144

Quad Flat No-Lead Plastic Package (QFN)

Micro Lead Frame Plastic Package (MLFP)

L20.5x5

20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

A

A1

A2

A3

b

0.80

0.90

-

0.02

-

0.65

9

0.20 REF

9

0.23

2.95

0.30

0.38

3.25

5, 8

D

5.00 BSC

-

D1

D2

E

4.75 BSC

9

3.10

7, 8

5.00 BSC

-

E1

E2

e

4.75 BSC

9

3.10

7, 8

0.65 BSC

-

k

0.20

0.35

-

0.60

20

5

-

L

0.75

8

N

2

Nd

Ne

P

3

5

3

-

0.60

12

9

θ

-

9

Rev. 4 11/04

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Compliant to JEDEC MO-220VHHC Issue I except for the "b"

dimension.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9131.7

October 6, 2011

30


型号：	ISL6144IVZAT
厂家：	RENESAS TECHNOLOGY CORP
描述：	IC 2 A BUF OR INV BASED MOSFET DRIVER, PDSO16, ROHS COMPLIANT, PLASTIC, TSSOP-16, MOSFET Driver 驱动光电二极管接口集成电路驱动器
文件：	总30页 (文件大小：1179K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6144IVZAT [RENESAS]

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