ISL61851CCBZ-T7 [RENESAS]
POWER SUPPLY SUPPORT CKT;
| 型号： | ISL61851CCBZ-T7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | POWER SUPPLY SUPPORT CKT |
| 文件： | 总20页 (文件大小：774K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual USB Port Power Supply Controller
ISL6185
Features
The ISL6185 USB power controller family provides fully
independent overcurrent (OC) fault protection for two or more
USB ports.
• 2.5V to 5V Operating Range
• 71mΩ Integrated Power P-channel MOSFET Switches
• Continuous Current Options for 0.6A, 1.1A, 1.5A and 1.8A
This product family consists of sixteen individual functional
product variants and three package options. It is operation
rated for a nominal +2.5V to +5V range and is specified over the
full commercial and industrial temperature ranges.
• Thermally Insensitive 12ms of Current Limiting Prior to
Turn-Off
• Output Discharges with Reverse Current Blocking When
Disabled
Each ISL6185 type incorporates in a single package two 71mΩ
P-channel MOSFET power switches for power control. Each
features internal current monitoring, accurate current limiting,
and current limited delay to turn-off, for system supply
protection along with control and communication I/O.
• Latch-off or Auto Restart Options
• 1µA Off-State Supply Current
• Enable Polarity Options
• Industry-standard Pin for Pin SOIC, and Smaller DFN Packages
Available
The ISL6185 family offers product variants with specified
continuous output current levels of 0.6A, 1.1A, 1.5A or 1.8A; enable
active high or low inputs; and latch off or automatic retry after
overcurrent turn-off, making these devices well suited for many
low-power applications.
• UL Recognized, File Number: E333469
Applications
• USB 1, 2, 3 Port Power Management
This family of ICs is offered in an industry-standard SOIC pinout
and also in the 70% smaller 3x3 DFN packages providing similar
or enhanced performance in the smallest possible package.
• Low Power (18W) Electronic Circuit Limiting and Breaker
D+
D-
USB
PORT 1
U
S
B
VBUS
1.3
1.2
1.1
1.0
0.9
0.8
0.7
OUT_1
ENABLE_1
FAULT_1
VIN
C
O
N
T
+5V
GND
R
O
L
ISL6185
FAULT_2
L
E
R
ENABLE_2
OUT_2
VBUS
USB
PORT_2
D+
D-
-40
-25
0
25
45
75
85
115
TEMPERATURE (°C)
USB PORT POWER
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. NORMALIZED r
TEMPERATURE
DS(ON)
CHARACTERISTIC CURVE
March 8, 2012
FN6937.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2010, 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL6185
Simplified Block Diagram
CHANNEL 1 LIKE CHANNEL 2
GND
VIN
FAULT_1
OUT_1
-
-V
comp
+
POR
EN_1
EN_2
CURRENT AND TEMP.
MONITORING, GATE,
DELAY & OUTPUT CONTROL
LOGIC
OUT_2
FAULT_2
Ordering Information
V
= 5V
IN
PART
NUMBER
(Notes 1, 2, 3)
MAXIMUM
CONTINUOUSIOUT
(A)
EN/EN
INPUT
LATCH/AUTO
RETRY
TEMP.
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
PART MARKING
61851A CBZ
61851B CBZ
61851C CBZ
61851D CBZ
61851E CBZ
61851F CBZ
61851G CBZ
61851H CBZ
61851I CBZ
61851J CBZ
61851K CBZ
61851L CBZ
52AC
ISL61851ACBZ
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
0.6
0.6
1.1
1.1
0.6
0.6
1.1
1.1
1.5
1.5
1.5
1.5
0.6
0.6
1.1
1.1
0.6
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
M8.15
ISL61851BCBZ
ISL61851CCBZ
ISL61851DCBZ
ISL61851ECBZ
ISL61851FCBZ
ISL61851GCBZ
ISL61851HCBZ
ISL61851ICBZ
ISL61851JCBZ
ISL61851KCBZ
ISL61851LCBZ
ISL61852ACRZ
ISL61852BCRZ
ISL61852CCRZ
ISL61852DCRZ
ISL61852ECRZ
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
52BC
52CC
52DC
52EC
FN6937.3
March 8, 2012
2
ISL6185
Ordering Information(Continued)
V
= 5V
IN
PART
NUMBER
(Notes 1, 2, 3)
MAXIMUM
CONTINUOUSIOUT
(A)
EN/EN
INPUT
LATCH/AUTO
RETRY
TEMP.
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
PART MARKING
52FC
ISL61852FCRZ
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
0.6
1.1
1.1
1.5
1.5
1.5
1.5
0.6
0.6
1.1
1.1
0.6
0.6
1.1
1.1
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
0.6
0.6
1.1
1.1
0.6
0.6
1.1
1.1
1.5
1.5
1.5
1.5
0.6
0.6
1.1
1.1
0.6
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
L8.3x3J
ISL61852GCRZ
ISL61852HCRZ
ISL61852ICRZ
ISL61852JCRZ
ISL61852KCRZ
ISL61852LCRZ
ISL61853ACRZ
ISL61853BCRZ
ISL61853CCRZ
ISL61853DCRZ
ISL61853ECRZ
ISL61853FCRZ
ISL61853GCRZ
ISL61853HCRZ
ISL61853ICRZ
ISL61853JCRZ
ISL61853KCRZ
ISL61853LCRZ
ISL61853MCRZ
ISL61853NCRZ
ISL61853OCRZ
ISL61853PCRZ
ISL61851AIBZ
ISL61851BIBZ
ISL61851CIBZ
ISL61851DIBZ
ISL61851EIBZ
ISL61851FIBZ
ISL61851GIBZ
ISL61851HIBZ
ISL61851IIBZ
ISL61851JIBZ
ISL61851KIBZ
ISL61851LIBZ
ISL61852AIRZ
ISL61852BIRZ
ISL61852CIRZ
ISL61852DIRZ
ISL61852EIRZ
52GC
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
M8.15
52HC
52IC
52JC
52KC
52LC
53AC
53BC
53CC
53DC
53EC
53FC
53GC
53HC
53IC
53JC
53KC
53LC
53MC
53NC
53OC
53PC
61851A IBZ
61851B IBZ
61851C IBZ
61851D IBZ
61851E IBZ
61851F IBZ
61851G IBZ
61851H IBZ
61851I IBZ
61851J IBZ
61851K IBZ
61851L IBZ
52AI
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
52BI
52CI
52DI
52EI
FN6937.3
March 8, 2012
3
ISL6185
Ordering Information(Continued)
V
= 5V
IN
PART
NUMBER
(Notes 1, 2, 3)
MAXIMUM
CONTINUOUSIOUT
(A)
EN/EN
INPUT
LATCH/AUTO
RETRY
TEMP.
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
PART MARKING
52FI
ISL61852FIRZ
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
0.6
1.1
1.1
1.5
1.5
1.5
1.5
0.6
0.6
1.1
1.1
0.6
0.6
1.1
1.1
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
LATCH
RETRY
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
8 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
10 Lead DFN
L8.3x3J
ISL61852GIRZ
ISL61852HIRZ
ISL61852IIRZ
ISL61852JIRZ
ISL61852KIRZ
ISL61852LIRZ
ISL61853AIRZ
ISL61853BIRZ
ISL61853CIRZ
ISL61853DIRZ
ISL61853EIRZ
ISL61853FIRZ
ISL61853GIRZ
ISL61853HIRZ
ISL61853IIRZ
ISL61853JIRZ
ISL61853KIRZ
ISL61853LIRZ
ISL61853MIRZ
ISL61853NIRZ
ISL61853OIRZ
ISL61853PIRZ
ISL61851EVAL1Z
ISL61852EVAL1Z
ISL61853EVAL1Z
NOTES:
52GI
52HI
52II
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
L8.3x3J
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
52JI
52KI
52LI
53AI
53BI
53CI
53DI
53EI
53FI
53GI
53HI
53II
53JI
53KI
53LI
53MI
53NI
53OI
53PI
8 Lead SOIC Evaluation Platform with ISL61851A installed
8 Lead DFN Evaluation Platform with ISL61852H installed
10 Lead DFN Evaluation Platform with ISL61853I installed
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information pages for ISL6185XXC (commercial version) and ISL6185XXI (industrial version).
For more information on MSL please see techbrief TB363.
FN6937.3
March 8, 2012
4
ISL6185
Pin Configurations
ISL6185
(8 LD SOIC/DFN)
TOP VIEW
ISL6185
(10 LD DFN)
TOP VIEW
GND
VIN
FLT1
OUT1
NC
1
2
3
4
5
10
9
GND
VIN
FLT1
1
2
3
4
8
7
6
5
(GND)
EPAD
(GND)
EPAD
OUT1
OUT2
VIN
8
DFN Only
7
EN1/EN1
EN2/EN2
OUT2
FLT2
EN1/EN1
6
EN2/EN2
FLT2
Pin Descriptions
PIN NUMBER
8 Ld
SOIC/DFN
10 Ld DFN
SYMBOL
GND
DESCRIPTION
1
2
1
IC ground reference.
2, 3
VIN
Chip bias, Controlled Voltage Input, Undervoltage Lock Out (UVLO). VIN provides chip bias voltage. At
VIN < 1.7V chip functionality is disabled, FLT is active and floating, and OUT is held low. Range 0V to
5.5V.
3,
4
4,
5
EN1, EN1/
EN2, EN2
Enable/Disable inputs, Active high (EN) and active low (EN) options enable the power switch. These
inputs have internal 1MΩ pull-off resistors. Range 0V to VIN.
5,
8
6,
10
FLT2
FLT1
Overcurrent Fault Indicator. FLT floats and is disabled until VIN >V
the current limit time-out period has expired. Fault is not signaled due to over-temperature shut down.
Range 0V to VIN.
. This output is pulled low after
UVLO
6,
7
7,
9
OUT2,
OUT1
Controlled Supply Output. Upon an OC condition, I
within 200µs. This output remains in current limit for a nominal 12ms before being turned off either for
is current limited. Current limit response time is
OUT
the latch or auto retry versions. Range 0V to VIN.
-
8
NC
This pin is not electrically connected internally.
PD
PD
EPAD
Thermal Dissipation Exposed PAD Range: Connect to GND.
(DFN only)
FN6937.3
March 8, 2012
5
ISL6185
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VIN to GND, Note 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V
EN, FAULT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VIN
OUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VIN 0.3V
Output Current . . . . . . . . . . . Short Circuit Protected Current Limit of 2.5A
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . . . . . . 3kV
Machine Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . . . . . 300V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical, Note 4)
θJA (°C/W) θJC (°C/W)
8 Lead SOIC Package (Note 4). . . . . . . . . .
8 Lead 3x3 DFN Package (Notes 5, 6) . . .
10 Lead 3x3 DFN Package (Notes 5, 6) . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
120
N/A
48
6
53
6
Operating Conditions
Commercial Temperature Range . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
6. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
7. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
V
= 5V, T = T , Unless Otherwise Specified. Boldface limits apply over the operating temperature
IN A J
range, 0°C to +75°C or -40°C to +85°C.
MIN
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 8)
TYP
71
(Note 8)
UNITS
POWER SWITCH
r
ON-Resistance at 5.0V (Pulse Tested)
ON-Resistance at 3.3V (Pulse Tested)
On Resistance at 2.5V (Pulse Tested)
V
= 5V, I
OUT
= 0.1A, T = T = +25°C
-
-
87
110
105
130
127
150
70
12
-
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mV
kΩ
DS(ON)_50
IN
A
J
T = T = +85°C
A
J
r
V
= 3.3V, I
= 0.1A, T = T = +25°C
-
90
DS(ON)_33
IN
OUT
A
J
T = T = +85°C
-
A
J
r
V
= 2.5V, I
= 0.1A, T = T = +25°C
-
114
DS(ON)_25
IN
OUT
A
J
T = T = +85°C
-
A
J
V
Disabled Output Voltage
Output Pull-Down Resistor
V
= 5V, Switch Disabled, 50µA Load
= 5V, Switch Disabled
-
50
9.6
100
200
23
OUT_DIS
IN
R
V
8
-
OUT_PU
IN
t
V
Rise Time
R = 10Ω, C = 10µF, 10% to 90%
µs
R
OUT
L
L
t
Slow V
Turn-off Fall Time
Turn-off Fall Time
R = 10Ω, C = 10µF, 90% to 10%
-
-
µs
F
OUT
OUT
L
L
t
Fast V
CURRENT CONTROL
R = 1Ω, C = 10µF, 80% to 20%
-
-
µs
F_fast
L
L
I
Maximum Continuous Current, V
5V.
Guaranteed by Itrip minimum
specification.
=
=
ISL6185xA,B,E,F
-
-
-
-
-
-
-
-
0.6
1.1
1.5
1.8
0.6
0.9
1.3
1.5
A
A
A
A
A
A
A
A
OUT_CONT_5
IN
I
ISL6185xC,D,G,H
OUT_CONT_5
I
ISL6185xI,J,K,L
OUT_CONT_5
I
ISL61853M,N,O,P (10 Ld DFN)
ISL6185xA,B,E,F
OUT_CONT_5
I
Maximum Continuous Current, V
3.3V.
OUT_CONT_3
IN
I
ISL6185xC,D,G,H
OUT_CONT_3
Guaranteed by Itrip minimum
specification.
I
ISL61851I,J,K,L (SOIC)
ISL61852, ISL61853 (DFN)
OUT_CONT_3
I
OUT_CONT_3
FN6937.3
March 8, 2012
6
ISL6185
Electrical Specifications
V
= 5V, T = T , Unless Otherwise Specified. Boldface limits apply over the operating temperature
IN
A
J
range, 0°C to +75°C or -40°C to +85°C. (Continued)
MIN
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 8)
TYP
0.6
(Note 8)
UNITS
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
I
Maximum Continuous Current, V
=
IN
ISL6185xA,B,E,F
-
-
OUT_CONT_2
2.5V
I
ISL61851C,D,G,H,I,J,K,L (SOIC)
ISL61852, ISL61853 C,D,G,H (DFN)
ISL61853I,J,K,L (10 Ld DFN)
ISL61853M,N,O,P (10 Ld DFN)
ISL6185xA,B,E,F
-
0.9
-
OUT_CONT_2
I
-
1
-
OUT_CONT_2
I
-
1
-
OUT_CONT_2
I
-
1
-
OUT_CONT_2
I
Trip Current, V = 5V
IN
0.70
1.15
1.55
1.85
0.65
0.95
1.35
1.55
-
1.02
1.45
1.82
1.99
0.86
1.25
1.60
1.89
0.65
1
1.52
1.95
2.25
2.45
1.20
1.60
1.85
2.25
-
TRIP_5
I
ISL6185xC,D,G,H
TRIP_5
I
ISL6185xI,J,K,L
TRIP_5
I
ISL61853M.N,O,P
TRIP_5
I
Trip Current, V = 3.3V
IN
ISL6185xA,B,E,F
TRIP_3
I
ISL6185xC,D,G,H
TRIP_3
I
ISL6185xI,J,K,L
TRIP_3
I
ISL61853M.N,O,P
TRIP_3
I
Trip Current, V = 2.5V
IN
ISL6185xA,B,E,F
TRIP_2
I
ISL6185xC,D,G,H
-
-
TRIP_2
I
ISL6185xI,J,K,L
-
1.2
-
TRIP_2
I
ISL61853M.N,O,P
-
1.6
-
TRIP_2
I
Current Limit, V = 5V
IN
ISL6185xA,B,E,F, V - V
IN OUT
= 1V
= 1V
0.50
0.98
1.30
1.52
0.45
0.90
1.25
1.48
0.47
0.90
1.15
1.3
0.60
1.00
1.15
1.20
0.35
0.65
0.70
0.90
0.65
1.14
1.55
1.83
0.63
1.10
1.50
1.78
0.61
1.05
1.37
1.63
0.80
1.27
1.61
1.70
0.48
0.80
1.06
1.24
0.78
1.28
1.72
2.20
0.75
1.26
1.68
2.05
0.74
1.17
1.58
1.90
1.00
1.55
1.85
2.5
LIM_5
I
ISL6185xC,D,G,H, V - V
IN OUT
LIM_5
I
ISL6185xI,J,K,L, V - V
IN OUT
= 1V
= 1V
LIM_5
I
ISL61853M,N,O,P, V - V
IN OUT
LIM_5
I
Current Limit, V = 3.3V
IN
ISL6185xA,B,E,F, V - V
IN OUT
= 1V
= 1V
LIM_3
I
ISL6185xC,D,G,H, V - V
IN OUT
LIM_3
I
ISL6185xI,J,K,L, V - V
IN OUT
= 1V
= 1V
LIM_3
I
ISL61853M,N,O,P, V - V
IN OUT
LIM_3
I
Current Limit, V = 2.5V
IN
ISL6185xA,B,E,F, V - V
IN OUT
= 1V
= 1V
LIM_2
I
ISL6185xC,D,G,H, V - V
IN OUT
LIM_2
I
ISL6185xI,J,K,L, V - V
IN OUT
= 1V
= 1V
LIM_2
I
ISL61853M,N,O,P, V - V
IN OUT
LIM_2
I
Short Circuit Current, V = 5V
IN
ISL6185xA,B,E,F, V
= 0V
= 0V
= 0V
sc_5
OUT
I
ISL6185xC,D,G,H, V
OUT
sc_5
I
ISL6185xI,J,K,L, V
OUT
sc_5
I
ISL61853M,N,O,P, V
= 0V
= 0V
sc_5
OUT
I
Short Circuit Current, V = 3.3V
IN
ISL6185XA,B,E,F, V
OUT
0.60
0.95
1.25
1.50
sc_3
I
ISL6185XC,D,G,H, V
= 0V
= 0V
sc_3
OUT
I
ISL6185xI,J,K,L, V
OUT
sc_3
I
ISL61853M,N,O,P, V = 0V
OUT
sc_3
FN6937.3
March 8, 2012
7
ISL6185
Electrical Specifications
V
= 5V, T = T , Unless Otherwise Specified. Boldface limits apply over the operating temperature
IN
A
J
range, 0°C to +75°C or -40°C to +85°C. (Continued)
MIN
MAX
SYMBOL
PARAMETER
Short Circuit Current, V = 2.5V
TEST CONDITIONS
ISL6185xA,B,E,F, V = 0V
(Note 8)
TYP
0.61
1.06
1.30
1.39
-
(Note 8)
UNITS
A
I
-
sc_2
IN
OUT
I
ISL6185xC,D,G,H, V
= 0V
-
-
A
sc_2
OUT
= 0V
OUT
I
ISL6185xI,J,K,L, V
-
-
A
sc_2
I
ISL61853M,N,O,P, V
OUT
= 0V
-
-
2.5
-
A
sc_2
I
Short Circuit Current, V = 5.5V
IN
All ISL6185X Variants
-
A
sc_5.5
tsett
OC to Limit Settling Time
Severe OC to Limit Settling Time
Current Limit Duration
V
/R = 2I , C = 10µF to within 10% of I
LIM
-
-
200
30
µs
µs
ms
s
Ilim
IN
L
L
LIM
tsett
V
/R = 4I , C = 10µF to within 10% of I
LIM
-
Ilim_sev
IN
L
L
LIM
t
I
= I
9.2
0.80
12
15
1.35
CL
OUT LIM
t
Automatic Retry Period
1
RTY
I/O PARAMETERS
Vfault_lo
Ifault
Fault Output Voltage
Fault I
OUT
= 10mA
-
-
-
5
0.4
-
V
µA
V
Fault Leakage
Venr_5
EN / EN Rising Threshold
V
V
V
V
V
V
= 5V
1.5
80
1.0
58
0.95
30
0.6
0.6
-
1.8
140
1.3
80
1.1
70
1
2
IN
IN
IN
IN
IN
IN
Hys_Venr_5
Venr_3
EN / EN Rising Threshold Hysteresis
EN / EN Rising Threshold
= 5V
175
1.6
120
1.3
110
1.55
1.55
-
mV
V
= 3.3V
= 3.3V
= 2.5V
= 2.5V
Hys_Venr_3
Venr_2
EN / EN Rising Threshold Hysteresis
EN / EN Rising Threshold
mV
V
Hys_Venr_2
Ren_h
EN / EN Rising Threshold Hysteresis
ENABLE Pull-Down Resistor
ENABLE Pull-Up Resistor
mV
MΩ
MΩ
ms
ms
Enable asserted high options
Enable asserted low options
Ren_l
1
t
Enable to Output Turn-on Time
Enable to Output Turn-off Time
R = 10Ω, C = 10µF, Enable 50% to Output 90%
0.1
0.25
ON
L
L
t
R = 10Ω, C = 10µF, Enable 50% to Output 10%
-
-
OFF
L
L
BIAS PARAMETERS
Enabled V Current
I
Switches Closed, OUTPUT = OPEN
Switches Open, OUTPUT = OPEN
50
2
75
5
µA
µA
V
VDD
IN
I
Disabled V Current
IN
-
VDD
V
Rising POR Threshold
V
Rising to functional operation
1.7
2.1
2.3
2
UVLO
IN
I
Reverse Blocking Leakage Current
Over-Temperature Disable
Over-Temperature Hysteresis
V
= 0V, V
IN OUT
= 5V
-
-
-
µA
°C
°C
VR
Temp_dis
Temp_hys
150
20
-
-
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN6937.3
March 8, 2012
8
ISL6185
Introduction
Functional Description
The ISL6185 is a dual channel fully independent overcurrent (OC)
fault protection IC for the +2.5V to +5V environment. Each
ISL6185 incorporates in a single package two 85mΩ P-channel
MOSFET power switches for power control. Independent enabling
inputs and fault reporting outputs compatible with 2.5V to 5V
logic allow for external control and reporting. This device features
integrated power switches with current monitoring, accurate
current limiting, reverse bias protection and current limited
timed delay to turn-off for system reliability. See Figures 13
through 28 for typical operational waveforms including both
under-current and over-current situations.
Power On Preset (POR)
The ISL6185 POR feature inhibits device functionality when
VIN < V
.
UVLO
Reverse Polarity Protection
In any event in which the power switch is disabled and
V
> V there will be no output-to-input current flow, nor will
OUT
IN,
the output voltage appear on the input.
Soft-Start
Upon enable, the switch passes a constant current to the load.
The voltage on the VOUT pin ramps up according the equation,
The ISL6185 offers current sense and limiting, with V = 5V
IN
guaranteed continuous current product variants of 0.6A, 1.1A, 1.5A
and 1.8A, making these devices well suited for a myriad of USB and
other low power (9W max) port power management applications
and configurations.
I
/C
(V/s). Resistive or active load slows the V ramp-up
LIM OUT
OUT
toward the top of its curve.
Fault Blanking On Start-Up
During initial turn-on, the ISL6185 prevents nuisance faults from
being reported to the system controller by blanking the fault
signal until the internal FET is fully enhanced.
The ISL6185 also provides thermally insensitive timed OC turn-off
and fault notification. This isolates and protects the voltage bus in
the event of a peripheral OC event or short circuit event,
independent of the adjoining switch’s electrical or the ambient
thermal condition.
Current Trip and Limiting Levels
The ISL6185 undervoltage lockout feature prevents turn-on of
the outputs unless the correct ENABLE state and V > V
are present. During initial turn-on, the ISL6185 prevents fault
reporting by blanking the fault signal.
The ISL6185 provides integrated current sensing in the MOSFET
that allows for rapid control of OC events. Once an OC condition is
detected, the ISL6185 goes into its current limiting (CL) control
mode. The ISL6185 is variant specified to allow a continuous
IN
UVLO
current (I
) operation of 0.6A, 1.1A, 1.5A or 1.8A. As the
CONT
During operation, once an OC condition is detected, the output
current increases past its continuous current rating, it will reach
a level that causes the device to enter its current limit mode; that
is, the current trip level. The current trip level is in all cases
adequately above the I
false faults. The current limit is specified at V
OUT
a known representative condition and is featured at a nominal
value slightly higher than the continuous current rating. The
speed of this current limiting control is inversely related to the
magnitude of the OC fault. Thus, a hard overcurrent is more
quickly pulled to its limiting value than a marginal OC condition.
is current limited for t to allow transient OC conditions to
CL
pass. If still in current limit after the current limit period has
elapsed, the output is turned off, and the fault is reported by
pulling the corresponding FAULT output low. On the latch-off
options, after turn-off, both the output and the FAULT signal are
latched low until reset by the enable signal being de-asserted or
until a POR occurs. At this time, the FAULT signal clears, and
the switch is ready to be turned back on. On the auto restart
options, the ISL6185 attempts to periodically turn on the
output, as long as the enable is asserted.
rating so as not to cause unintended
= V - 1V to test
CONT
IN
When disabled, the ISL6185 has a low quiescent supply current
and an output-to-input reverse current flow blocking capability.
Over-Temperature Shutdown
Although the ISL6185 has an over-temperature shutdown and
lockout feature, because of the 12ms timed shutdown, the
thermal shutdown is likely to be invoked only in extremely high
ambient temperatures.
The ISL6185 family is provided with enable polarity options and
an industry-standard 8 lead SOIC pinout, along with two versions
in the 70% smaller 3x3 DFN. The 8 Ld DFN package offers the
same performance as the 8 Ld SOIC, whereas the 10 Ld DFN
offers higher current capability in the smallest possible package
because of lower package electrical and thermal resistance.
The over-temperature protection invokes and disables the switch
turn-on operation once the die temperature is ~+140°C. It turns
off an already on switch at ~+150°C and releases the part to
operation once the die temperature falls to ~+120°C.
FN6937.3
March 8, 2012
9
ISL6185
Turn-off Time Delay
Latch-off Restart/Auto-Restart Start
During operation, once an OC condition is detected, the output
is current limited for ~12ms to allow transient OC conditions to
pass. If still in current limit and after the current limit period
has elapsed, the output is turned off, and the fault is reported
by pulling the corresponding FAULT low. The internal 12ms timer
starts upon current limiting and is independent of ambient or IC
thermal conditions, thus providing more consistent operation
over the entire temperature range.
After turn-off, with the latch-off options, both the output and the
FAULT signal are latched low until they are reset by the enable
signal being de-asserted. At this time, the FAULT signal clears,
and the IC is ready for enable to assert. On the auto restart
options, the ISL6185 attempts to periodically turn-on the
output at approximately 1s intervals, as long as the enable is
asserted. If the OC condition remains indefinitely, the fault
indication and the restart attempts also continue until the
thermal protection feature is invoked, thus increasing the
restart period.
Active Output Pull-down
Another ISL6185 feature is the 10kΩ active pull-down on the
outputs to <60mV above GND when the device is disabled, thus
ensuring discharge of the load.
Typical Performance Curves
150
140
130
1.3
1.2
1.1
1.0
0.9
0.8
0.7
V
= 2.5V
= 3.3V
IN
120
110
100
90
V
IN
80
70
V
= 5V
IN
60
50
-40
-25
0
25
45
75
85
115
-40
-25
0
25
45
75
85
115
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 3. SWITCH ON-RESISTANCE AT 0.5A
FIGURE 4. NORMALIZED SWITCH RESISTANCE
1.6
1.5
1.2
5V I
TRIP
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
5V I
TRIP
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
5V I
SC
3.3V ITRIP
5V I
3.3V ITRIP
LIM
5V I
5V I
SC
3.3V I
LIM
LIM
3.3V I
LIM
3.3V I
85
SC
3.3V I
85
SC
-40
-25
0
25
45
75
115
-40
-25
0
25
45
75
115
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 6. 1.1A CONTINUOUS CURRENT CHARACTERISTICS
FIGURE 5. 0.6A CONTINUOUS CURRENT CHARACTERISTICS
FN6937.3
March 8, 2012
10
ISL6185
Typical Performance Curves (Continued)
2.0
2.2
2.0
1.8
1.6
1.4
1.2
1.0
5V I
TRIP
1.8 5V I
TRIP
3.3V I
TRIP
3.3V I
TRIP
5V I
SC
1.6
1.4
1.2
1.0
0.8
5V I
SC
5V I
LIM
3.3V I
LIM
5V I
LIM
3.3V I
LIM
3.3V I
SC
3.3V I
85
SC
-40
-25
0
25
45
75
115
-40
-25
0
25
45
75
85
115
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 7. 1.5A CONTINUOUS CURRENT CHARACTERISTICS
FIGURE 8. 1.8A CONTINUOUS CURRENT CHARACTERISTICS
0.75
1.25
0.6A CONTINUOUS I
OUT
VERSION
1.1A CONTINUOUS I
VERSION
OUT
+3 SIGMA
TYPICAL
-3 SIGMA
0.70
0.65
0.60
0.55
0.50
1.20
1.15
1.10
1.05
1.00
+3 SIGMA
TYPICAL
-3 SIGMA
-40
-25
0
25
45
75
85
115
-40
-25
0
25
45
75
85
115
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 9. LIMITING CURRENT ±3 SIGMA, V = 5V
IN
FIGURE 10. LIMITING CURRENT ±3 SIGMA, V = 5V
IN
1.65
2.00
1.8A CONTINUOUS I
VERSION
1.5A CONTINUOUS I
OUT
VERSION
OUT
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
+3 SIGMA
1.60
1.55
1.50
1.45
1.40
1.35
+3 SIGMA
TYPICAL
TYPICAL
-3 SIGMA
-3 SIGMA
-40
-25
0
25
45
75
85
115
-40
-25
0
25
45
75
85
115
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 12. LIMITING CURRENT ±3 SIGMA, V = 5V
IN
FIGURE 11. LIMITING CURRENT ±3 SIGMA, V = 5V
IN
FN6937.3
March 8, 2012
11
ISL6185
Typical Performance Curves (Continued)
ENABLE
ENABLE
C
= 1µF
C
= 10µF
L
L
C
= 10µF
L
V
OUT
1V/DIV
C
= 100µF
L
C
= 100µF
L
VOUT
1V/DIV
C
= 1µF
L
FIGURE 13. V
R
TURN-ON/RISE TIME vs C
. V = 5V,
LOAD IN
FIGURE 14. V
TURN-OFF/FALL TIME
OUT
OUT
= 10Ω
vs C
. V = 5V, R = 10Ω
L
LOAD IN
L
0.6A I
VARIANT
CONT
FLT
C
= 10µF
L
V
V
OUT
OUT
C
= 100µF
L
1V/DIV
I
IN
C
= 1µF
L
FIGURE 15. LATCH-OFF vs C
FIGURE 16. I
WAVEFORM
LIM
LOAD
0.6A I
CONT
VARIANT
0.6A I
VARIANT
CONT
2A OC 27µs
6A/ms
0.6A/ms
1A OC 57µs
0.08A/ms
0.5A OC 200µs
0.72A CURRENT LIMIT
0.53A LOAD CURRENT
0.66A CURRENT LIMIT
0.56A LOAD CURRENT
I
2A/DIV
IN
FIGURE 18. PEAK CURRENT SETTLING TIMES
FIGURE 17. OC RAMP RATE I
WAVEFORMS
LIM
FN6937.3
March 8, 2012
12
ISL6185
Typical Performance Curves (Continued)
ENABLE
VARIANT
ENABLE
0.6A I
CONT
VARIANT
V
OUT
0.6A I
CONT
FAULT
FAULT
I
IN
LIMITED TO 0.64A
I
IN
V
OUT
FIGURE 20. TURN-ON INTO MOMENTARY OC
FIGURE 19. TURN-ON INTO A SHORT
1.1A I
VARIANT
FLT
CONT
V
OUT
V
OUT
FLT
I
IN
I
IN
FIGURE 21. ISL6185 RETRY FUNCTION
FIGURE 22. I
WAVEFORM
LIM
ENABLE
FAULT
ENABLE
FAULT
V
OUT
V
OUT
Iin
I
1.8A I
VARIANT
IN
CONT
1.8A I
CONT
VARIANT
FIGURE 23. V = 2.5V TURN-ON INTO 2.2Ω
FIGURE 24. V = 5V TURN-ON INTO 2.7Ω
IN
IN
FN6937.3
March 8, 2012
13
ISL6185
Typical Performance Curves (Continued)
CH1 and CH2 ON
(3.6A TOTAL I
I
IN
)
IN
ENABLE
FAULT
V
OUT
CH1 ON
(1.8A)
I
IN
LIMITED TO 1.7A
ENABLE
FAULT
1.8A I
VARIANT
V
CONT
OUT
FIGURE 26. TURN-ON 2ND OUTPUT TO FULL LOAD
FIGURE 25. TURN-ON INTO A SHORT
1.1A I
VARIANT
FLT
CONT
V
OUT
V
OUT
FLT
I
IN
I
IN
FIGURE 27. ISL6185 RETRY FUNCTION
FIGURE 28. PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
FIGURE 28. ILIM WAVEFORM
Test Circuits
-
+
V
10k
10k
OUTPUT
sized
for desired
OC level
FLT
FLT
5V
VIN
EN
OUT
R
L
5V
OUTPUT
VIN
OUT
10µF
10
ISL6185
10µF
ISL6185
EN
10
R
L
r
= V/(VOUT/10W)
DS(ON)
FIGURE 29A. r
FIGURE 29B. CURRENT LIMITING
DS(ON)
FIGURE 29. DC TEST CIRCUIT
FN6937.3
March 8, 2012
14
ISL6185
Test Circuits (Continued)
VIN
0V
EN
0.5VIN
0.5VIN
10k
t
t
OFF
ON
FLT
OUT
VIN
90%
5V
OUTPUT
VIN
EN
OUTPUT
OUTPUT
10µF
ISL6185
10%
0-V
GND
IN
10
VIN
90%
90%
10%
10%
t
-GND
t
R
F
FIGURE 30. TRANSIENT TEST CIRCUIT
FIGURE 31. TRANSIENT WAVEFORM MEASUREMENT POINTS
ISL6185xEVAL1Z Schematic and Photo
R1
FLT1
OUT1
10k
R3
10
AGND
C2
FLT1
OUT1
OUT2
AGND
V+
EN1
U1
A
10µF
V+
A
ISL6185
R4
FLT2
OUT2
EN2
A
10
C3
A
A
10µF
R2
FLT2
10k
NOTE: EXPOSED PAD on DFN packages only
FIGURE 32A. ISL6185xEVAL SCHEMATIC
FIGURE 32B. ISL61851EVAL1Z BOARD PHOTO
FIGURE 32. ISL6185xEVAL1Z SCHEMATIC and ISL61851EVAL1Z PHOTOGRAPH
FN6937.3
March 8, 2012
15
ISL6185
Application Considerations
Application Information
Using the ISL6185xEVAL1Z Platform
General and Biasing Information
There are three evaluation platforms for the ISL6185 family.
There is one platform for each package style, each with a
different continuous output current level and a mix of enable
polarity and output retry or latch options. See page 4, at the end
of the “Ordering Information” table, for information on the
standard available evaluation board options. Figure 32A shows
the common schematic for all three evaluation boards. See “Pin
Configurations” on page 5 for details and differences.
The application considerations for the ISL6185 family are widely
accepted best industry practices. Good decoupling practices on
the VIN pin must be followed: placement close to the IC, with at
least 2.2µF recommended. It is recommended to reduce the
input and output inductance to the ISL6185 with good PCB
layout practices.
When designing with the 1.5A and 1.8A versions in an
implementation in which the output may be unloaded (open)
while the ISL6185 is turned on, a minimum of 4.7µF of
capacitive output load is recommended to prevent high dv/dt
from unnecessarily activating the surge/ESD control circuit.
The evaluation platform is biased and monitored through
numerous labeled test points. See Table 1 for test point
assignments and descriptions.
The ISL6185 provides several continuous current rated devices
specified at V = 5V; these are 0.6A, 1.1A, 1.5A and 1.8A
IN
options that are capable over the entire temperature extreme. At
V
= 3.3V, the current capability is degraded, and the ISL6185 is
IN
specified at 0.6A, 1.1A, 1.3A and 1.5A, respectively. At
= 2.5V, there are no minimum specifications, but a typical
TABLE 1. ISL61851EVAL1Z TEST POINT ASSIGNMENTS
TP NAME
GND
V+
DESCRIPTION
Eval Board and IC Gnd
V
IN
value is provided for +25°C operation (see “Electrical
Specifications” on page 6). This degraded capability is due to the
higher r
Eval Board and IC Bias
Enable Switch 1
Enable Switch 2
Switch 2 Fault
Switch Out 2
of the FET switch at the lower bias voltage.
DS(ON)
EN1
The enhanced thermal characteristics and increased number of
bond wires allow the 10 Ld DFN to have a higher current
capability than either the 8 Ld SOIC or the DFN.
EN2
FLT2
OUT2
OUT1
FLT1
TABLE 2. ISL6185XEVAL1Z BOARD COMPONENT LISTING
COMPONENT
DESIGNATOR
COMPONENT
FUNCTION
COMPONENT DESCRIPTION
Intersil, ISL6185
Switch Out 1
U1
ISL6185
Switch 1 Fault
R3 - R4
Output Load
Resistors
10Ω, 5%, 3W
Upon proper bias of the evaluation platform and correct enabling
of the IC, the ISL6185 will have a nominal V /10Ω load current
IN
R1 - R2
C1
FLT Output Pull-up 10kΩ, 0805
Resistor
that is lower than the continuous current rating passing through
each enabled switch. See Figures 13 and 14 for typical ISL6185
turn-on and turn-off waveforms.
Decoupling
Capacitor
2.2µF, 0805
External current loading in excess of the trip current level for the
particular part being evaluated will result in the ISL6185 entering
the current limiting mode. Figure 16 illustrates the current
limiting mode for the ISL6185 product variants with 0.6A of
continuous load current rating. The scope shot shows current
limiting for ~12ms before it is turned off and the fault signal is
asserted.
C2 - C3
Load Capacitor
10µF 16V Electrolytic,
Radial Lead
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6937.3
March 8, 2012
16
ISL6185
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
FN6937.3
CHANGE
March 1, 2012
In “Features” on page 1 changed from:
UL Recognized, File Number: E333469
(Applies to DFN Packages, SOIC Package to be Qualified Shortly)
to:
UL Recognized, File Number : E333469
In “Absolute Maximum Ratings” on page 6:
Changed from:
Output Current . . . . . . . . . Short Circuit Protected
to:
Output Current . . . . . . . . . .Short Circuit Protected Current Limit of 2.5A
Updated “Package Outline Drawing” on page 20. Changed Note 1 "1982" to "1994".
December 2, 2011
FN6937.2
FN6937.1
Page 1: Added "UL Recognized, File Number: E333469 (Applies to DFN packages, SOIC pkg to be qualified
shortly)" to "Features"
Page 8: Added Isc_5.5, Short Circuit Current with max of 2.5A to “Electrical Specifications”
Page 19: Updated package outline drawing to most updated revision. Removed package outline and included
center to center distance between lands on recommended land pattern. Removed Note 4 "Dimension b applies
to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip." since it is
not applicable to this package. Renumbered notes accordingly.
June 14, 2011
Page 2: “Ordering Information”: added part numbers of parts installed on evaluation boards to Description
column.
Page 7: “Electrical Specifications” table:
- For “Maximum Continuous Current, VIN = 2.5V,” changed “ISL61851C,D,G,H (SOIC)” to
“ISL61851C,D,G,H,I,J,K,L (SOIC)”
- For “Trip Current, V = 5V”, changed “ISL61853I,J,K,L” to “ISL6185xI,J,K,L”. For “ISL61853M.N,O,P” changed
IN
MAX from “2.15” to “2.45”.
- For “Trip Current, VIN = 3.3V” and “Trip Current, VIN = 2.5V” changed “ISL61853I,J,K,L“ to “ISL6185xI,J,K,L“.
- For “Current Limit, VIN = 5V”, “Current Limit, VIN = 3.3V”, and “Current Limit, VIN = 2.5V”, changed
“ISL61853I,J,K,L, VIN - VOUT = 1V” to “ISL6185xI,J,K,L, VIN - VOUT = 1V”
- For “Short Circuit Current, VIN = 5V”, “Short Circuit Current, VIN = 3.3V” and “Short Circuit Current, VIN = 2.5V”
changed “ISL61853I,J,K,L, VOUT = 0V” to “ISL6185xI,J,K,L, VOUT = 0V”
Page 8: “Electrical Specifications” table: For the I/O Parameters Venr_5, Hys_Venr_5, Venr_3, Hys_Venr_3,
Venr_2, and Hys_Venr_2: changed "ENABLE Rising Threshold" and "ENABLE Rising Threshold Hysteresis" to "EN
/ EN Rising Threshold" and "EN / EN Rising Threshold Hysteresis," for clarity.
Page 8: Electrical Specifications table: Removed UV
, POR Hysteresis specification.
HYS
Page 20: Replaced Rev. 1 of M8.15 package outline drawing, dated 6/05, with Rev 2 (latest version), dated
11/10.
Applied current Intersil datasheet template to document.
October 22, 2010
FN6937.0
Initial release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information pages
on intersil.com for ISL6185XXC (commercial version) and ISL6185XXI (industrial version).
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/sear
FN6937.3
March 8, 2012
17
ISL6185
Package Outline Drawing
L8.3x3J
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 0 9/09
2X 1.950
3.00
A
6X 0.65
B
5
8
(4X)
0.15
1.64 +0.10/ - 0.15
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
4
1
4
8X 0.30
0.10 M C A B
8X 0.400 ± 0.10
TOP VIEW
2.38
+0.10/ - 0.15
BOTTOM VIEW
SEE DETAIL "X"
( 2.38 )
( 1.95)
C
0.10
C
Max 1.00
0.08
C
SIDE VIEW
( 8X 0.60)
(1.64)
( 2.80 )
PIN 1
5
C
0 . 2 REF
(6x 0.65)
0 . 00 MIN.
0 . 05 MAX.
( 8 X 0.30)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6937.3
March 8, 2012
18
ISL6185
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 7, 10/11
5
3.00
A
B
PIN #1 INDEX AREA
1
2
5
PIN 1
INDEX AREA
10 x 0.23
(4X)
0.10
1.60
10x 0.35
TOP VIEW
BOTTOM VIEW
A B
C
M
0.10
(4X)
0.415
0.23
0.35
SEE DETAIL "X"
0.10
(10 x 0.55)
(10x 0.23)
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
4
0.20 REF
0.05
C
1.60
2.85 TYP
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
4.
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
5.
FN6937.3
March 8, 2012
19
ISL6185
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
AREA
6.20 (0.244)
5.80 (0.228)
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
8°
0°
1
2
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
1
8
SEATING PLANE
0.60 (0.023)
1.27 (0.050)
1.75 (0.069)
5.00 (0.197)
4.80 (0.189)
2
3
7
6
1.35 (0.053)
-C-
4
5
0.25(0.010)
0.10(0.004)
1.27 (0.050)
0.51(0.020)
0.33(0.013)
5.20(0.205)
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN6937.3
March 8, 2012
20
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