ISL62391IRTZ [RENESAS]
High-Efficiency, Triple-Output System Power Supply Controller for Notebook Computers;
| 型号： | ISL62391IRTZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | High-Efficiency, Triple-Output System Power Supply Controller for Notebook Computers |
| 文件： | 总22页 (文件大小：1063K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL62391, ISL62392, ISL62391C, ISL62392C
High-Efficiency, Triple-Output System Power Supply Controller for Notebook
Computers
FN6666
Rev 8.00
August 25, 2015
The ISL62391, ISL62392, ISL62391C and ISL62392C
controller generate supply voltages for battery-powered
Features
3
• High Performance R Technology
• Fast Transient Response
systems. It includes two pulse-width modulation (PWM)
controllers, adjustable from 0.6V to 5.5V, and a linear
regulator (LDO3) that generates a fixed 3.3V and can deliver
up to 100mA. The ISL62391, ISL62392, ISL62391C and
ISL62392C include on-board power-up sequencing, a
power-good (PGOOD) output, digital soft-start, and internal
soft-stop output discharge that prevents negative voltages on
shutdown.
• ±1% Output Voltage Accuracy
• 2 Fully Programmable Switch-Mode Power Supplies
• Programmable Switching Frequency
• Fixed 3.3V LDO Output
• Internal Soft-Start and Soft-Stop Output Discharge
• Wide Input Voltage Range: 5.5V to 25V
• Full and Ultrasonic Pulse-Skipping Mode
• Power-Good Indicator
3
The patented R PWM control scheme provides a low jitter
system with fast response to load transients. Light-load
efficiency is improved with period-stretching discontinuous
conduction mode (DCM) operation. To eliminate noise in audio
frequency applications, an ultrasonic DCM mode is included,
which limits the minimum switching frequency to 28kHz.
• Overvoltage, Undervoltage and Overcurrent Protection
• Thermal Monitor and Protection
The ISL62391, ISL62391C and ISL62392, ISL62392C are
identical except for how their overvoltage protection is
handled. The ISL62391 and ISL62391C utilize a tri-state
overvoltage scheme, whereas the ISL62392 and ISL62392C
employ a soft-crowbar method.
• Pb-Free (RoHS Compliant)
Applications
• Notebook and Sub-Notebook Computers
• PDAs and Mobile Communication Devices
• 3-Cell and 4-Cell Li+ Battery-Powered Devices
The ISL62391, ISL62392, ISL62391C and ISL62392C are
available in a 28 Ld 4x4 TQFN package and operate over
the extended temperature range (-40°C to +100°C).
Pinout
ISL62391, ISL62392, ISL62391C, ISL62392C
(28 LD 4X4 TQFN)
TOP VIEW
28 27 26 25 24 23 22
PGOOD
FSET2
FCCM
VCC
BOOT2
LGATE2
PGND
PVCC
VIN
1
2
3
4
5
6
7
21
20
19
18
17
16
15
LDO3EN
FSET1
FB1
LDO3
CENTER PAD:
GND
LGATE1
8
9
10 11 12 13 14
FN6666 Rev 8.00
August 25, 2015
Page 1 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Ordering Information
PART NUMBER
PACKAGE
(Pb-Free)
PKG.
DWG. #
(Notes 1, 2)
ISL62391HRTZ (Note 3)
ISL62392HRTZ (Note 3)
PART MARKING
623 91HRTZ
623 92HRTZ
TEMP RANGE (°C)
-10 to +100
28 Ld 4x4 TQFN
L28.4x4
-10 to +100
28 Ld 4x4 TQFN
28 Ld 4x4 TQFN
L28.4x4
L28.4x4
ISL62391CHRTZ (No longer available or 62391C HRTZ
-10 to +100
supported)
ISL62392CHRTZ
62392C HRTZ
623 91IRTZ
623 92IRTZ
62391C IRTZ
-10 to +100
-40 to +100
-40 to +100
-40 to +100
28 Ld 4x4 TQFN
28 Ld 4x4 TQFN
28 Ld 4x4 TQFN
28 Ld 4x4 TQFN
L28.4x4
L28.4x4
L28.4x4
L28.4x4
ISL62391IRTZ (Note 3)
ISL62392IRTZ (Note 3)
ISL62391CIRTZ (No longer available or
supported)
ISL62392CIRTZ
NOTES:
62392C IRTZ
-40 to +100
28 Ld 4x4 TQFN
L28.4x4
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
3. Not Recommended for New Designs. No Recommended Replacement.
FN6666 Rev 8.00
August 25, 2015
Page 2 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Absolute Maximum Ratings
Thermal Information
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +28V
Thermal Resistance (Typical, Notes 4, 5)
(°C/W)
37
(°C/W)
3.5
JA
JC
VCC, PGOOD, PVCC to GND. . . . . . . . . . . . . . . . . . -0.3V to +7.0V
TQFN Package . . . . . . . . . . . . . . . . . .
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55C to +150°C
Operating Temperature Range
EN
1, 2
, LDO3EN . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC +0.3V
. . . . . . . . . . . . -0.3V to GND, VCC +0.3V
VOUT , FB , FSET
1,2 1,2 1,2
PHASE to GND . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V
1,2
(<100ns Pulse Width, 10µJ). . . . . . . . . . . . . . . . . . . . . . . . . -5.0V
ISL62391IRTZ). . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +100°C
ISL62392IRTZ). . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +100°C
Operating Temperature Range
ISL62391HRTZ). . . . . . . . . . . . . . . . . . . . . . . . . .-10C to +100°C
ISL62392HRTZ). . . . . . . . . . . . . . . . . . . . . . . . . .-10C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
BOOT
BOOT
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +33V
1,2
to PHASE
. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7V
1,2
1,2
UGATE
. . . . . . . . . . . .(DC) -0.3V to PHASE , BOOT
+0.3V
1,2
1,2 1,2
(<200ns Pulse Width, 20µJ) . . . . . . . . . . . . . . . . . . . . . . . . -4.0V
LGATE . . . . . . . . . . . . . . . . . . . (DC) -0.3V to GND, PVCC +0.3V
1,2
(<100ns Pulse Width, 4µJ). . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V
LDO3 Current (Internal Regulator) Continuous . . . . . . . . . +100mA
Recommended Operating Conditions
Ambient Temperature Range
ISL62391IRTZ). . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
ISL62392IRTZ). . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Ambient Temperature Range
ISL62391HRTZ). . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
ISL62392HRTZ). . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Supply Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . 5.5V to 25V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications VIN = 12V, EN = VCC, T = -40°C to +100°C, unless otherwise noted. Typical values are at T = +25°C.
A
A
Boldface limits apply over the operating temperature range.
MIN
MAX
PARAMETER
LINEAR REGULATOR
CONDITIONS
(Note 7)
TYP
(Note 7) UNITS
VIN Power-on Reset
Rising Threshold
Hysteresis
5.3
20
5.4
80
5.5
150
15
V
mV
µA
µA
V
VIN Shutdown Supply Current
VIN Standby Supply Current
LDO3 Output Voltage
EN1 = EN2 = LDO3EN = 0
EN1 = EN2 = 0, LDO3EN = 1
I_LDO3 = 100mA
I_LDO3 = 0mA
6
150
3.3
3.3
180
250
3.35
3.35
3.25
3.25
V
LDO3 Short-Circuit Current
LDO3EN Input Voltage
LDO3 = GND
mA
V
Rising edge
1.1
0.94
-1
2.5
1.06
1
Falling edge
V
LDO3EN Input Leakage Current
LDO3 Discharge ON-resistance
PVCC POR Threshold
LDO3EN = 0 or VCC
LDO3EN = 0
µA
36
4.2
4.8
2.5
60
V
SMPS2 to PVCC Switchover Threshold
SMPS2 to PVCC Switchover Resistance
MAIN SMPS CONTROLLERS
VCC Input Bias Current
4.63
3.45
4.93
3.2
V
VOUT2 to PVCC, VOUT2 = 5V
EN1 = EN2 = 1, FB1 = FB2 = 0.65V
EN1 = EN2 = LDO3EN = GND
2
mA
V
VCC Start-up Voltage
3.6
3.75
FN6666 Rev 8.00
August 25, 2015
Page 3 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Electrical Specifications VIN = 12V, EN = VCC, T = -40°C to +100°C, unless otherwise noted. Typical values are at T = +25°C.
A
A
Boldface limits apply over the operating temperature range. (Continued)
MIN
MAX
PARAMETER
VCC POR Threshold
CONDITIONS
(Note 7)
TYP
4.50
4.50
(Note 7) UNITS
Rising Edge
Rising Edge (ISL62391HRTZ, ISL62392HRTZ,
= -10°C to +100°C)
4.33
4.55
4.55
V
V
4.35
T
A
Falling Edge
4.08
4.10
4.20
4.20
4.30
4.30
V
V
Falling Edge (ISL62391HRTZ, ISL62392HRTZ,
T
= -10°C to +100°C)
A
Reference Voltage
Regulation Accuracy
FB Input Bias Current
0.6
V
VOUT regulated to 0.6V
FB = 0.6V
-1
1
%
-12
-10
30
30
nA
nA
FB = 0.6V (ISL62391HRTZ, ISL62392HRTZ,
T
= -10°C to +100°C)
A
Frequency Range
200
-12
0.6
600
12
5.5
50
50
1
kHz
%
Frequency Set Accuracy
F
= 300kHz (Note 6)
SW
VOUT Voltage Adjust Range
VOUT Soft-discharge Resistance
PGOOD Pull-down Impedance
PGOOD Leakage Current
Maximum PGOOD Sink Current
VIN 6V for VOUT = 5.5V
V
14
32
PGOOD = VCC
0
µA
mA
ms
ms
ms
5
PGOOD Soft-start Delay
(From first EN = 1 to PGOOD = 1)
EN1 = EN2 = 1
2.20
4.50
4.50
2.75
5.60
5.60
3.70
7.60
7.50
EN1 = 1, EN2 = Floating or EN1 = Floating, EN2 =1
EN1 = 1, EN2 = Floating or EN1 = Floating, EN2 =1
(ISL62391HRTZ, ISL62392HRTZ, T = -10°C to
A
+100°C)
UGATE Pull-up ON-resistance
UGATE Source Current
200mA source current
UGATE-PHASE = 2.5V
250mA source current
UGATE-PHASE = 2.5V
250mA source current
LGATE-PGND = 2.5V
250mA source current
LGATE-PGND = 2.5V
UG falling to LG rising, no load
LG falling to UG rising, no load
2mA forward diode current
1.0
2.0
1.0
2.0
1.0
2.0
0.5
4.0
21
1.5
1.5
1.5
0.9
A
UGATE Pull-down ON-resistance
UGATE Sink Current
A
LGATE Pull-up ON-resistance
LGATE Source Current
A
LGATE Pull-down ON-resistance
LGATE Sink Current
A
UGATE to LGATE Deadtime
LGATE to UGATE Deadtime
Bootstrap Diode Forward Voltage
Bootstrap Diode Reverse Leakage Current
FCCM Input Voltage
ns
ns
V
21
0.58
0.2
V
= 25V
1
µA
V
R
Low Level (DCM enabled)
Float Level (audio filter enabled)
High Level (forced CCM)
FCCM = GND or VCC
0.8
2.1
1.9
2.4
-2
V
V
FCCM Input Leakage Current
Audio Filter Switching Frequency
EN Input Voltage
2
µA
kHz
V
FCCM floating
28
Low Level (Clear fault level/SMPS off)
Float Level (Delayed start)
High Level (SMPS on)
0.8
2.1
1.9
2.4
V
V
FN6666 Rev 8.00
August 25, 2015
Page 4 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Electrical Specifications VIN = 12V, EN = VCC, T = -40°C to +100°C, unless otherwise noted. Typical values are at T = +25°C.
A
A
Boldface limits apply over the operating temperature range. (Continued)
MIN
MAX
PARAMETER
EN Input Leakage Current
CONDITIONS
(Note 7)
TYP
(Note 7) UNITS
EN = GND or VCC
EN = VCC
-3.5
3.5
µA
k
µA
k
µA
µA
µA
ISEN Input Impedance
600
0.1
ISEN Input Leakage Current
OCSET Input Impedance
OCSET Input Leakage Current
OCSET Current Source
EN = GND
EN = VCC
600
0.1
EN = GND
EN = VCC
8.7
9
10.0
10.0
10.5
10.5
EN = VCC (ISL62391HRTZ, ISL62392HRTZ,
= -10°C to +100°C)
T
A
OCP (OCSET-ISEN) Threshold
UVP Threshold
-1.75
80.9
81
0.0
84
84
1.75
87
mV
%
Falling edge, referenced to FB
Falling edge, referenced to FB (ISL62391HRTZ,
87
%
ISL62392HRTZ, T = -10°C to +100°C)
A
OVP Threshold
OTP Threshold
NOTES:
Rising edge, referenced to FB
Falling edge, referenced to FB
Rising edge
113
116
103
150
135
120
106
%
%
99.5
°C
Falling edge
6. F
SW
accuracy reflects IC tolerance only; it does not include frequency variation due to V , V
, L
, ESR , or other application specific
COUT
IN OUT OUT
parameters.
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN6666 Rev 8.00
August 25, 2015
Page 5 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Functional Pin Description
PIN
NAME
FUNCTION
1
PGOOD Open-drain power-good status outputs. Connect to VCC through a 100k resistor. Output will be high when all outputs are
within regulation with no faults detected.
2
3
FSET2
FCCM
VCC
Frequency control input for SMPS2. Connect a resistor to ground to program the switching frequency. The pin output is
a pulsed current and requires a decoupling capacitor to average the signal.
Logic input to control efficiency mode. Logic high forces continuous conduction mode (CCM). Logic low allows full
discontinuous conduction mode (DCM). Float this pin for ultrasonic DCM operation.
4
5
6
Analog power supply input for reference voltages and currents. Bypass to ground with a 1µF ceramic capacitor near the IC.
LDO3EN Logic input for enabling and disabling the LDO3 linear regulator. Positive logic input.
FSET1
Frequency control input for SMPS1. Connect a resistor to ground to program the switching frequency. The pin output is
a pulsed current and requires a decoupling capacitor to average the signal.
7
8
FB1
SMPS1 feedback input used for output voltage programming and regulation.
VOUT1 SMPS1 output voltage sense input. Used for soft-discharge.
ISEN1 SMPS1 DCR current sense input. Used for overcurrent protection and R regulation.
OCSET1 Input from DCR current-sensing network used to program the overcurrent shutdown threshold for SMPS1.
3
9
10
11
EN1
Logic input to enable and disable SMPS1. A logic high will immediately enable SMPS1. Floating this pin will enable
SMPS1 only after SMPS2 has been enabled and achieved regulation. A logic low disables SMPS1.
12
PHASE1 SMPS1 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS
source, the synchronous NMOS drain, and the output inductor for SMPS1.
13
14
15
16
17
18
19
20
21
22
23
UGATE1 High-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 switching FET.
BOOT1 SMPS1 bootstrap input for the switching NMOS gate drivers. Connect to SMPS1 PHASE with a ceramic capacitor of 0.22µF.
LGATE1 Low-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 synchronous FET.
LDO3
VIN
3.3V linear regulator output, capable of providing 100mA continuous current. Bypass to ground with a 4.7µF ceramic capacitor.
Feed-forward input for line voltage transient compensation. Connect to the power train input voltage.
5V power source for SMPS gate drive current. Bypass to ground with a 4.7µF ceramic capacitor.
Power ground for SMPS1 and SMPS2. This provides a return path for synchronous FET switching currents.
PVCC
PGND
LGATE2 Low-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 synchronous FET.
BOOT2 SMPS2 bootstrap input for the switching NMOS gate drivers. Connect to SMPS2 PHASE with a ceramic capacitor of 0.22µF.
UGATE2 High-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 switching FET.
PHASE2 SMPS2 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS
source, the synchronous NMOS drain, and the output inductor for SMPS2.
24
EN2
Logic input to enable and disable SMPS2. A logic high will immediately enable SMPS2. Floating this pin will enable
SMPS2 only after SMPS1 has been enabled and achieved regulation. A logic low disables SMPS2.
25
26
27
28
OCSET2 Input from DCR current-sensing network used to program the overcurrent shutdown threshold for SMPS2.
3
ISEN2
SMPS2 DCR current sense input. Used for overcurrent protection and R regulation.
VOUT2 SMPS2 output voltage sense input. Used for soft-discharge and switchover for PVCC 5V LDO.
FB2
SMPS2 feedback input used for output voltage programming and regulation.
Analog ground for analog and logic signals.
Bottom
Pad
GND
FN6666 Rev 8.00
August 25, 2015
Page 6 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Typical Application Circuits
The typical application circuits generate the 5V/8A and 3.3V/8A (system regulator), or 1.05V/15A and 1.5V/15A (chip set) supplies
in a notebook computer. The input supply (VBAT) range is 5.5V to 25V.
V B A T
4x10µF
V IN
B O O T 1
B O O T 2
0.22µF
4.7µH
0.22µF
4.7µH
IRF7821
IRF7821
IRF7832
U G A T E 1
P H A S E 1
U G A T E 2
P H A S E 2
5 V
3 .3 V
330µF
0.022µF
14k
330µF
0.022µF 14k
14k
14k
IRF7832
L G A T E 1
L G A T E 2
750
1200pF
750
O C S E T 1
IS E N 1
O C S E T 2
IS E N 2
45.3k
10k
68.1k
9.09k
1200pF
V O U T 1
V O U T 2
F B 1
F B 2
ISL62391, ISL62392
ISL62391C, ISL62392C
100k
P G O O D
P V C C
L D O 3
4.7µF
1µF
E N 1
E N 2
L D O 3 E N
F C C M
F S E T 1
F S E T 2
P V C C
V C C
1µF
P G N D
P A D
0.01µF
24.3k
0.01µF
19.6k
FIGURE 1. TYPICAL SYSTEM REGULATOR APPLICATION CIRCUIT WITH INDUCTOR DCR CURRENT SENSE
V B A T
V IN
B O O T 1
B O O T 2
4x10µF
IRF7821
IRF7832
IRF7821
IRF7832
0.22µF
4.7µH
0.22µF
4.7µH
U G A T E 1
P H A S E 1
U G A T E 2
P H A S E 2
3 .3 V
5V
0.001
1k
0.001
1k
1k
330µF
330µF
L G A T E 1
L G A T E 2
1k
750
750
O C S E T 1
IS E N 1
O C S E T 2
IS E N 2
68.1k
45.3k
10k
1200pF
1200pF
V O U T 1
V O U T 2
F B 1
F B 2
9.09k
ISL62391, ISL62392
ISL62391C, ISL62392C
100k
P G O O D
P V C C
E N 1
E N 2
3 .3 V
L D O 3
L D O 3E N
4.7µF
F C C M
F S E T 1
F S E T 2
P V C C
V C C
1µF
1µF
0.01µF
P G N D
G N D
24.3k
0.01µF
19.6k
FIGURE 2. TYPICAL SYSTEM REGULATOR APPLICATION CIRCUIT WITH RESISTOR SENSE
FN6666 Rev 8.00
August 25, 2015
Page 7 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Typical Application Circuits (Continued)
V B A T
V IN
4x10µF
0.22µF
B O O T 1
B O O T 2
0.22µF
2.2µH
IRF7821
IRF7821
2x
U G A T E 1
P H A S E 1
U G A T E 2
P H A S E 2
2.2µH
0.022µF
14k
1 .0 5 V
1 .5 V
2x
2x330µF
0.022µF
14k
2x330µF
14k
14k
2x
IRF7832
L G A T E 1
L G A T E 2
IRF7832
2x
590
590
O C S E T 1
IS E N 1
O C S E T 2
IS E N 2
36.5k
48.7k
36.5k
24.3k
1800pF
1800pF
V O U T 1
V O U T 2
F B 1
F B 2
ISL62391, ISL62392
ISL62391C, ISL62392C
100k
P G O O D
P V C C
L D O 3
E N 1
E N 2
4.7µF
1µF
L D O 3 E N
F C C M
F S E T 1
F S E T 2
P V C C
V C C
1µF
P G N D
0.01µF
P A D
17.4k
0.01µF
14k
FIGURE 3. TYPICAL CHIP SET APPLICATION CIRCUIT WITH INDUCTOR DCR CURRENT SENSE
V B A T
4x10µF
V IN
B O O T 1
B O O T 2
IRF7821
IRF7832
IRF7821
IRF7832
0.22µF
2.2µH
0.22µF
2.2µH
U G A T E 1
P H A S E 1
U G A T E 2
P H A S E 2
2x
2x
2x
0.001
1k
1.05V
1.5V
0.001
1k
1k
2x330µF
2x330µF
L G A T E 1
L G A T E 2
2x
1k
590
590
O C S E T 1
IS E N 1
O C S E T 2
IS E N 2
36.5k
36.5k
1800pF
1800pF
V O U T 1
V O U T 2
F B 1
F B 2
24.3k
ISL62391, ISL62392
ISL62391C, ISL62392C
48.7k
100k
P G O O D
P V C C
E N 1
E N 2
3 .3 V
L D O 3
L D O 3E N
4.7µF
F C C M
F S E T 1
F S E T 2
P V C C
V C C
1µF
1µF
0.01µF
P G N D
G N D
17.4k
0.01µF
14k
FIGURE 4. TYPICAL CHIP SET APPLICATION CIRCUIT WITH RESISTOR SENSE
FN6666 Rev 8.00
August 25, 2015
Page 8 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Block Diagram
VIN
VOUT2*
FSET1/2
4.8V
5V
LDO
FB1/2
R3
MODULATOR
PVCC
VREF
0.6V
BOOT1/2
FCCM
PWM
UGATE
DRIVER
UGATE1/2
PHASE1/2
VOUT1/2
SOFT DISCHARGE
LGATE
LGATE1/2
DRIVER
PGND
EN1
EN2
PGOOD
START-UP
AND
SHUTDOWN
LOGIC
LDO3EN
VCC
BIAS AND
REFERENCE
10µA
OCSET1/2
ISEN1/2
OCP
UVP
OVP
T-PAD
PROTECTION LOGIC
OVP/UVP/OCP/OTP
PVCC
VREF + 16%
3.3V
LDO
LDO3
FB1/2
VREF - 16%
THERMAL
MONITOR
SOFT DISCHARGE
*In addition to being used for regulation, VOUT2 will also provide power for PVCC when it is programmed to 5V.
FN6666 Rev 8.00
August 25, 2015
Page 9 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Typical Performance Curves
100
95
90
85
80
75
70
65
60
55
50
100
V
= 7V
IN
V
= 7V
IN
95
90
85
80
75
70
65
60
55
50
V
= 12V
V
= 12V
IN
IN
V
= 19V
V
= 19V
IN
IN
0.01
0.10
1.00
10.00
0.10
1.00
(A)
10.00
I
(A)
I
OUT
OUT
FIGURE 5. CHANNEL 1 EFFICIENCY AT V = 3.3V, DEM
O
FIGURE 6. CHANNEL 2 EFFICIENCY AT V = 5V, DEM
O
OPERATION. HIGH-SIDE 1xIRF7821,
OPERATION. HIGH-SIDE 1xIRF7821,
r
r
F
= 9.1m; LOW-SIDE 1xIRF7832,
r
r
F
= 9.1m; LOW-SIDE 1xIRF7832,
= 4m; L = 4.7µH, DCR = 14.3m; CCM
= 330kHz
DS(ON)
DS(ON)
DS(ON)
DS(ON)
= 4m; L = 4.7µH, DCR = 14.3m; CCM
= 270kHz
SW
SW
V
V
O1
O1
FB1
FB1
PGOOD
PGOOD
PHASE1
PHASE1
FIGURE 8. POWER-OFF, V = 12V, I = 5A, V = 3.3V
IN
FIGURE 7. POWER-ON, V = 12V, LOAD = 5A, V = 3.3V
O
O
IN
O
V
O1
V
O1
FB1
FB1
PGOOD
EN1
PGOOD
EN1
FIGURE 9. ENABLE CONTROL, EN1 = HIGH, V = 12V,
IN
FIGURE 10. ENABLE CONTROL, EN1 = LOW, V = 12V,
IN
V
= 3.3V, I = 5A
V
= 3.3V, I = 5A
O
O
O
O
FN6666 Rev 8.00
August 25, 2015
Page 10 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Typical Performance Curves (Continued)
V
V
O1
O1
PHASE1
PHASE1
V
V
O2
O2
PHASE2
PHASE2
FIGURE 11. CCM STEADY-STATE OPERATION, V = 12V,
IN
FIGURE 12. DCM STEADY-STATE OPERATION, V = 12V,
IN
V
= 3.3V, I = 5A, V = 5V, I = 5A
V
= 3.3V, I = 0. 2A, V = 5V, I = 0.2A
O1
O1 O2 O2
O1 O1 O2 O2
V
O1
V
O1
PHASE1
PHASE1
V
O2
PHASE2
I
O1
FIGURE 13. AUDIO FILTER OPERATION, V = 12V,
IN
FIGURE 14. TRANSIENT RESPONSE, V = 12V, V = 3.3V,
IN
O
V
= 3.3V, V = 5V, NO LOAD
I = 0.1A/8.1A @ 2.5A/µs
O1
O2
O
V
O1
V
O1
PHASE1
PHASE1
I
O1
I
O1
FIGURE 15. LOAD INSERTION RESPONSE, V = 12V,
IN
FIGURE 16. LOAD RELEASE RESPONSE, V = 12V,
IN
V
= 3.3V, I = 0.1A/8.1A @ 2.5A/µs
V = 3.3V, I = 0.1A/8.1A @ 2.5A/µs
O
O
O O
FN6666 Rev 8.00
August 25, 2015
Page 11 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Typical Performance Curves (Continued)
EN1
EN2
V
O1
V
V
O1
O2
V
O2
FIGURE 17. DELAYED START, V = 12V, V = 3.3V, V = 5V,
FIGURE 18. DELAYED START, V = 12V, V = 3.3V, V = 5V,
IN
O1
O2
IN
O1
O2
EN2 = FLOAT, NO LOAD
EN1 = FLOAT, NO LOAD
V
V
O1
O1
PGOOD
I
O1
V
O2
PGOOD
FIGURE 19. DELAYED START, V = 12V, V = 3.3V, V = 5V,
IN O1 O2
FIGURE 20. OVERCURRENT PROTECTION, V = 12V,
IN
EN1 = 1, EN2 = FLOAT, NO LOAD
V = 3.3V
O
V
O1
V
O1
UGATE1-PHASE1
UGATE1-PHASE1
LGATE1
LGATE1
PGOOD
PGOOD
FIGURE 21. CROWBAR OVERVOLTAGE PROTECTION,
= 12V, V = 3.3V, NO LOAD
FIGURE 22. TRI-STATE OVERVOLTAGE PROTECTION,
= 12V, V = 3.3V, NO LOAD
V
V
IN
IN
O
O
FN6666 Rev 8.00
August 25, 2015
Page 12 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
A window voltage V is referenced with respect to the error
Theory of Operation
W
amplifier output voltage V
, creating an envelope into
COMP
Three Output Controller
which the ripple voltage V is compared. The amplitude of V
R
W
The ISL62391, ISL62392, ISL62391C and ISL62392C generate
three regulated output voltages. Two are produced with switch-
mode power supplies (SMPS), and the third by a low dropout
linear regulator (LDO). An additional 5V LDO (PVCC) is used to
power the chip during operation, allowing the ISL62391,
ISL62392, ISL62391C and ISL62392C to regulate all outputs
from a single power source (VIN) with no need for a separate
quiescent supply. This makes the ISL62391, ISL62392,
ISL62391C and ISL62392C an ideal choice as system regulator
for notebook PCs. Because the two SMPS channels are
identical and almost entirely independent, all conclusions drawn
apply to both channels unless otherwise noted.
is set by a resistor, R , connected across the FSET and GND
W
pins. The V
V
and V signals feed into a window
R, COMP,
comparator in which V
W
is the lower threshold voltage and
COMP
is the higher threshold voltage. Figure 23 shows PWM
V
W
pulses being generated as V traverses the V and V
R
W
COMP
thresholds. The PWM switching frequency is proportional to
the slew rates of the positive and negative slopes of V it is
R;
inversely proportional to the voltage between V and V
W
COMP.
Equation 3 illustrates how to calculate the window size based
on output voltage and frequency set resistor.
(EQ. 3)
(EQ. 4)
V
= g V
1 – D R
OUT W
W
m
The frequency can be expressed in Equation 4:
1
Modulator and Switching Frequency
-----------------
=
F
The ISL62391, ISL62392, ISL62391C and ISL62392C
SW
K R
W
3
modulator feature Intersil’s R technology, a hybrid of fixed
frequency PWM and variable frequency hysteretic control.
Intersil’s R technology can simultaneously affect the PWM
Inverting Equation 4 allows easy selection of R for a desired
W
3
F
:
SW
switching frequency and PWM duty cycle in response to input
1
K F
(EQ. 5)
--------------------
R
=
3
W
voltage and output load transients. The R modulator
SW
synthesizes an AC signal, V , which is an analog
R
For Equations 3 through 5:
= 1.66µs
representation of the output inductor ripple current. The duty-
cycle of V is the result of charge and discharge current
R
g
m
through a ripple capacitor, C . The current through C is
R
R
-10
K = 1.7 x 10
D = V /V
(±20%)
provided by a transconductance amplifier that measures the
VIN and VO pin voltages. The positive slope of V can be
OUT IN
R
written as Equation 1:
Power-On Reset
(EQ. 1)
V
= g V – V
OUT
The ISL62391, ISL62392, ISL62391C and ISL62392C are
disabled until the voltage at the VIN pin has increased above
the rising power-on reset (POR) threshold. Conversely, the
controller will be disabled when the voltage at the VIN pin
decreases below the falling POR threshold.
RPOS
m
IN
The negative slope of V can be written as Equation 2:
R
(EQ. 2)
V
= g V
m OUT
RNEG
Where g is the gain of the transconductance amplifier.
m
In addition to VIN POR, the PVCC pin is also monitored. If its
voltage falls below 4.2V, the SMPS outputs will be shut down.
This ensures that there is sufficient BOOT voltage to enhance
the upper MOSFET.
WINDOW VOLTAGE V
W
RIPPLE CAPACITOR VOLTAGE C
R
(WRT V
)
COMP
EN, Soft-Start and PGOOD
The ISL62391, ISL62392, ISL62391C and ISL62392C use a
digital soft-start circuit to ramp the output voltage of each
SMPS to the programmed regulation setpoint at a predictable
slew rate. The slew rate of the soft-start sequence has been
selected to limit the in-rush current through the output
ERROR AMPLIFIER
VOLTAGE V
COMP
capacitors as they charge to the desired regulation voltage.
When the EN pins are pulled above their rising thresholds, the
PWM
PGOOD Soft-Start Delay, t , starts and the output voltage
SS
begins to rise. The FB pin ramps to 0.6V in approximately 1.5ms
and the PGOOD pin goes to high impedance approximately
1.25ms after the FB pin voltage reaches 0.6V.
FIGURE 23. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
FN6666 Rev 8.00
August 25, 2015
Page 13 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
above the 4.2V VCC POR threshold, VCC will switchover to
PVCC internally.
1.5ms
VO
tSOFTSTART
After VIN is applied, the VCC start-up 3.6V voltage can be used
as the logic high signal of any of EN1, EN2 and LDO3EN to
enable PVCC if there is no other power supply on the board.
VCC AND PVCC
EN
MOSFET Gate-Drive Outputs LGATE and UGATE
FB
The ISL62391, ISL62392, ISL62391C and ISL62392C have
internal gate-drivers for the high-side and low-side N-Channel
MOSFETs. The low-side gate-drivers are optimized for low
duty-cycle applications where the low-side MOSFET
PGOOD
2.75ms
PGOOD DELAY
conduction losses are dominant, requiring a low r
DS(ON)
MOSFET. The LGATE pull-down resistance is small in order to
clamp the gate of the MOSFET below the V at turn-off. The
FIGURE 24. SOFT-START SEQUENCE FOR ONE SMPS
GS(th)
current transient through the gate at turn-off can be considerable
because the gate charge of a low r MOSFET can be large.
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. It is an undefined impedance if V
IN
DS(ON)
is not above the rising POR threshold or below the POR falling
threshold. When a fault is detected, the ISL62391, ISL62392,
ISL62391C and ISL62392C will turn on the open-drain NMOS,
which will pull PGOOD low with a nominal impedance of 32
This will flag the system that one of the output voltages is out of
regulation.
Adaptive shoot-through protection prevents a gate-driver output
from turning on until the opposite gate-driver output has fallen
below approximately 1V. The dead-time shown in Figure 25 is
extended by the additional period that the falling gate voltage
stays above the 1V threshold. The typical dead-time is 21ns. The
high-side gate-driver output voltage is measured across the
UGATE and PHASE pins while the low-side gate-driver output
voltage is measured across the LGATE and PGND pins. The
power for the LGATE gate-driver is sourced directly from the
PVCC pin. The power for the UGATE gate-driver is sourced from
a “boot” capacitor connected across the BOOT and PHASE pins.
The boot capacitor is charged from the 5V PVCC supply through
a “boot diode” each time the low-side MOSFET turns on, pulling
the PHASE pin low. The ISL62391, ISL62392, ISL62391C and
ISL62392C have integrated boot diodes connected from the
PVCC pins to BOOT pins.
Separate enable pins allow for full soft-start sequencing.
Because low shutdown quiescent current is necessary to
prolong battery life in notebook applications, the PVCC 5V LDO
is held off until any of the three enable signals (EN1, EN2 or
LDO3EN) are pulled high. Soft-start of all outputs will only start
until after PVCC is above the 4.2V POR threshold. In addition to
user-programmable sequencing, the ISL62391, ISL62392,
ISL62391C and ISL62392C include a pre-programmed
sequential SMPS soft-start feature. Table 1 shows the SMPS
enable truth table.
TABLE 1. SMPS ENABLE SEQUENCE LOGIC
t
t
UGFLGR
LGFUGR
EN1
EN2
START-UP SEQUENCE
All SMPS outputs OFF
0
0
0
FLOAT All SMPS outputs OFF
50%
0
FLOAT
FLOAT
FLOAT
1
1
0
SMPS1 OFF, SMPS2 ON
All SMPS outputs OFF
UGATE
LGATE
FLOAT All SMPS outputs OFF
1
0
SMPS1 enables after SMPS2 is in regulation
SMPS1 ON, SMPS2 OFF
50%
1
FLOAT SMPS2 enables after SMPS1 is in regulation
All SMPS outputs ON simultaneously
1
1
FIGURE 25. LGATE AND UGATE DEAD-TIME
VCC
Diode Emulation
The VCC nominal operation voltage is 5V. If EN1, EN2 and
LDO3EN are all logic low, the VCC start-up voltage is 3.6V
when VIN is applied on ISL62391, ISL62392, ISL62391C and
ISL62392C. PVCC is held off until any of the three enable
signals (EN1, EN2 or LDO3EN) is pulled high. When PVCC is
FCCM is a logic input that controls the power state of the
ISL62391, ISL62392, ISL62391C and ISL62392C. If forced
high, the ISL62391, ISL62392, ISL62391C and ISL62392C will
operate in forced continuous-conduction-mode (CCM) over the
entire load range. This will produce the best transient response
FN6666 Rev 8.00
August 25, 2015
Page 14 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
to all load conditions, but will have increased light-load power
loss. If FCCM is forced low, the ISL62391, ISL62392,
ISL62391C and ISL62392C will automatically operate in Diode
Emulation Mode (DEM) at light load to optimize efficiency in the
entire load range. The transition is automatically achieved by
detecting the load current and turning off LGATE when the
inductor current reaches 0A.
allow DEM at light loads, but will prevent the switching
frequency from going below ~28kHz to prevent noise injection
to the audio band. A timer is reset each PWM pulse. If the
timer exceeds 30µs, LGATE is turned on, causing the ramp
voltage to reduce until another UGATE is commanded by the
voltage loop.
Overcurrent Protection
Positive-going inductor current flows from either the source of
the high-side MOSFET, or the drain of the low-side MOSFET.
Negative-going inductor current flows into the drain of the low-
side MOSFET. When the low-side MOSFET conducts positive
inductor current, the phase voltage will be negative with
respect to the GND and PGND pins. Conversely, when the
low-side MOSFET conducts negative inductor current, the
phase voltage will be positive with respect to the GND and
PGND pins. The ISL62391, ISL62392, ISL62391C and
ISL62392C monitor the phase voltage when the low-side
MOSFET is conducting inductor current to determine its
direction.
The overcurrent protection (OCP) setpoint is programmed with
resistor, R
, that is connected across the OCSET and
OCSET
PHASE pins.
L
DCR
V
I
O
L
PHASE1
_
V
+
DCR
C
SEN
R
ISL62391,
ISL62392
OCSET
C
O
_
10µA
V
+
ROCSET
OCSET1
R
O
ISEN1
When the output load current is greater than or equal to ½ the
inductor ripple current, the inductor current is always positive,
and the converter is always in CCM. The ISL62391, ISL62392,
ISL62391C and ISL62392C minimize the conduction loss in
this condition by forcing the low-side MOSFET to operate as a
synchronous rectifier.
FIGURE 26. OVERCURRENT-SET CIRCUIT
Figure 26 shows the overcurrent-set circuit for SMPS1. The
inductor consists of inductance L and the DC resistance
(DCR). The inductor DC current I creates a voltage drop
L
across DCR, which is given by Equation 6:
When the output load current is less than ½ the inductor ripple
current, negative inductor current occurs. Sinking negative
inductor through the low-side MOSFET lowers efficiency
through unnecessary conduction losses. The ISL62391,
ISL62392, ISL62391C and ISL62392C automatically enter
DEM after the PHASE pin has detected positive voltage and
LGATE was allowed to go high for 8 consecutive PWM
switching cycles. The ISL62391, ISL62392, ISL62391C and
ISL62392C will turn off the low-side MOSFET once the phase
voltage turns positive, indicating negative inductor current. The
ISL62391, ISL62392, ISL62391C and ISL62392C will return to
CCM on the following cycle after the PHASE pin detects
negative voltage, indicating that the body diode of the low-side
MOSFET is conducting positive inductor current.
(EQ. 6)
V
= I
L DCR
DCR
The ISL62391, ISL62392, ISL62391C and ISL62392C sink a
10µA current into the OCSET1 pin, creating a DC voltage drop
across the resistor R
, which is given by Equation 7:
OCSET
= 10A R
OCSET
(EQ. 7)
V
ROCSET
Resistor R is connected between the ISEN1 pin and the
O
actual output voltage of the converter. During normal
operation, the ISEN1 pin is a high impedance path, therefore
there is no voltage drop across R . The DC voltage difference
O
between the OCSET1 pin and the ISEN1 pin can be
established using Equation 8:
Efficiency can be further improved with a reduction of
V
–V
= I
ISEN1
L DCR – 10A ROCSET
OCSET1
unnecessary switching losses by reducing the PWM frequency.
(EQ. 8)
3
It is characteristic of the R architecture for the PWM
frequency to decrease while in diode emulation. The extent of
the frequency reduction is proportional to the reduction of load
current. Upon entering DEM, the PWM frequency makes an
initial step-reduction because of a 33% step-increase of the
The ISL62391, ISL62392, ISL62391C and ISL62392C monitor
the OCSET1 pin and the ISEN1 pin voltages. Once the
OCSET1 pin voltage is higher than the ISEN1 pin voltage for
more than 10µs, the ISL62391, ISL62392, ISL62391C and
window voltage V
.
W
ISL62392C declare an OCP fault. The value of R
written as Equation 9:
is then
OCSET
Because the switching frequency in DEM is a function of load
current, very light load conditions can produce frequencies well
into the audio band. This can be problematic if audible noise is
coupled into audio amplifier circuits. To prevent this from
occurring, the ISL62391, ISL62392, ISL62391C and
I
OC DCR
10A
---------------------------
=
R
OCSET
(EQ. 9)
ISL62392C allow the user to float the FCCM input. This will
FN6666 Rev 8.00
August 25, 2015
Page 15 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Where:
until the EN pin has been pulled below the falling EN threshold
voltage, or until V has decayed below the falling POR
- R
OCSET
() is the resistor used to program the
IN
threshold. During the latch condition, the ISL62391 and
ISL62391C will tri-state the PHASE node by turning both
UGATE and LGATE off until the latch is cleared.
overcurrent setpoint
- I is the output current threshold that will activate the
OC
OCP circuit
- DCR is the inductor DC resistance
Although latched, the ISL62392 and ISL62392C LGATE gate-
driver output will retain the ability to toggle the low-side
MOSFET on and off in response to the output voltage
transversing the OVP rising and falling thresholds. The LGATE
gate-driver will turn on the low-side MOSFET to discharge the
output voltage, thus protecting the load from potentially
damaging voltage levels. The LGATE gate-driver will turn off the
low-side MOSFET once the FB pin voltage is lower than the
falling overvoltage threshold for more than 2µs. The falling
overvoltage threshold is typically 106% of the reference voltage,
or 1.06*0.6V = 0.636V. This soft-crowbar process repeats as
long as the output voltage fault is present, allowing the ISL62392
and ISL62392C to protect against persistent overvoltage
conditions.
For example, if I
is 20A and DCR is 4.5m, the choice of
= 20A x 4.5m/10µA = 9k
OC
R
is R
OCSET
OCSET
Resistor R
and capacitor C
form an R-C network to
SEN
OCSET
sense the inductor current. To sense the inductor current
correctly, not only in DC operation but also during dynamic
operation, the R-C network time constant R
-C
OCSET SEN
needs to match the inductor time constant L/DCR. The value of
C
is then written as Equation 10:
SEN
L
-----------------------------------------
C
=
SEN
OCSET DCR
R
(EQ. 10)
For example, if L is 1.5µH, DCR is 4.5m, and R
OCSET
is 9k
the choice of C
= 1.5µH/(9kx 4.5m) = 0.037µF
SEN
Undervoltage Protection
Upon converter start-up, the C capacitor bias is 0V. To
SEN
The UVP fault detection circuit triggers after the FB pin voltage is
below the undervoltage threshold for more than 2µs. The
undervoltage threshold is typically 86% of the reference voltage,
or 0.86*0.6V = 0.516V. If a UVP fault is declared, the PGOOD
pin will pull-down with 32and latch-off the converter. The fault
will remain latched until the EN pin has been pulled below the
prevent false OCP during this time, a 10µA current source
flows out of the ISEN1 pin, generating a voltage drop on the
R
resistor, which should be chosen to have the same
O
resistance as R
. When the PGOOD pin goes high, the
OCSET
ISEN1 pin current source will be removed.
When an OCP fault is declared, the PGOOD pin will pull-down
to 32and latch-off the converter. The fault will remain latched
until the EN pin has been pulled below the falling EN threshold
falling enable threshold, or if V has decayed below the falling
POR threshold.
IN
Programming the Output Voltage
voltage, or until V has decayed below the falling POR
IN
When the converter is in regulation, there will be 0.6V between
the FB and GND pins. Connect a two-resistor voltage divider
across the OUT and GND pins with the output node connected
to the FB pin, as shown in Figure 27. Scale the voltage-divider
network such that the FB pin is 0.6V with respect to the GND
pin when the converter is regulating at the desired output
voltage. The output voltage can be programmed from 0.6V to
5.5V.
threshold.
When using a discrete current sense resistor, inductor
time-constant matching is not required. Equation 7 remains
unchanged, but Equation 8 is modified in Equation 11:
(EQ. 11)
V
–V
= I
– 10A R
L RSENSE
OCSET
OCSET1
ISEN1
Furthermore, Equation 9 is changed in Equation 12:
Programming the output voltage is written as Equation 13:
R
I
OC RSENSE
-------------------------------------
=
(EQ. 12)
R
OCSET
10A
TOP
----------------------------
(EQ. 13)
V
= V
REF 1 +
OUT
R
BOTTOM
Where R
is the series power resistor for sensing
inductor current. For example, with an R = 1m and an
SENSE
Where:
- V
SENSE
is the desired output voltage of the converter
OCP target of 10A, R
= 1k
OUT
OCSET
- The voltage to which the converter regulates the FB pin is
the V (0.6V)
Overvoltage Protection
REF
is the voltage-programming resistor that connects
The OVP fault detection circuit triggers after the FB pin voltage
is above the rising overvoltage threshold for more than 2µs.
The FB pin voltage is 0.6V in normal operation. The rising
overvoltage threshold is typically 116% of that value, or
1.16*0.6V = 0.696V.
- R
TOP
from the FB pin to the converter output. In addition to
setting the output voltage, this resistor is part of the loop
compensation network
- R
is the voltage-programming resistor that
connects from the FB pin to the GND pin
BOTTOM
For ISL62391, ISL62392, ISL62391C and ISL62392C, when an
OVP fault is declared, the PGOOD pin will pull-down with 32
and latch-off the converter. The OVP fault will remain latched
Choose R
first when compensating the control loop, and
TOP
then calculate R
according to Equation 14:
BOTTOM
FN6666 Rev 8.00
August 25, 2015
Page 16 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
power dissipation. The outputs will remain off until the junction
temperature has fallen below +135°C.
V
REF R
TOP
-------------------------------------
=
(EQ. 14)
R
BOTTOM
V
– V
REF
OUT
General Application Design Guide
Compensation Design
This design guide is intended to provide a high-level explanation
of the steps necessary to design a single-phase power
converter. It is assumed that the reader is familiar with many of
the basic skills and techniques referenced in the following
section. In addition to this guide, Intersil provides complete
reference designs that include schematics, bills of materials, and
example board layouts.
Figure 27 shows the recommended Type-II compensation circuit.
The FB pin is the inverting input of the error amplifier. The COMP
signal, the output of the error amplifier, is inside the chip and
unavailable to users. C
is a 100pF capacitor integrated inside
INT
the IC that connects across the FB pin and the COMP signal.
, R , C and C form the Type-II compensator. The
R
TOP FB FB INT
frequency domain transfer function is given by Equation 15:
Selecting the LC Output Filter
1 + s R
+ R C
FB
TOP
FB
-------------------------------------------------------------------------------------------
s =
G
(EQ. 15)
COMP
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as
Equation 16:
TOP CINT 1 + s RFB C
s R
FB
C
C
= 100pF
FB
INT
V
O
R
FB
---------
(EQ. 16)
D =
V
IN
R
TOP
The output inductor peak-to-peak ripple current is written as
Equation 17:
VO
-
FB
EA
V
O 1 – D
R
(EQ. 17)
COMP
-----------------------------
=
PP
BOTTOM
I
SW L
f
+
A typical step-down DC/DC converter will have an I
of 20%
REF
P-P
ISL62391, ISL62392
to 40% of the maximum DC output load current. The value of
I
is selected based upon several criteria, such as MOSFET
P-P
FIGURE 27. COMPENSATION REFERENCE CIRCUIT
switching loss, inductor core loss, and the resistive loss of the
inductor winding. The DC copper loss of the inductor can be
estimated by Equation 18:
The LC output filter has a double pole at its resonant frequency
that causes rapid phase change. The R modulator used in the
3
2
ISL62391, ISL62392, ISL62391C and ISL62392C make the LC
output filter resemble a first order system in which the closed loop
stability can be achieved with the recommended Type-II
compensation network. Intersil provides a PC-based tool
(example page is shown later) that can be used to calculate
compensation network component values and help simulate
the loop frequency response.
(EQ. 18)
P
= I
DCR
COPPER
LOAD
Where I
LOAD
is the converter output DC current.
The copper loss can be significant so attention has to be given
to the DCR selection. Another factor to consider when
choosing the inductor is its saturation characteristics at
elevated temperature. A saturated inductor could cause
destruction of circuit components, as well as nuisance OCP
faults.
3.3V Linear Regulator
In addition to the two SMPS outputs, the ISL62391, ISL62392,
ISL62391C and ISL62392C also provide a fixed 3.3V LDO output
(LDO3) capable of sourcing 100mA continuous current. LDO3
draws its power from PVCC and can be independently enabled
from both SMPS channels.
A DC/DC buck regulator must have output capacitance C into
O
which ripple current I
can flow. Current I develops a
P-P
P-P
corresponding ripple voltage V
P-P
of the voltage drop across the capacitor ESR and of the voltage
across C which is the sum
O,
change stemming from charge moved in and out of the
LDO3 also has a current limit feature with a nominal level of
180mA. Currents in excess of the limit will cause the LDO3
voltage to drop dramatically, limiting the power dissipation.
capacitor. These two voltages are written as Equation 19:
(EQ. 19)
V
= I
P-P ESR
ESR
Thermal Monitor and Protection
and Equation 20:
I
LDO3 and PVCC LDOs can dissipate non-trivial power inside the
ISL62391, ISL62392, ISL62391C and ISL62392C at high input-
to-output voltage ratios and full load conditions. To protect the
silicon, ISL62391, ISL62392, ISL62391C and ISL62392C
continually monitor the die temperature. If the temperature
exceeds +150°C, all outputs will be turned off to sharply curtail
P-P
-----------------------------
(EQ. 20)
V
=
C
8 C
O f
SW
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled to
reduce the total ESR until the required V
is achieved. The
P-P
inductance of the capacitor can cause a brief voltage dip if the
FN6666 Rev 8.00
August 25, 2015
Page 17 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
load transient has an extremely high slew rate. Low inductance
capacitors should be considered in this scenario. A capacitor
dissipates heat as a function of RMS current and frequency. Be
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
sure that I
is shared by a sufficient quantity of paralleled
capacitors so that they operate below the maximum rated RMS
P-P
have a maximum V rating that exceeds the sum of the upper
DS
current at f . Take into account that the rated value of a
SW
voltage tolerance of the input power source and the voltage
spike that occurs when the MOSFET switches off.
capacitor can fade as much as 50% as the DC voltage across it
increases.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low gate charge so that the
device spends the least amount of time dissipating power in
the linear region. Unlike the low-side MOSFET, which has the
drain-source voltage clamped by its body diode during turn off,
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25x greater than the
maximum input voltage, while a voltage rating of 1.5x is a
preferred rating. Figure 28 is a graph of the input RMS ripple
current (normalized relative to output load current) as a function
of duty cycle and is adjusted for a converter efficiency of 80%.
The ripple current calculation is written as Equation 21:
2
the high-side MOSFET turns off with a V
of approximately
DS
V
- V
, plus the spike across it. The preferred low-side
IN OUT
MOSFET emphasizes low r
when fully saturated to
DS(ON)
minimize conduction loss. It should be noted that this is an
optimal configuration of MOSFET selection for low duty cycle
applications (D < 50%). For higher output, low input voltage
solutions, a more balanced MOSFET selection for high- and
low-side devices may be warranted.
2
x
12
(EQ. 21)
------
I
=
D – D + D
IN_RMS NORMALIZED
For the low-side (LS) MOSFET, the power loss can be assumed
to be conductive only and is written as Equation 23:
Where:
- I
2
P
I
r
DSON_LS 1 – D
(EQ. 23)
CON_LS
LOAD
is the maximum continuous I
of the converter
LOAD
MAX
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a percentage
For the high-side (HS) MOSFET, the conduction loss is written
as Equation 24:
of I
(0% to 100%)
MAX
- D is the duty cycle that is adjusted to take into account the
efficiency of the converter which is written as Equation 22.
2
P
= I
r
DSON_HS D
(EQ. 24)
CON_HS
LOAD
V
O
(EQ. 22)
--------------------------
D =
For the high-side MOSFET, the switching loss is written as
Equation 25:
V
EFF
IN
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain of
the high-side MOSFET and the source of the low-side
MOSFET.
V
IN IVALLEY tON f
IN IPEAK tOFF f
V
SW
SW
---------------------------------------------------------------- -------------------------------------------------------------
P
=
+
SW_HS
2
2
(EQ. 25)
Where:
- I
is the difference of the DC component of the
0.60
0.55
0.50
0.45
0.40
0.35
VALLEY
inductor current minus 1/2 of the inductor ripple current
- I is the sum of the DC component of the inductor
PEAK
current plus 1/2 of the inductor ripple current
- t
- t
is the time required to drive the device into saturation
ON
is the time required to drive the device into cut-off
OFF
0.30
x = 1
Selecting The Bootstrap Capacitor
0.25
0.20
0.15
0.10
0.05
0
x = 0.75
x = 0.50
x = 0.25
x = 0
The selection of the bootstrap capacitor is written as Equation
26:
Q
g
-----------------------
(EQ. 26)
C
=
BOOT
V
BOOT
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY CYCLE
1.0
FIGURE 28. NORMALIZED RMS INPUT CURRENT
FN6666 Rev 8.00
August 25, 2015
Page 18 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Where:
Co
L2
- Q is the total gate charge required to turn on the
g
high-side MOSFET
PIN 18 (PVCC)
- V
, is the maximum allowed voltage decay across
BOOT
PIN 4 (VCC)
the boot capacitor each time the high-side MOSFET is
switched on
L2 U2
ISL6239
Ci
As an example, suppose the high-side MOSFET has a total
LINE OF SYMMETRY
gate charge Q , of 25nC at V
= 5V, and a V of
g
GS
BOOT
200mV. The calculated bootstrap capacitance is 0.125µF; for a
comfortable margin, select a capacitor that is double the
calculated capacitance. In this example, 0.22µF will suffice.
Use an X7R or X5R ceramic capacitor.
Ci
L1 U1
PGND PLANE
L1
Co
PHASE PLANES
VOUT PLANES
VIN PLANE
Layout Considerations
As a general rule, power should be on the bottom layer of the
PCB and weak analog or logic signals are on the top layer of
the PCB. The ground-plane layer should be adjacent to the top
layer to provide shielding. The ground plane layer should have
an island located under the IC, the compensation components,
and the FSET components. The island should be connected to
the rest of the ground plane layer at one point.
FIGURE 30. SYMMETRIC LAYOUT GUIDE
VIN (Pin 17)
The VIN pin should be connected close to the drain of the high-
side MOSFET, using a low resistance and low inductance path.
VCC (Pin 4)
VIAS TO
GND
GND
GROUND
OUTPUT
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
PLANE
CAPACITORS
SCHOTTKY
DIODE
VOU
PVCC (Pin 18)
LOW-SIDE
PHASE
INDUCTOR
For best performance, place the decoupling capacitor very
close to the PVCC and respective PGND pin, preferably on the
same side of the PCB as the ISL62391, ISL62392, ISL62391C
and ISL62392C ICs.
NODE
NE
MOSFETS
HIGH-SIDE
MOSFETS
INPUT
CAPACITORS
VIN
VIN
FIGURE 29. TYPICAL POWER COMPONENT PLACEMENT
EN (Pins 11 and 24), and PGOOD (Pin 1)
These are logic signals that are referenced to the GND pin.
Treat as a typical logic signal.
Because there are two SMPS outputs and only one PGND pin,
the power train of both channels should be laid out
symmetrically. The line of bilateral symmetry should be drawn
through pins 4 and 18. This layout approach ensures that the
controller does not favor one channel over another during
critical switching decisions. Figure 29 illustrates one example
of how to achieve proper bilateral symmetry.
OCSET (Pins 10 and 25) and ISEN (Pins 9 and 26)
For DCR current sensing, the current-sense network,
consisting of R
and C , needs to be connected to the
OCSET
SEN
inductor pads for accurate measurement. Connect R
to
to
OCSET
the phase-node side pad of the inductor, and connect C
SEN
Signal Ground and Power Ground
the output side pad of the inductor. The ISEN resistor should
also be connected to the output pad of the inductor with a
separate trace. Connect the OCSET pin to the common node
The bottom of the ISL62391, ISL62392, ISL62391C and
ISL62392C TQFN package is the signal ground (GND)
terminal for analog and logic signals of the IC. Connect the
GND pad of the ISL62391, ISL62392, ISL62391C and
ISL62392C to the island of ground plane under the top layer
using several vias for a robust thermal and electrical
conduction path. Connect the input capacitors, the output
capacitors, and the source of the lower MOSFETs to the power
ground plane.
of node of R
and C .
SEN
OCSET
For resistive current sensing, connect R
from the
OCSET pin to the inductor side of the resistor pad. The ISEN
OCSET
resistor should be connected to the V
pad.
side of the resistor
OUT
In both current-sense configurations, the resistor and capacitor
sensing elements, with the exclusion of the current sense
power resistor, should be placed near the corresponding IC
pin. The trace connections to the inductor or sensing resistor
should be treated as Kelvin connections.
PGND (Pin 19)
This is the return path for the pull-down of the LGATE low-side
MOSFET gate driver. Ideally, PGND should be connected to
the source of the low-side MOSFET with a low-resistance, low-
inductance path.
FN6666 Rev 8.00
August 25, 2015
Page 19 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
FB (Pins 7 and 28), and VOUT (Pins 8 and 27)
BOOT (Pins 14 and 21), UGATE (Pins 13 and 22), and
PHASE (Pins 12 and 23)
3
The VOUT pin is used to generate the R synthetic ramp
voltage and for soft-discharge of the output voltage during
shutdown events. This signal should be routed as close to the
regulation point as possible. The input impedance of the FB pin
is high, so place the voltage programming and loop
compensation components close to the VOUT, FB, and GND
pins, keeping the high impedance trace short.
The signals going through these traces are both high dv/dt and
high di/dt, with high peak charging and discharging current.
Route the UGATE and PHASE pins in parallel with short and
wide traces. There should be no other weak signal traces in
proximity with these traces on any layer.
Copper Size for the Phase Node
FSET (Pins 2 and 6)
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across the
drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
This pin requires a quiet environment. The resistor R
and
should be placed directly adjacent to this pin.
FSET
capacitor C
FSET
Keep fast moving nodes away from this pin.
LGATE (Pins 15 and 20)
The signal going through this trace is both high dv/dt and high
di/dt, with high peak charging and discharging current. Route
this trace in parallel with the trace from the PGND pin. These
two traces should be short, wide, and away from other traces.
There should be no other weak signal traces in proximity with
these traces on any layer.
FN6666 Rev 8.00
August 25, 2015
Page 20 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
CHANGE
August 25, 2015
FN6666.8
Updated Ordering Information table on page 2.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing L28.4X4 to the latest revision.
-Revision 0 to Revision 1 changes - Added +/- 0.05 tolerances to each dimension in Top View and Bottom
View. Added 2 degrees to Bottom view pin 1 index area dimension
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2008-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6666 Rev 8.00
August 25, 2015
Page 21 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Package Outline Drawing
L28.4x4
28 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 6/15
A
4.00 ±0.05
2.50 ±0.05
PIN #1 INDEX AREA
CHAMFER
B
PIN 1
INDEX AREA
0.40 ±0.05
0.400 ±0.05 x 45° ±2°
22
28
21
1
0.40 ±0.05
15
7
0.10
2x
14
8
0.20 ±0.05
0.10 M C A B
0.4 x 6 = 2.40 REF
3.20 ±0.05
TOP VIEW
BOTTOM VIEW
SEE DETAIL X''
0.10 C
C
(3.20)
PACKAGE
OUTLINE
MAX. 0.80
SEATING PLANE
(28x 0.20)
0.00 - 0.05
0.08 C
0.20 REF
SIDE VIEW
(0.40)
0.20 REF
C
5
(0.40)
0 ~ 0.05
(28x 0.60)
(2.50)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Controlling dimensions are in mm.
Dimensions in ( ) are for reference only.
2. Unless otherwise specified, tolerance : Decimal ±0.05
Angular ±2°
3. Dimensioning and tolerancing conform to AMSE Y14.5M-1994
4. Bottom side Pin#1 ID is diepad chamfer as shown.
5. Tiebar shown (if present) is a non-functional feature.
.
FN6666 Rev 8.00
August 25, 2015
Page 22 of 22
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