ISL6312CRZ-T13_技术文档

ISL6312

®

Data Sheet

February 1, 2011

FN9289.6

Four-Phase Buck PWM Controller with

Integrated MOSFET Drivers for Intel VR10,

VR11, and AMD Applications

Features

• Integrated Multiphase Power Conversion

- 2- or 3-Phase Operation with Internal Drivers

- 4-Phase Operation with External PWM Driver Signal

• Precision Core Voltage Regulation

- Differential Remote Voltage Sensing

- ±0.5% System Accuracy Over-Temperature

- Adjustable Reference-Voltage Offset

• Optimal Transient Response

The ISL6312 four-phase PWM control IC provides a

precision voltage regulation system for advanced

microprocessors. The integration of power MOSFET drivers

into the controller IC marks a departure from the separate

PWM controller and driver configuration of previous

multiphase product families. By reducing the number of

external parts, this integration is optimized for a cost and

space saving power management solution.

- Active Pulse Positioning (APP) Modulation

- Adaptive Phase Alignment (APA)

• Fully Differential, Continuous DCR Current Sensing

- Accurate Load Line Programming

- Precision Channel Current Balancing

• User Selectable Adaptive Dead Time Scheme

- PHASE Detect or LGATE Detect for Application Flexibility

• Variable Gate Drive Bias: 5V to 12V

One outstanding feature of this controller IC is its

multi-processor compatibility, allowing it to work with both Intel

and AMD microprocessors. Included are programmable VID

codes for Intel VR10, VR11, as well as AMD DAC tables. A

unity gain, differential amplifier is provided for remote voltage

sensing, compensating for any potential difference between

remote and local grounds. The output voltage can also be

positively or negatively offset through the use of a single

external resistor.

• Multi-Processor Compatible

- Intel VR10 and VR11 Modes of Operation

- AMD Mode of Operation

• Microprocessor Voltage Identification Inputs

- 8-bit DAC

- Selectable between Intel’s Extended VR10, VR11, AMD

5-bit, and AMD 6-bit DAC Tables

- Dynamic VID Technology

The ISL6312 also includes advanced control loop features

for optimal transient response to load apply and removal.

One of these features is highly accurate, fully differential,

continuous DCR current sensing for load line programming

and channel current balance. Active Pulse Positioning (APP)

modulation is another unique feature, allowing for quicker

initial response to high di/dt load transients.

• Overcurrent Protection

• Multi-Tiered Overvoltage Protection

• Digital Soft-Start

This controller also allows the user the flexibility to choose

between PHASE detect or LGATE detect adaptive dead time

schemes. This ability allows the ISL6312 to be used in a

multitude of applications where either scheme is required.

• Selectable Operation Frequency up to 1.5MHz Per Phase

• Pb-Free (RoHS Compliant)

Ordering Information

PART NUMBER

(Note 1)

PART

MARKING

TEMP.

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

Protection features of this controller IC include a set of

sophisticated overvoltage, undervoltage, and overcurrent

protection. Furthermore, the ISL6312 includes protection

against an open circuit on the remote sensing inputs.

Combined, these features provide advanced protection for the

microprocessor and power system.

ISL6312CRZ

ISL6312 CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7

ISL6312CRZ-T

(Note 2)

ISL6312CRZ-TK ISL6312 CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7

(Note 2)

ISL6312IRZ

ISL6312 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7

ISL6312IRZ-T

(Note 2)

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb-

free material sets, molding compounds/die attach materials, and

100% matte tin plate plus anneal (e3 termination finish, which is

RoHS compliant and compatible with both SnPb and Pb-free

soldering operations). Intersil Pb-free products are MSL classified at

Pb-free peak reflow temperatures that meet or exceed the Pb-free

requirements of IPC/JEDEC J STD-020.

2. Please refer to TB347 for details on reel specifications.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6312

Pinout

ISL6312

(48 LD QFN)

TOP VIEW

48 47 46 45 44 43 42 41 40 39 38 37

VID4

VID3

EN

1

2

36

35

34

33

32

31

30

29

28

27

26

25

ISEN1+

ISEN1-

VID2

3

VID1

PHASE1

UGATE1

BOOT1

LGATE1

PVCC1_2

LGATE2

BOOT2

UGATE2

PHASE2

4

VID0

5

VRSEL

DRSEL

OVPSEL

SS

49

GND

6

7

8

9

VCC

10

11

12

REF

OFS

13 14 15 16 17 18 19 20 21 22 23 24

ISL6312 Integrated Driver Block Diagram

PVCC

BOOT

DRSEL

UGATE

PHASE

20kΩ

PWM

SHOOT-

GATE

THROUGH

CONTROL

LOGIC

PROTECTION

SOFT-START

AND

10kΩ

FAULT LOGIC

LGATE

FN9289.6

February 1, 2011

2

ISL6312

Block Diagram

EN

SS

PGOOD

OPEN SENSE

LINE PREVENTION

0.85V

VSEN

RGND

x1

VCC

POWER-ON

RESET

PVCC1_2

VDIFF

SOFT-START

AND

UNDERVOLTAGE

DETECTION

LOGIC

FAULT LOGIC

BOOT1

UGATE1

MOSFET

DRIVER

OVERVOLTAGE

DETECTION

LOGIC

PHASE1

LGATE1

0.2V

LOAD APPLY

TRANSIENT

OVPSEL

ENHANCEMENT

DRSEL

FS

CLOCK AND

MODULATOR

WAVEFORM

GENERATOR

MODE/DAC

SELECT

VRSEL

VID7

BOOT2

UGATE2

MOSFET

DRIVER

PWM1

PWM2

PWM3

PWM4

PHASE2

LGATE2

∑

VID6

VID5

VID4

OC

DYNAMIC

VID

D/A

∑

VID3

VID2

VID1

VID0

I_TRIP

PH4 POR/

DETECT

EN_PH4

PVCC3

CHANNEL

DETECT

REF

FB

E/A

BOOT3

COMP

OFS

UGATE3

MOSFET

DRIVER

OFFSET

PHASE3

LGATE3

I_AVG

CHANNEL

CURRENT

BALANCE

1

N

I_AVG

IDROOP

∑

PWM4

SIGNAL

LOGIC

PWM4

CH1

CURRENT

SENSE

CH2

CURRENT

SENSE

CH3

CURRENT

SENSE

CH4

CURRENT

SENSE

GND

ISEN1- ISEN1+ ISEN2- ISEN2+ ISEN3- ISEN3+ ISEN4- ISEN4+

FN9289.6

February 1, 2011

3

ISL6312

Typical Application - ISL6312 (4-Phase)

+12V

FB IDROOP

COMP

VDIFF

VSEN

RGND

BOOT1

UGATE1

+5V

PHASE1

LGATE1

VCC

OFS

ISEN1-

ISEN1+

FS

+12V

REF

PVCC1_2

BOOT2

SS

UGATE2

PHASE2

LGATE2

LOAD

OVPSEL

ISEN2-

ISEN2+

ISL6312

+12V

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

PVCC3

BOOT3

UGATE3

PHASE3

LGATE3

VRSEL

PGOOD

+12V

ISEN3-

ISEN3+

+12V

EN

BOOT

VCC

UGATE

EN_PH4

PWM4

PVCC

PHASE

DRSEL

ISL6612

LGATE

GND

PWM

GND

ISEN4-

ISEN4+

FN9289.6

February 1, 2011

4

ISL6312

Typical Application - ISL6312 with NTC Thermal Compensation (4-Phase)

+12V

FB IDROOP

COMP

VDIFF

VSEN

RGND

PLACE IN

CLOSE

PROXIMITY

BOOT1

NTC

UGATE1

PHASE1

+5V

VCC

OFS

LGATE1

ISEN1-

ISEN1+

FS

+12V

REF

PVCC1_2

BOOT2

SS

UGATE2

PHASE2

LGATE2

LOAD

OVPSEL

ISEN2-

ISEN2+

ISL6312

+12V

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

PVCC3

BOOT3

UGATE3

PHASE3

LGATE3

VRSEL

PGOOD

+12V

ISEN3-

ISEN3+

+12V

EN

BOOT

VCC UGATE

EN_PH4

PWM4

PVCC

PHASE

DRSEL

GND

ISL6612

LGATE

PWM

GND

ISEN4-

ISEN4+

FN9289.6

February 1, 2011

5

ISL6312

Absolute Maximum Ratings

Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

Supply Voltage, PVCC. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +15V

Thermal Resistance

θ

(°C/W)

32

θ

(°C/W)

3.5

JA

JC

QFN Package (Notes 3, 4) . . . . . . . . . .

BOOT Voltage, V

. . . . . . . . . . . . . .GND - 0.3V to GND + 36V

BOOT

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

BOOT to PHASE Voltage, V

BOOT-PHASE

. . . . . . -0.3V to 15V (DC)

-0.3V to 16V (<10ns, 10µJ)

PHASE Voltage, V

. . . . . . . GND - 0.3V to 15V (PVCC = 12)

PHASE

GND - 8V (<400ns, 20µJ) to 24V (<200ns, V

= 12V)

+ 0.3V

BOOT - PHASE

UGATE Voltage, V

. . . . . . . . V

- 0.3V to V

UGATE

PHASE

BOOT

Recommended Operating Conditions

V

- 3.5V (<100ns Pulse Width, 2µJ) to V

PHASE

LGATE Voltage, V

VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5%

Ambient Temperature (ISL6312CRZ) . . . . . . . . . . . . . 0°C to +70°C

Ambient Temperature (ISL6312IRZ) . . . . . . . . . . . . .-40°C to +85°C

. . . . . . . . . . . GND - 0.3V to PVCC + 0.3V

LGATE

GND - 5V (<100ns Pulse Width, 2µJ) to PVCC + 0.3V

Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

3. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified.

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 6)

TYP

(Note 6) UNITS

BIAS SUPPLIES

Input Bias Supply Current

I

; EN = high

15

2

20

25

6

mA

V

VCC

Gate Drive Bias Current - PVCC1_2 Pin

Gate Drive Bias Current - PVCC3 Pin

VCC POR (Power-On Reset) Threshold

; EN = high

4.3

PVCC1_2

; EN = high

PVCC3

1

2.1

3

VCC rising

VCC falling

PVCC rising

PVCC falling

4.25

3.75

4.25

3.60

4.38

3.88

4.38

3.88

4.50

4.00

4.50

4.00

V

PVCC POR (Power-On Reset) Threshold

V

PWM MODULATOR

Oscillator Frequency Accuracy, f

SW

R

= 100kΩ (± 0.1%)

225

0.08

-

250

-

275

1.0

-

kHz

MHz

V

T

Adjustment Range of Switching Frequency

(Note 5)

Oscillator Ramp Amplitude, V

CONTROL THRESHOLDS

EN Rising Threshold

1.50

PP

-

0.85

110

-

V

mV

V

EN Hysteresis

EN_PH4 Rising Threshold

EN_PH4 Falling Threshold

COMP Shutdown Threshold

REFERENCE AND DAC

1.160

1.00

0.1

1.210

1.06

0.2

1.250

1.10

0.3

V

COMP falling

V

System Accuracy (1.000V - 1.600V)

System Accuracy (0.600V - 1.000V)

System Accuracy (0.375V - 0.600V)

DAC Input Low Voltage (VR10, VR11)

DAC Input High Voltage (VR10, VR11)

-0.5

-1.0

-2.0

-

0.5

1.0

2.0

0.4

-

%

V

0.8

V

FN9289.6

February 1, 2011

6

ISL6312

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued)

MIN

MAX

PARAMETER

DAC Input Low Voltage (AMD)

DAC Input High Voltage (AMD)

PIN-ADJUSTABLE OFFSET

OFS Sink Current Accuracy (Negative Offset)

OFS Source Current Accuracy (Positive Offset)

ERROR AMPLIFIER

TEST CONDITIONS

(Note 6)

TYP

(Note 6) UNITS

-

0.6

-

V

1.0

R

= 10kΩ from OFS to GND

= 30kΩ from OFS to VCC

37.0

50.5

40.0

53.5

43.0

56.5

μA

OFS

DC Gain

R

C

= 10k to ground, (Note 5)

-

96

20

-

dB

MHz

V/μs

V

L

Gain-Bandwidth Product

Slew Rate

= 100pF, R = 10k to ground, (Note 5)

-

L

CL = 100pF, Load = ±400mA, (Note 5)

Load = 1mA

-

3.90

-

8

Maximum Output Voltage

Minimum Output Voltage

SOFT-START RAMP

4.20

1.30

-

Load = -1mA

1.5

V

Soft-Start Ramp Rate

VR10/VR11, R = 100kΩ

-

1.563

2.063

-

mV/µs

S

AMD

Adjustment Range of Soft-Start Ramp Rate (Note 5)

PWM OUTPUT

0.625

6.25

PWM Output Voltage LOW Threshold

PWM Output Voltage HIGH Threshold

CURRENT SENSING

Iload = ±500µA

-

0.5

-

V

4.5

Current Sense Resistance, R

Sensed Current Tolerance

T = +25°C

297

76

300

80

303

84

Ω

ISEN

ISEN1+ = ISEN2+ = ISEN3+ = ISEN4+ = 80μA

μA

OVERCURRENT PROTECTION

Overcurrent Trip Level - Average Channel

Normal operation

110

143

125

163

177

238

140

183

μA

Dynamic VID change

Normal operation

Overcurrent Trip Level - Individual Channel

150

204

Dynamic VID change (Note NOTES:)

209.4

266.6

PROTECTION

Undervoltage Threshold

Undervoltage Hysteresis

Overvoltage Threshold During Soft-Start

VSEN falling

VSEN rising

VR10/VR11

AMD

55

-

60

10

65

-

%VID

1.24

2.13

1.28

2.20

1.32

2.27

V

Overvoltage Threshold (Default)

VR10/VR11, OVPSEL tied to ground, VSEN rising VDAC+ VDAC + VDAC+

150mV 175mV 200mV

AMD, OVPSEL tied to ground, VSEN rising

OVPSEL tied to +5V, VSEN rising

VSEN falling

VDAC+ VDAC + VDAC+

225mV 250mV 275mV

V

Overvoltage Threshold (Alternate)

VDAC+ VDAC + VDAC+

325mV

350mV

375mV

Overvoltage Hysteresis

SWITCHING TIME (Note 5)

UGATE Rise Time

-

100

-

mV

t

V

= 12V, 3nF load, 10% to 90%

-

26

-

ns

RUGATE; PVCC

FN9289.6

February 1, 2011

7

ISL6312

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued)

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 6)

TYP

18

(Note 6) UNITS

LGATE Rise Time

UGATE Fall Time

LGATE Fall Time

t

V

= 12V, 3nF load, 10% to 90%

= 12V, 3nF load, 90% to 10%

-

ns

RLGATE; PVCC

V

18

FUGATE; PVCC

V

12

FLGATE; PVCC

UGATE Turn-On Non-Overlap

LGATE Turn-On Non-Overlap

GATE DRIVE RESISTANCE (Note 5)

Upper Drive Source Resistance

Upper Drive Sink Resistance

Lower Drive Source Resistance

Lower Drive Sink Resistance

OVER TEMPERATURE SHUTDOWN (Note 5)

Thermal Shutdown Setpoint

Thermal Recovery Setpoint

NOTES:

; V

= 12V, 3nF load, adaptive

10

PDHUGATE PVCC

; V

10

PDHLGATE PVCC

V

= 12V, 15mA source current

1.25

0.9

2.0

3.0

Ω

PVCC

= 12V, 15mA sink current

= 12V, 15mA source current

= 12V, 15mA sink current

1.65

1.25

0.80

0.85

0.60

2.2

1.35

-

160

100

-

°C

5. Limits established by characterization and are not production tested.

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

Timing Diagram

t

PDHUGATE

t

RUGATE

FUGATE

UGATE

LGATE

t

FLGATE

RLGATE

t

PDHLGATE

FN9289.6

February 1, 2011

8

ISL6312

FB and COMP

Functional Pin Descriptions

These pins are the internal error amplifier inverting input and

output respectively. FB, VDIFF, and COMP are tied together

through external R-C networks to compensate the regulator.

VCC

VCC is the bias supply for the ICs small-signal circuitry.

Connect this pin to a +5V supply and decouple using a

quality 0.1µF ceramic capacitor.

IDROOP

The IDROOP pin is the average channel-current sense

output. Connecting this pin through a tuned parallel R-C

network to FB allows the converter to incorporate output

voltage droop proportional to the output current. If voltage

droop is not desired leave this pin unconnected.

PVCC1_2 and PVCC3

These pins are the power supply pins for the corresponding

channel MOSFET drive, and can be connected to any

voltage from +5V to +12V depending on the desired

MOSFET gate-drive level. Decouple these pins with a quality

1.0µF ceramic capacitor.

REF

The REF input pin is the positive input of the error amplifier. It

is internally connected to the DAC output through a 1kΩ

resistor. A capacitor is used between the REF pin and ground

to smooth the voltage transition during Dynamic VID

operations.

Leaving PVCC3 unconnected or grounded programs the

controller for 2-phase operation.

GND

GND is the bias and reference ground for the IC.

OFS

EN

The OFS pin provides a means to program a DC current for

generating an offset voltage across the resistor between FB

and VDIFF. The offset current is generated via an external

resistor and precision internal voltage references. The polarity

of the offset is selected by connecting the resistor to GND or

VCC. For no offset, the OFS pin should be left unconnected.

This pin is a threshold-sensitive (approximately 0.85V) enable

input for the controller. Held low, this pin disables controller

operation. Pulled high, the pin enables the controller for

operation.

FS

A resistor, placed from FS to ground, sets the switching

frequency of the controller.

ISEN1-, ISEN1+, ISEN2-, ISEN2+, ISEN3-, ISEN3+,

ISEN4-, and ISEN4+

VID0, VID1, VID2, VID3, VID4, VID5, VID6, and VID7

These pins are used for differentially sensing the

corresponding channel output currents. The sensed currents

are used for channel balancing, protection, and load line

regulation.

These are the inputs for the internal DAC that provides the

reference voltage for output regulation. These pins respond to

TTL logic thresholds. These pins are internally pulled high, to

approximately 1.2V, by 40µA internal current sources for Intel

modes of operation, and pulled low by 20µA internal current

sources for AMD modes of operation. The internal pull-up

current decreases to 0 as the VID voltage approaches the

internal pull-up voltage. All VID pins are compatible with

external pull-up voltages not exceeding the IC’s bias voltage

(VCC).

Connect ISEN1-, ISEN2-, ISEN3-, and ISEN4- to the node

between the RC sense elements surrounding the inductor of

their respective channel. Tie the ISEN+ pins to the VCORE

side of their corresponding channel’s sense capacitor.

UGATE1, UGATE2, and UGATE3

Connect these pins to the corresponding upper MOSFET

gates. These pins are used to control the upper MOSFETs

and are monitored for shoot-through prevention purposes.

VRSEL

The state of this pin selects which of the available DAC tables

will be used to decode the VID inputs and puts the controller

into the corresponding mode of operation. Refer to Table 1 for

available options and details of implementation.

BOOT1, BOOT2, and BOOT3

These pins provide the bias voltage for the corresponding

upper MOSFET drives. Connect these pins to appropriately-

chosen external bootstrap capacitors. Internal bootstrap

diodes connected to the PVCC pins provide the necessary

bootstrap charge.

VSEN and RGND

VSEN and RGND are inputs to the precision differential

remote-sense amplifier and should be connected to the sense

pins of the remote load.

VDIFF

VDIFF is the output of the differential remote-sense amplifier.

The voltage on this pin is equal to the difference between

VSEN and RGND.

FN9289.6

February 1, 2011

9

ISL6312

Operation

PHASE1, PHASE2, and PHASE3

Connect these pins to the sources of the corresponding

upper MOSFETs. These pins are the return path for the

upper MOSFET drives.

Multiphase Power Conversion

Microprocessor load current profiles have changed to the

point that using single-phase regulators is no longer a viable

solution. Designing a regulator that is cost-effective,

LGATE1, LGATE2, and LGATE3

thermally sound, and efficient has become a challenge that

only multiphase converters can accomplish. The ISL6322

controller helps simplify implementation by integrating vital

functions and requiring minimal external components. The

“Block Diagram” on page 3 provides a top level view of

multiphase power conversion using the ISL6322 controller.

These pins are used to control the lower MOSFETs. Connect

these pins to the corresponding lower MOSFETs’ gates.

PWM4

Pulse-width modulation output. Connect this pin to the PWM

input pin of an Intersil driver IC if 4-phase operation is

desired.

EN_PH4

This pin has two functions. First, a resistor divider connected

to this pin will provide a POR power-up synch between the

on-chip and external driver. The resistor divider should be

designed so that when the POR-trip point of the external

driver is reached the voltage on this pin should be 1.21V.

IL1 + IL2 + IL3, 7A/DIV

IL3, 7A/DIV

PWM3, 5V/DIV

IL2, 7A/DIV

The second function of this pin is disabling PWM4 for

3-phase operation. This can be accomplished by connecting

this pin to a +5V supply.

PWM2, 5V/DIV

IL1, 7A/DIV

SS

PWM1, 5V/DIV

1µs/DIV

A resistor, placed from SS to ground, will set the soft-start

ramp slope for the Intel DAC modes of operation. Refer to

Equations 18 and 19 for proper resistor calculation.

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS

FOR 3-PHASE CONVERTER

For AMD modes of operation, the soft-start ramp frequency

is preset, so this pin can be left unconnected.

Interleaving

OVPSEL

The switching of each channel in a multiphase converter is

timed to be symmetrically out of phase with each of the other

channels. In a 3-phase converter, each channel switches 1/3

cycle after the previous channel and 1/3 cycle before the

following channel. As a result, the three-phase converter has a

combined ripple frequency three times greater than the ripple

frequency of any one phase. In addition, the peak-to-peak

amplitude of the combined inductor currents is reduced in

proportion to the number of phases (Equations 1 and 2).

Increased ripple frequency and lower ripple amplitude mean

that the designer can use less per-channel inductance and

lower total output capacitance for any performance

specification.

This pin selects the OVP trip point during normal operation.

Leaving it unconnected or tieing it to ground selects the

default setting of VDAC+175mV for Intel Modes of operation

and VDAC+250mV for AMD modes of operation. Connecting

this pin to VCC will select an OVP trip setting of VID+350mV

for all modes of operation.

DRSEL

This pin selects the adaptive dead time scheme the internal

drivers will use. If driving MOSFETs, tie this pin to ground to

select the PHASE detect scheme or to a +5V supply through

a 50kΩ resistor to select the LGATE detect scheme.

PGOOD

Figure 1 illustrates the multiplicative effect on output ripple

frequency. The three channel currents (IL1, IL2, and IL3)

combine to form the AC ripple current and the DC load

current. The ripple component has three times the ripple

frequency of each individual channel current. Each PWM

pulse is terminated 1/3 of a cycle after the PWM pulse of the

previous phase. The peak-to-peak current for each phase is

about 7A, and the DC components of the inductor currents

combine to feed the load.

During normal operation PGOOD indicates whether the

output voltage is within specified overvoltage and

undervoltage limits. If the output voltage exceeds these limits

or a reset event occurs (such as an overcurrent event),

PGOOD is pulled low. PGOOD is always low prior to the end

of soft-start.

FN9289.6

February 1, 2011

10

ISL6312

To understand the reduction of ripple current amplitude in the

multiphase circuit, examine the equation representing an

individual channel peak-to-peak inductor current.

Active Pulse Positioning (APP) Modulated PWM

Operation

The ISL6312 uses a proprietary Active Pulse Positioning

(APP) modulation scheme to control the internal PWM

signals that command each channel’s driver to turn their

upper and lower MOSFETs on and off. The time interval in

which a PWM signal can occur is generated by an internal

clock, whose cycle time is the inverse of the switching

frequency set by the resistor between the FS pin and

ground. The advantage of Intersil’s proprietary Active Pulse

Positioning (APP) modulator is that the PWM signal has the

ability to turn on at any point during this PWM time interval,

and turn off immediately after the PWM signal has

(V – V

) ⋅ V

OUT

IN

OUT

(EQ. 1)

I

= ---------------------------------------------------------

(P – P)

L ⋅ f ⋅ V

S

IN

In Equation 1, V and V

IN

are the input and output

OUT

voltages respectively, L is the single-channel inductor value,

and f is the switching frequency.

S

The output capacitors conduct the ripple component of the

inductor current. In the case of multiphase converters, the

capacitor current is the sum of the ripple currents from each

of the individual channels. Compare Equation 1 to the

expression for the peak-to-peak current after the summation

of N symmetrically phase-shifted inductor currents in

Equation 2. Peak-to-peak ripple current decreases by an

amount proportional to the number of channels. Output

voltage ripple is a function of capacitance, capacitor

equivalent series resistance (ESR), and inductor ripple

current. Reducing the inductor ripple current allows the

designer to use fewer or less costly output capacitors.

transitioned high. This is important because is allows the

controller to quickly respond to output voltage drops

associated with current load spikes, while avoiding the ring

back affects associated with other modulation schemes.

The PWM output state is driven by the position of the error

amplifier output signal, V

, minus the current correction

COMP

signal relative to the proprietary modulator ramp waveform

as illustrated in Figure 3. At the beginning of each PWM time

(V – N ⋅ V

) ⋅ V

OUT

IN

OUT

(EQ. 2)

I

= -------------------------------------------------------------------

C(P – P)

interval, this modified V

signal is compared to the

L ⋅ f ⋅ V

COMP

S

IN

internal modulator waveform. As long as the modified

voltage is lower then the modulator waveform

Another benefit of interleaving is to reduce input ripple

current. Input capacitance is determined in part by the

maximum input ripple current. Multiphase topologies can

improve overall system cost and size by lowering input ripple

current and allowing the designer to reduce the cost of input

capacitance. The example in Figure 2 illustrates input

currents from a three-phase converter combining to reduce

the total input ripple current.

V

COMP

voltage, the PWM signal is commanded low. The internal

MOSFET driver detects the low state of the PWM signal and

turns off the upper MOSFET and turns on the lower

synchronous MOSFET. When the modified V

voltage

COMP

crosses the modulator ramp, the PWM output transitions

high, turning off the synchronous MOSFET and turning on

the upper MOSFET. The PWM signal will remain high until

The converter depicted in Figure 2 delivers 1.5V to a 36A load

from a 12V input. The RMS input capacitor current is 5.9A.

Compare this to a single-phase converter also stepping down

12V to 1.5V at 36A. The single-phase converter has 11.9A

RMS input capacitor current. The single-phase converter

must use an input capacitor bank with twice the RMS current

capacity as the equivalent three-phase converter.

the modified V

voltage crosses the modulator ramp

COMP

again. When this occurs the PWM signal will transition low

again.

During each PWM time interval the PWM signal can only

transition high once. Once PWM transitions high it can not

transition high again until the beginning of the next PWM

time interval. This prevents the occurrence of double PWM

pulses occurring during a single period.

INPUT-CAPACITOR CURRENT, 10A/DIV

To further improve the transient response, ISL6312 also

implements Intersil’s proprietary Adaptive Phase Alignment

(APA) technique, which turns on all phases together under

transient events with large step current. With both APP and

APA control, ISL6312 can achieve excellent transient

performance and reduce the demand on the output

capacitors.

CHANNEL 3

INPUT CURRENT

10A/DIV

CHANNEL 2

INPUT CURRENT

10A/DIV

Channel-Current Balance

One important benefit of multiphase operation is the thermal

advantage gained by distributing the dissipated heat over

multiple devices and greater area. By doing this the designer

avoids the complexity of driving parallel MOSFETs and the

expense of using expensive heat sinks and exotic magnetic

materials.

CHANNEL 1

INPUT CURRENT

10A/DIV

1µs/DIV

FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-

CAPACITOR RMS CURRENT FOR 3-PHASE

CONVERTER

FN9289.6

February 1, 2011

11

ISL6312

In order to realize the thermal advantage, it is important that

each channel in a multiphase converter be controlled to

carry equal amounts of current at any load level. To achieve

this, the currents through each channel must be sampled

Continuous Current Sampling

In order to realize proper current-balance, the currents in

each channel are sensed continuously every switching

cycle. During this time the current-sense amplifier uses the

ISEN inputs to reproduce a signal proportional to the

every switching cycle. The sampled currents, I , from each

n

active channel are summed together and divided by the

number of active channels. The resulting cycle average

inductor current, I . This sensed current, I

scaled version of the inductor current.

, is simply a

SEN

L

current, I

, provides a measure of the total load-current

AVG

The ISL6312 supports inductor DCR current sensing to

continuously sense each channel’s current for channel-

current balance. The internal circuitry, shown in Figure 5

represents channel n of an N-channel converter. This

circuitry is repeated for each channel in the converter, but

may not be active depending on how many channels are

operating.

demand on the converter during each switching cycle.

Channel-current balance is achieved by comparing the

sampled current of each channel to the cycle average

current, and making the proper adjustment to each channel

pulse width based on the error. Intersil’s patented current-

balance method is illustrated in Figure 3, with error

correction for Channel 1 represented. In the figure, the cycle

average current, I

sample, I , to create an error signal I

1

, is compared with the Channel 1

AVG

V

IN

I

L

.

ER

UGATE(n)

LGATE(n)

L

DCR

V

OUT

MOSFET

DRIVER

+

PWM1

V

COMP

INDUCTOR

TO GATE

CONTROL

LOGIC

+

-

C

OUT

-

MODULATOR

RAMP

V (s)

L

-

WAVEFORM

-

V (s)

C

FILTER f(s)

R

C

1

I

4

I

ER

+

I

AVG

Σ

R

÷ N

2*

3

2

-

ISL6312 INTERNAL CIRCUIT

I

1

n

NOTE: Channel 3 and 4 are optional.

SAMPLE

FIGURE 3. CHANNEL-1 PWM FUNCTION AND CURRENT-

BALANCE ADJUSTMENT

+

ISEN-(n)

ISEN+(n)

-

V (s)

C

-

R

The filtered error signal modifies the pulse width

ISEN

commanded by V

to correct any unbalance and force

COMP

toward zero. The same method for error signal

*R is OPTIONAL

2

I

SEN

I

ER

correction is applied to each active channel.

FIGURE 5. INDUCTOR DCR CURRENT SENSING

CONFIGURATION

Inductor windings have a characteristic distributed

resistance or DCR (Direct Current Resistance). For

simplicity, the inductor DCR is considered as a separate

lumped quantity, as shown in Figure 5. The channel current

PWM

SWITCHING PERIOD

I , flowing through the inductor, passes through the DCR.

L

I

Equation 3 shows the s-domain equivalent voltage, V ,

L

across the inductor.

(EQ. 3)

V (s) = I ⋅ (s ⋅ L + DCR)

L

I

SEN

A simple R-C network across the inductor (R and C)

1

extracts the DCR voltage, as shown in Figure 5. The voltage

across the sense capacitor, V , can be shown to be

proportional to the channel current I , shown in Equation 4.

L

C

TIME

FIGURE 4. CONTINUOUS CURRENT SAMPLING

FN9289.6

February 1, 2011

12

ISL6312

s ⋅ L

⎛

⎝

⎞

(EQ. 4)

-------------

+ 1

TABLE 1. ISL6312 DAC SELECT TABLE

⎠

DCR

-------------------------------------

V

(s) =

⋅ DCR ⋅ I

C

L

(s ⋅ R ⋅ C + 1)

DAC VERSION

VRSEL PIN

VRSEL = GND

VRSEL = VCC/2

VRSEL = VCC

VID7 PIN

1

VR10(Extended)

VR11

-

In some cases it may be necessary to use a resistor divider

R-C network to sense the current through the inductor. This

can be accomplished by placing a second resistor, R ,

across the sense capacitor. In these cases the voltage

across the sense capacitor, V , becomes proportional to the

-

2

AMD 5-Bit

AMD 6-Bit

LOW

HIGH

C

channel current I , and the resistor divider ratio, K.

L

TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION

CODES

s ⋅ L

⎛

⎝

⎞

(EQ. 5)

(EQ. 6)

-------------

+ 1

⎠

DCR

-------------------------------------------------------

V

(s) =

⋅ K ⋅ DCR ⋅ I

VID4 VID3 VID2 VID1 VID0 VID5 VID6

VDAC

C

L

(R ⋅ R )

⎛

⎜

⎝

⎞

1

2

-----------------------

s ⋅

⋅ C + 1

⎟

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1.50000

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

R

+ R

2

⎠

1

R

2

--------------------

K =

R

+ R

1

2

If the R-C network components are selected such that the

RC time constant matches the inductor L/DCR time

constant, then V is equal to the voltage drop across the

C

DCR multiplied by the ratio of the resistor divider, K. If a

resistor divider is not being used, the value for K is 1.

The capacitor voltage V , is then replicated across the

C

sense resistor R

. The current through R

is

ISEN

proportional to the inductor current. Equation 7 shows that

the proportion between the channel current and the sensed

) is driven by the value of the sense resistor,

the resistor divider ratio, and the DCR of the inductor.

current (I

SEN

DCR

-----------------

I

= K ⋅ I

⋅

(EQ. 7)

SEN

L

R

ISEN

Output Voltage Setting

The ISL6312 uses a digital to analog converter (DAC) to

generate a reference voltage based on the logic signals at

the VID pins. The DAC decodes the logic signals into one of

the discrete voltages shown in Tables 2, 3, 4 and 5. In Intel

modes of operation, each VID pin is pulled up to an internal

1.2V voltage by a weak current source (40µA), which

decreases to 0A as the voltage at the VID pin varies from 0

to the internal 1.2V pull-up voltage. In AMD modes of

operation the VID pins are pulled low by a weak 20µA

current source. External pull-up resistors or active-high

output stages can augment the pull-up current sources, up to

a voltage of 5V.

The ISL6312 accommodates four different DAC ranges: Intel

VR10 (Extended), Intel VR11, AMD K8/K9 5-bit, and AMD

6-bit. The state of the VRSEL and VID7 pins decide which

DAC version is active. Refer to Table 1 for a description of

how to select the desired DAC version. For VR11 setting, tie

the VRSEL pin to the midpoint of a 10kΩ (or other suitable

value) resistor divider connected from VCC to GND.

FN9289.6

February 1, 2011

13

ISL6312

TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION

CODES (Continued)

TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION

CODES (Continued)

VID4 VID3 VID2 VID1 VID0 VID5 VID6

VDAC

VID4 VID3 VID2 VID1 VID0 VID5 VID6

VDAC

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

1.21250

1.20625

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

1.10000

1.09375

OFF

1.08750

1.08125

1.07500

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

FN9289.6

February 1, 2011

14

ISL6312

TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION

CODES (Continued)

TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

VID4 VID3 VID2 VID1 VID0 VID5 VID6

VDAC

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

1.26250

1.25625

1.25000

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.93750

0.93125

0.92500

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

OFF

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1.50000

FN9289.6

February 1, 2011

15

ISL6312

TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.24375

1.23750

1.23125

1.22500

1.21875

1.21250

1.20625

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

1.10000

1.09375

1.08750

1.08125

1.07500

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

0.93750

0.93125

0.92500

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

0.82500

0.81875

0.81250

0.80625

0.80000

0.79375

0.78750

0.78125

0.77500

0.76875

0.76250

0.75625

0.75000

FN9289.6

February 1, 2011

16

ISL6312

TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.74375

0.73750

0.73125

0.72500

0.71875

0.71250

0.70625

0.70000

0.69375

0.68750

0.68125

0.67500

0.66875

0.66250

0.65625

0.65000

0.64375

0.63750

0.63125

0.62500

0.61875

0.61250

0.60625

0.60000

0.59375

0.58750

0.58125

0.57500

0.56875

0.56250

0.55625

0.55000

0.54375

0.53750

0.53125

0.52500

0.51875

0.51250

0.50625

0.50000

1

0

1

OFF

TABLE 4. AMD 5-BIT VOLTAGE IDENTIFICATION CODES

VID4

1

0

VID3

1

0

1

0

VID2

1

0

1

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VDAC

Off

0.800

0.825

0.850

0.875

0.900

0.925

0.950

0.975

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

FN9289.6

February 1, 2011

17

ISL6312

TABLE 5. AMD 6-BIT VOLTAGE IDENTIFICATION CODES

(Continued)

VID5

0

1

VID4

0

1

0

VID3

0

1

0

1

0

VID2

0

1

0

1

0

1

0

1

0

1

VID1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VDAC

1.5500

1.5250

1.5000

1.4750

1.4500

1.4250

1.4000

1.3750

1.3500

1.3250

1.3000

1.2750

1.2500

1.2250

1.2000

1.1750

1.1500

1.1250

1.1000

1.0750

1.0500

1.0250

1.0000

0.9750

0.9500

0.9250

0.9000

0.8750

0.8500

0.8250

0.8000

0.7750

0.7625

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

VID5

1

VID4

0

VID3

0

VID2

1

VID1

1

VID0

1

VDAC

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Voltage Regulation

The integrating compensation network shown in Figure 6

insures that the steady-state error in the output voltage is

limited only to the error in the reference voltage (output of

the DAC) and offset errors in the OFS current source,

remote-sense and error amplifiers. Intersil specifies the

guaranteed tolerance of the ISL6312 to include the

combined tolerances of each of these elements.

The output of the error amplifier, V

, is compared to the

COMP

triangle waveform to generate the PWM signals. The PWM

signals control the timing of the Internal MOSFET drivers

and regulate the converter output so that the voltage at FB is

equal to the voltage at REF. This will regulate the output

voltage to be equal to Equation 8. The internal and external

circuitry that controls voltage regulation is illustrated in

Figure 6.

FN9289.6

February 1, 2011

18

ISL6312

negative spike can be sustained without crossing the lower

V

= V

– V

OFS DROOP

(EQ. 8)

OUT

REF

limit. By adding a well controlled output impedance, the

output voltage under load can effectively be level shifted

down so that a larger positive spike can be sustained without

crossing the upper specification limit.

The ISL6312 incorporates an internal differential

remote-sense amplifier in the feedback path. The amplifier

removes the voltage error encountered when measuring the

output voltage relative to the controller ground reference

point resulting in a more accurate means of sensing output

voltage. Connect the microprocessor sense pins to the

non-inverting input, VSEN, and inverting input, RGND, of the

As shown in Figure 6, a current proportional to the average

current of all active channels, I

, flows from FB through a

AVG

load-line regulation resistor R . The resulting voltage drop

FB

across R is proportional to the output current, effectively

FB

creating an output voltage droop with a steady-state value

remote-sense amplifier. The remote-sense output, V

, is

DIFF

connected to the inverting input of the error amplifier through

an external resistor.

defined as:

V

= I

⋅ R

AVG FB

(EQ. 9)

DROOP

EXTERNAL CIRCUIT

COMP

ISL6312 INTERNAL CIRCUIT

The regulated output voltage is reduced by the droop voltage

V

. The output voltage as a function of load current is

DROOP

derived by combining Equations 7, 8, and 9.

VID DAC

C

I

⎛

⎜

⎝

⎞

⎟

DCR

------------- -----------------

OUT

N

REF

V

= V

– V

–

⋅

⋅ R

FB

(EQ. 10)

is the

OUT

REF

OFS

R

ISEN

⎠

1k

R

C

In Equation 10, V

programmed offset voltage, I

of the converter, R

ISEN

is the reference voltage, V

OFS

REF

+

ERROR

AMPLIFIER

is the total output current

OUT

-

V

FB

COMP

is the internal sense resistor

connected to the ISEN+ pin, R is the feedback resistor, N

I

FB

OFS

is the active channel number, and DCR is the Inductor DCR

value.

I

IDROOP

+

AVG

R

(V

+ V

)

FB

DROOP

OFS

Therefore the equivalent loadline impedance, i.e. droop

impedance, is equal to Equation 11:

-

VDIFF

VSEN

RGND

R

DCR

R

ISEN

FB

------------ -----------------

R

=

⋅

(EQ. 11)

LL

N

V

+

OUT

+

-

Output-Voltage Offset Programming

The ISL6312 allows the designer to accurately adjust the

offset voltage by connecting a resistor, R , from the OFS

-

OUT

DIFFERENTIAL

REMOTE-SENSE

AMPLIFIER

OFS

is connected between OFS

pin to VCC or GND. When R

OFS

and VCC, the voltage across it is regulated to 1.6V. This

causes a proportional current (I ) to flow into the FB pin.

FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE

REGULATION WITH OFFSET ADJUSTMENT

OFS

is connected to ground, the voltage across it is

If R

OFS

Load-Line (Droop) Regulation

regulated to 0.4V, and I

flows out of the FB pin. The

OFS

Some microprocessor manufacturers require a

offset current flowing through the resistor between VDIFF

and FB will generate the desired offset voltage which is

precisely-controlled output resistance. This dependence of

output voltage on load current is often termed “droop” or

“load line” regulation. By adding a well controlled output

impedance, the output voltage can effectively be level shifted

in a direction which works to achieve the load-line regulation

required by these manufacturers.

equal to the product (I

x R ). These functions are

OFS

FB

shown in Figures 7 and 8.

Once the desired output offset voltage has been determined,

use the following formulas to set R

:

OFS

In other cases, the designer may determine that a more

cost-effective solution can be achieved by adding droop.

Droop can help to reduce the output-voltage spike that

results from fast load-current demand changes.

For Negative Offset (connect R

to GND):

OFS

0.4 ⋅ R

FB

(EQ. 12)

(EQ. 13)

--------------------------

OFFSET

R

=

OFS

V

For Positive Offset (connect R

to VCC):

OFS

The magnitude of the spike is dictated by the ESR and ESL

of the output capacitors selected. By positioning the no-load

voltage level near the upper specification limit, a larger

1.6 ⋅ R

FB

--------------------------

OFFSET

R

=

OFS

V

FN9289.6

February 1, 2011

19

ISL6312

a new code is established and it remains stable for 3

FB

consecutive readings (1ms to 1.33ms), the ISL6312

recognizes the new code and changes the internal DAC

reference directly to the new level. The Intel processor

controls the VID transitions and is responsible for

incrementing or decrementing one VID step at a time. In

VR10 and VR11 settings, the ISL6312 will immediately

change the internal DAC reference to the new requested

value as soon as the request is validated, which means the

fastest recommended rate at which a bit change can occur is

once every 2ms. In cases where the reference step is too

large, the sudden change can trigger overcurrent or

overvoltage events.

-

E/A

I

V

OFS

+

R

FB

REF

1:1

VDIFF

CURRENT

MIRROR

I

OFS

VCC

-

In order to ensure the smooth transition of output voltage

during a VR10 or VR11 VID change, a VID step change

smoothing network is required. This network is composed of

an internal 1kΩ resistor between the DAC and the REF pin,

and the external capacitor CREF, between the REF pin and

ground. The selection of CREF is based on the time duration

for 1 bit VID change and the allowable delay time.

1.6V

R

OFS

+

OFS

ISL6312

VCC

FIGURE 7. POSITIVE OFFSET OUTPUT VOLTAGE

PROGRAMMING

Assuming the microprocessor controls the VID change at 1

bit every TVID, the relationship between CREF and TVID is

given by Equation 14.

FB

+

OFS

-

E/A

V

C

= 0.001(S) ⋅ T

REF VID

R

(EQ. 14)

I

FB

OFS

As an example, for a VID step change rate of 5ms per bit,

the value of CREF is 5600pF based on Equation 14.

REF

VDIFF

VCC

AMD DYNAMIC VID TRANSITIONS

1:1

When running in AMD 5-bit or 6-bit modes of operation, the

ISL6312 responds differently to a dynamic VID change then

when in Intel VR10 or VR11 mode. In the AMD modes the

ISL6312 still checks the VID inputs on the positive edge of

an internal 3MHz clock. In these modes the VID code can be

changed by more than a 1-bit step at a time. If a new code is

established and it remains stable for 3 consecutive readings

(1ms to 1.33ms), the ISL6312 recognizes the change and

begins slewing the DAC in 6.25mV steps at a stepping

frequency of 330kHz until the VID and DAC are equal. Thus,

the total time required for a VID change, tDVID, is dependent

only on the size of the VID change (DVVID).

CURRENT

MIRROR

I

OFS

+

-

0.4V

OFS

R

OFS

ISL6312

GND

FIGURE 8. NEGATIVE OFFSET OUTPUT VOLTAGE

PROGRAMMING

The time required for a ISL6312-based converter in AMD

5-bit DAC configuration to make a 1.1V to 1.5V reference

voltage change is about 194ms, as calculated using

Dynamic VID

Modern microprocessors need to make changes to their core

voltage as part of normal operation. They direct the ISL6312 to

do this by making changes to the VID inputs. The ISL6312 is

required to monitor the DAC inputs and respond to on-the-fly

VID changes in a controlled manner, supervising a safe output

voltage transition without discontinuity or disruption. The DAC

mode the ISL6312 is operating in determines how the controller

responds to a dynamic VID change.

Equation 15.

ΔV

1

VID

⎛

⋅

3

⎞

⎠

------------------------- ---------------------

t

=

(EQ. 15)

DVID

⎝

0.00625

330 × 10

In order to ensure the smooth transition of output voltage

during an AMD VID change, a VID step change smoothing

network is required. This network is composed of an internal

1kΩ resistor between the DAC and the REF pin, and the

INTEL DYNAMIC VID TRANSITIONS

external capacitor C

, between the REF pin and ground.

REF

When in Intel VR10 or VR11 mode the ISL6312 checks the

VID inputs on the positive edge of an internal 3MHz clock. If

For AMD VID transitions C

capacitor.

should be a 1000pF

REF

FN9289.6

February 1, 2011

20

ISL6312

Once the PHASE is high, the advanced adaptive

User Selectable Adaptive Deadtime Control

Techniques

shoot-through circuitry monitors the PHASE and UGATE

voltages during a PWM falling edge and the subsequent

UGATE turn-off. If either the UGATE falls to less than 1.75V

above the PHASE or the PHASE falls to less than +0.8V, the

LGATE is released to turn on.

The ISL6312 integrated drivers incorporate two different

adaptive deadtime control techniques, which the user can

choose between. Both of these control techniques help to

minimize deadtime, resulting in high efficiency from the reduced

freewheeling time of the lower MOSFET body-diode

conduction, and both help to prevent the upper and lower

MOSFETs from conducting simultaneously. This is

accomplished by ensuring either rising gate turns on its

MOSFET with minimum and sufficient delay after the other has

turned off.

Internal Bootstrap Device

All three integrated drivers feature an internal bootstrap

schottky diode. Simply adding an external capacitor across

the BOOT and PHASE pins completes the bootstrap circuit.

The bootstrap function is also designed to prevent the

bootstrap capacitor from overcharging due to the large

negative swing at the PHASE node. This reduces voltage

stress on the boot to phase pins.

The difference between the two adaptive deadtime control

techniques is the method in which they detect that the lower

MOSFET has transitioned off in order to turn on the upper

MOSFET. The state of the DRSEL pin chooses which of the

two control techniques is active. By tying the DRSEL pin

directly to ground, the PHASE Detect Scheme is chosen,

which monitors the voltage on the PHASE pin to determine if

the lower MOSFET has transitioned off or not. Tying the

DRSEL pin to VCC though a 50kΩ resistor selects the

LGATE Detect Scheme, which monitors the voltage on the

LGATE pin to determine if the lower MOSFET has turned off

or not. For both schemes, the method for determining

whether the upper MOSFET has transitioned off in order to

signal to turn on the lower MOSFET is the same.

1.6

1.4

1.2

1.0

0.8

0.6

Q

= 100nC

GATE

0.4

50nC

0.2

0.0

20nC

PHASE DETECT

If the DRSEL pin is tied directly to ground, the PHASE Detect

adaptive deadtime control technique is selected. For the

PHASE detect scheme, during turn-off of the lower MOSFET,

the PHASE voltage is monitored until it reaches a -0.3V/+0.8V

(forward/reverse inductor current). At this time the UGATE is

released to rise. An auto-zero comparator is used to correct the

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

ΔV (V)

BOOT_CAP

FIGURE 9. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

r

drop in the phase voltage preventing false detection of

DS(ON)

the -0.3V phase level during r

The bootstrap capacitor must have a maximum voltage

rating above PVCC + 4V and its capacitance value can be

conduction period. In the

DS(ON)

case of zero current, the UGATE is released after 35ns delay of

the LGATE dropping below 0.5V. When LGATE first begins to

transition low, this quick transition can disturb the PHASE node

and cause a false trip, so there is 20ns of blanking time once

LGATE falls until PHASE is monitored.

chosen from Equation 16: where Q is the amount of gate

G1

charge per upper MOSFET at V

gate-source voltage and

GS1

is the number of control MOSFETs. The ΔV

N

Q1

BOOT_CAP

term is defined as the allowable droop in the rail of the upper

gate drive.

Once the PHASE is high, the advanced adaptive

shoot-through circuitry monitors the PHASE and UGATE

voltages during a PWM falling edge and the subsequent

UGATE turn-off. If either the UGATE falls to less than 1.75V

above the PHASE or the PHASE falls to less than +0.8V, the

LGATE is released to turn-on.

Q

GATE

-------------------------------------

C

Q

≥

BOOT_CAP

ΔV

BOOT_CAP

(EQ. 16)

Q

⋅ PVCC

G1

V

----------------------------------

=

⋅ N

Q1

GATE

GS1

LGATE DETECT

Gate Drive Voltage Versatility

If the DRSEL pin is tied to VCC through a 50kΩ resistor, the

LGATE Detect adaptive deadtime control technique is selected.

For the LGATE detect scheme, during turn-off of the lower

MOSFET, the LGATE voltage is monitored until it reaches

1.75V. At this time the UGATE is released to rise.

The ISL6312 provides the user flexibility in choosing the

gate drive voltage for efficiency optimization. The controller

ties the upper and lower drive rails together. Simply applying

a voltage from 5V up to 12V on PVCC sets both gate drive

rail voltages simultaneously.

FN9289.6

February 1, 2011

21

ISL6312

In order for the ISL6312 to begin operation, PVCC1 is the

only pin that is required to have a voltage applied that

exceeds POR. However, for 2 or 3-phase operation

PVCC2 and PVCC3 must also exceed the POR

threshold. Hysteresis between the rising and falling

thresholds assure that once enabled, the ISL6312 will not

inadvertently turn off unless the PVCC bias voltage drops

substantially (see “Electrical Specifications” on page 6).

Initialization

Prior to initialization, proper conditions must exist on the EN,

VCC, PVCC and the VID pins. When the conditions are met,

the controller begins soft-start. Once the output voltage is

within the proper window of operation, the controller asserts

PGOOD.

ISL6312 INTERNAL CIRCUIT

EXTERNAL CIRCUIT

VCC

For Intel VR10, VR11 and AMD 6-bit modes of operation

these are the only conditions that must be met for the

controller to immediately begin the soft-start sequence. If

running in AMD 5-bit mode of operation there is one more

condition that must be met:

PVCC1

+12V

POR

CIRCUIT

5. The VID code must not be 11111 in AMD 5-bit mode. This

code signals the controller that no load is present. The

controller will not allow soft-start to begin if this VID code

is present on the VID pins.

ENABLE

COMPARATOR

10.7kΩ

EN

+

-

Once all of these conditions are met the controller will begin

the soft-start sequence and will ramp the output voltage up

to the user designated level.

1.40kΩ

0.85V

Intel Soft-Start

+

-

EN_PH4

The soft-start function allows the converter to bring up the

output voltage in a controlled fashion, resulting in a linear

ramp-up. The soft-start sequence for the Intel modes of

operation is slightly different then the AMD soft-start

sequence.

SOFT-START

AND

FAULT LOGIC

1.21V

FIGURE 10. POWER SEQUENCING USING THRESHOLD-

SENSITIVE ENABLE (EN) FUNCTION

For the Intel VR10 and VR11 modes of operation, the

soft-start sequence if composed of four periods, as shown in

Figure 11. Once the ISL6312 is released from shutdown and

soft-start begins (as described in “Enable and Disable” on

page 22), the controller will have fixed delay period TD1.

After this delay period, the VR will begin first soft-start ramp

until the output voltage reaches 1.1V VBOOT voltage. Then,

the controller will regulate the VR voltage at 1.1V for another

fixed period TD3. At the end of TD3 period, ISL6312 will

read the VID signals. If the VID code is valid, ISL6312 will

initiate the second soft-start ramp until the output voltage

reaches the VID voltage plus/minus any offset or droop

voltage.

Enable and Disable

While in shutdown mode, the PWM outputs are held in a

high-impedance state to assure the drivers remain off. The

following input conditions must be met, for both Intel and

AMD modes of operation, before the ISL6312 is released

from shutdown mode to begin the soft-start start-up

sequence:

1. The bias voltage applied at VCC must reach the internal

power-on reset (POR) rising threshold. Once this

threshold is reached, proper operation of all aspects of

the ISL6312 is guaranteed. Hysteresis between the rising

and falling thresholds assure that once enabled, the

ISL6312 will not inadvertently turn off unless the bias

voltage drops substantially (see “Electrical

The soft-start time is the sum of the 4 periods as shown in

Equation 17.

Specifications” on page 6).

T

= TD1 + TD2 + TD3 + TD4

(EQ. 17)

SS

2. The voltage on EN must be above 0.85V. The EN input

allows for power sequencing between the controller bias

voltage and another voltage rail. The enable comparator

holds the ISL6312 in shutdown until the voltage at EN

rises above 0.85V. The enable comparator has 110mV of

hysteresis to prevent bounce.

3. The voltage on the EN_PH4 pin must be above 1.21V.

The EN_PH4 input allows for power sequencing between

the controller and the external driver.

4. The driver bias voltage applied at the PVCC pins must

reach the internal power-on reset (POR) rising threshold.

FN9289.6

February 1, 2011

22

ISL6312

.

V

1

VID

⎛

⋅

⎞

⎠

(EQ. 20)

------------------------- ---------------------

TDB =

⎝

3

0.00625

330 × 10

VOUT, 500mV/DIV

After the DAC voltage reaches the final VID setting, PGOOD

will be set to high with the fixed delay TDC. The typical value

for TDC can range between 1.5ms and 3.0ms.

TD1

TD2

TD5

TD3 TD4

VOUT, 500mV/DIV

EN_VTT

PGOOD

TDC

TDB

TDA

500µs/DIV

FIGURE 11. SOFT-START WAVEFORMS

EN_VTT

PGOOD

TD1 is a fixed delay with the typical value as 1.40ms. TD3 is

determined by the fixed 85µs plus the time to obtain valid

VID voltage. If the VID is valid before the output reaches the

1.1V, the minimum time to validate the VID input is 500ns.

Therefore the minimum TD3 is about 86µs.

500µs/DIV

FIGURE 12. SOFT-START WAVEFORMS

During TD2 and TD4, ISL6312 digitally controls the DAC

voltage change at 6.25mV per step. The time for each step is

determined by the frequency of the soft-start oscillator which

Pre-Biased Soft-Start

is defined by the resistor R from SS pin to GND. The

second soft-start ramp time TD2 and TD4 can be calculated

based on Equations 18 and 19:

SS

The ISL6312 also has the ability to start up into a

pre-charged output, without causing any unnecessary

disturbance. The FB pin is monitored during soft-start, and

should it be higher than the equivalent internal ramping

reference voltage, the output drives hold both MOSFETs off.

1.1 ⋅ R

SS

------------------------

TD2 =

(μs)

(EQ. 18)

6.25 ⋅ 25

OUTPUT PRECHARGED

ABOVE DAC LEVEL

(V

– 1.1) ⋅ R

SS

6.25 ⋅ 25

VID

(EQ. 19)

---------------------------------------------------

TD4 =

(μs)

For example, when VID is set to 1.5V and the R is set at

SS

100kΩ, the first soft-start ramp time TD2 will be 704µs and

OUTPUT PRECHARGED

BELOW DAC LEVEL

the second soft-start ramp time TD4 will be 256µs.

NOTE: If the SS pin is grounded, the soft-start ramp in TD2

and TD4 will be defaulted to a 6.25mV step frequency of

330kHz.

V

(0.5V/DIV)

GND>

OUT

After the DAC voltage reaches the final VID setting, PGOOD

will be set to high with the fixed delay TD5. The typical value

for TD5 is 440µs.

EN (5V/DIV)

T1 T2

T3

AMD Soft-Start

FIGURE 13. SOFT-START WAVEFORMS FOR ISL6312-BASED

MULTIPHASE CONVERTER

For the AMD 5-bit and 6-bit modes of operation, the

soft-start sequence is composed of three periods, as shown

in Figure 12. At the beginning of soft-start, the VID code is

immediately obtained from the VID pins, followed by a fixed

delay period TDA. After this delay period the ISL6312 will

begin ramping the output voltage to the desired DAC level at

a fixed rate of 6.25mV per step, with a stepping frequency of

330kHz. The amount of time required to ramp the output

voltage to the final DAC voltage is referred to as TDB, and

can be calculated as shown in Equation 20:

Once the internal ramping reference exceeds the FB pin

potential, the output drives are enabled, allowing the output

to ramp from the pre-charged level to the final level dictated

by the DAC setting. Should the output be pre-charged to a

level exceeding the DAC setting, the output drives are

enabled at the end of the soft-start period, leading to an

abrupt correction in the output voltage down to the DAC-set

level.

FN9289.6

February 1, 2011

23

ISL6312

Overvoltage Protection

Fault Monitoring and Protection

The ISL6312 constantly monitors the sensed output voltage

on the VDIFF pin to detect if an overvoltage event occurs.

When the output voltage rises above the OVP trip level

actions are taken by the ISL6312 to protect the

microprocessor load. The overvoltage protection trip level

changes depending on what mode of operation the controller

is in and what state the OVPSEL and VRSEL pins are in.

Tables 6 and 7 list what the OVP trip levels are under all

conditions.

The ISL6312 actively monitors output voltage and current to

detect fault conditions. Fault monitors trigger protective

measures to prevent damage to a microprocessor load. One

common power good indicator is provided for linking to

external system monitors. The schematic in Figure 14

outlines the interaction between the fault monitors and the

power good signal.

170µA

-

At the inception of an overvoltage event, LGATE1, LGATE2

and LGATE3 are commanded high, PWM4 is commanded

low, and the PGOOD signal is driven low. This turns on the

all of the lower MOSFETs and pulls the output voltage below

a level that might cause damage to the load. The LGATE

outputs remain high and PWM4 remains low until VDIFF falls

100mV below the OVP threshold that tripped the overvoltage

protection circuitry. The ISL6312 will continue to protect the

load in this fashion as long as the overvoltage condition

recurs. Once an overvoltage condition ends the ISL6312

latches off, and must be reset by toggling EN, or through

POR, before a soft-start can be reinitiated.

OCL

+

I

1

REPEAT FOR

EACH CHANNEL

VDAC

VRSEL

125µA

-

+175mV,

+250mV,

+350mV

OCP

+

I

AVG

OVPSEL

SOFT-START, FAULT

AND CONTROL LOGIC

V

OVP

TABLE 6. INTEL VR10 AND VR11 OVP THRESHOLDS

MODE OF

OPERATION

OVPSEL PIN OPEN OVPSEL PIN TIED

-

OR TIED TO GND

TO VCC

OV

UV

VSEN

+

Soft-Start

(TD1 and TD2)

1.280V and

VDAC + 175mV

(higher of the two)

1.280V and

VDAC + 350mV

(higher of the two)

+

PGOOD

x1

-

RGND

VDIFF

Soft-Start

(TD3 and TD4)

VDAC + 175mV

VDAC + 350mV

+

Normal Operation

VDAC + 175mV

VDAC + 350mV

0.60 x DAC

ISL6312 INTERNAL CIRCUITRY

TABLE 7. AMD OVP THRESHOLDS

MODE OF OVPSEL PIN OPEN OVPSEL PIN TIED

FIGURE 14. POWER GOOD AND PROTECTION CIRCUITRY

OPERATION

OR TIED TO GND

TO VCC

Power Good Signal

Soft-Start

2.200V and

VDAC + 250mV

(higher of the two)

2.200V and

VDAC + 350mV

(higher of the two)

The power good pin (PGOOD) is an open-drain logic output

that signals whether or not the ISL6312 is regulating the

output voltage within the proper levels, and whether any fault

conditions exist. This pin should be tied to a +5V source

through a resistor.

Normal Operation

VDAC + 250mV

VDAC + 350mV

One exception that overrides the overvoltage protection

circuitry is a dynamic VID transition in AMD modes of

operation. If a new VID code is detected during normal

operation, the OVP protection circuitry is disabled from the

beginning of the dynamic VID transition, until 50µs after the

internal DAC reaches the final VID setting. This is the only

time during operation of the ISL6312 that the OVP circuitry is

not active.

During shutdown and soft-start PGOOD pulls low and

releases high after a successful soft-start and the output

voltage is operating between the undervoltage and

overvoltage limits. PGOOD transitions low when an

undervoltage, overvoltage, or overcurrent condition is

detected or when the controller is disabled by a reset from

EN, EN_PH4, POR, or one of the no-CPU VID codes. In the

event of an overvoltage or overcurrent condition, the

controller latches off and PGOOD will not return high until

after a successful soft-start. In the case of an undervoltage

event, PGOOD will return high when the output voltage

returns to within the undervoltage.

Pre-POR Overvoltage Protection

Prior to PVCC and VCC exceeding their POR levels, the

ISL6312 is designed to protect the load from any overvoltage

events that may occur. This is accomplished by means of an

internal 10kΩ resistor tied from PHASE to LGATE, which

FN9289.6

February 1, 2011

24

ISL6312

turns on the lower MOSFET to control the output voltage

until the overvoltage event ceases or the input power supply

cuts off. For complete protection, the low side MOSFET

should have a gate threshold well below the maximum

voltage rating of the load/microprocessor.

–6

125 ⋅ 10 ⋅ R

⋅ N

⎞

⎟

⎠

R + R

1 2

R

2

⎛

⎜

⎝

⎛

⎜

⎝

⎞

⎟

⎠

ISEN

(EQ. 22)

---------------------------------------------------------

--------------------

I

=

⋅

OCP

DCR

I

> I

OCP

OCP, min

The overcurrent trip level of the ISL6312 cannot be set any

lower then the I level calculated above. If an

In the event that during normal operation the PVCC or VCC

voltage falls back below the POR threshold, the pre-POR

overvoltage protection circuitry reactivates to protect from

any more pre-POR overvoltage events.

OCP,min

overcurrent trip level lower then I

is desired, then the

OCP,min

ISL6312A should be used in the place of the ISL6312.

At the beginning of overcurrent shutdown, the controller sets

all of the UGATE and LGATE signals low, puts PWM4 in a

high-impedance state, and forces PGOOD low. This turns off

all of the upper and lower MOSFETs. The system remains in

this state for fixed period of 12ms. If the controller is still

enabled at the end of this wait period, it will attempt a soft-

start. If the fault remains, the trip-retry cycles will continue

indefinitely until either the controller is disabled or the fault is

cleared. Note that the energy delivered during trip-retry

cycling is much less than during full-load operation, so there

is no thermal hazard.

Undervoltage Detection

The undervoltage threshold is set at 60% of the VID code.

When the output voltage (VSEN-RGND) is below the

undervoltage threshold, PGOOD gets pulled low. No other

action is taken by the controller. PGOOD will return high if

the output voltage rises above 70% of the VID code.

Open Sense Line Prevention

In the case that either of the remote sense lines, VSEN or

GND, become open, the ISL6312 is designed to prevent the

controller from regulating. This is accomplished by means of

a small 5µA pull-up current on VSEN, and a pull-down

current on RGND. If the sense lines are opened at any time,

the voltage difference between VSEN and RGND will

increase until an overvoltage event occurs, at which point

overvoltage protection activates and the controller stops

regulating. The ISL6312 will be latched off and cannot be

restarted until the controller is reset.

OUTPUT CURRENT, 50A/DIV

0A

Overcurrent Protection

The ISL6312 takes advantage of the proportionality between

OUTPUT VOLTAGE,

500mV/DIV

the load current and the average current, I

, to detect an

AVG

overcurrent condition. See “Continuous Current Sampling”

on page 12 for more detail on how the average current is

measured. The average current is continually compared with

a constant 125µA OCP reference current as shown in

Figure 14. Once the average current exceeds the OCP

reference current, a comparator triggers the converter to

begin overcurrent protection procedures.

0V

3ms/DIV

FIGURE 15. OVERCURRENT BEHAVIOR IN HICCUP MODE

Individual Channel Overcurrent Limiting

The ISL6312 has the ability to limit the current in each

individual channel without shutting down the entire regulator.

This is accomplished by continuously comparing the sensed

currents of each channel with a constant 170μA OCL

reference current as shown in Figure 14. If a channel’s

individual sensed current exceeds this OCL limit, the UGATE

signal of that channel is immediately forced low, and the

LGATE signal is forced high. This turns off the upper

MOSFET(s), turns on the lower MOSFET(s), and stops the

rise of current in that channel, forcing the current in the

channel to decrease. That channel’s UGATE signal will not

be able to return high until the sensed channel current falls

back below the 170µA reference.

This method for detecting overcurrent events limits the

minimum overcurrent trip threshold because of the fact the

ISL6312 uses set internal R

current sense resistors.

ISEN

The minimum overcurrent trip threshold is dictated by the

DCR of the inductors and the number of active channels. To

calculate the minimum overcurrent trip level, I

, use

OCP,min

Equation 21, where N is the number of active channels, DCR

is the individual inductor’s DCR, and R

internal current sense resistor.

is the 300Ω

ISEN

–6

125 ⋅ 10 ⋅ R

⋅ N

ISEN

(EQ. 21)

---------------------------------------------------------

=

I

OCP, min

DCR

If the desired overcurrent trip level is greater then the

minimum overcurrent trip level, I , then the resistor

OCP,min

divider R-C circuit around the inductor shown in Figure 5

should be used to set the desired trip level.

FN9289.6

February 1, 2011

25

ISL6312

General Design Guide

This design guide is intended to provide a high-level

⎛

⎜

⎝

⎞

⎟

⎛I

⎞

⎟

I

(EQ. 24)

M

PP

2 ⎠

M

P

= V

⋅ f

⋅

S

PP

2

⋅ t

+

⋅ t

d2

⎜

---------

LOW, 2

D(ON)

------ + ---------

------ –

d1

⎟

⎝ N

N

⎠

explanation of the steps necessary to create a multiphase

power converter. It is assumed that the reader is familiar with

many of the basic skills and techniques referenced below. In

addition to this guide, Intersil provides complete reference

designs that include schematics, bills of materials, and example

board layouts for all common microprocessor applications.

The total maximum power dissipated in each lower MOSFET

is approximated by the summation of P and P

.

LOW,2

LOW,1

UPPER MOSFET POWER CALCULATION

In addition to r losses, a large portion of the

DS(ON)

upper-MOSFET losses are due to currents conducted

across the input voltage (V ) during switching. Since a

Power Stages

IN

substantially higher portion of the upper-MOSFET losses are

dependent on switching frequency, the power calculation is

more complex. Upper MOSFET losses can be divided into

separate components involving the upper-MOSFET

switching times, the lower-MOSFET body-diode

The first step in designing a multiphase converter is to

determine the number of phases. This determination

depends heavily on the cost analysis which in turn depends

on system constraints that differ from one design to the next.

Principally, the designer will be concerned with whether

components can be mounted on both sides of the circuit

board, whether through-hole components are permitted, the

total board space available for power-supply circuitry, and

the maximum amount of load current. Generally speaking,

the most economical solutions are those in which each

phase handles between 25A and 30A. All surface-mount

designs will tend toward the lower end of this current range.

If through-hole MOSFETs and inductors can be used, higher

per-phase currents are possible. In cases where board

space is the limiting constraint, current can be pushed as

high as 40A per phase, but these designs require heat sinks

and forced air to cool the MOSFETs, inductors and heat-

dissipating surfaces.

reverse-recovery charge, Q , and the upper MOSFET

rr

r

conduction loss.

DS(ON)

When the upper MOSFET turns off, the lower MOSFET does

not conduct any portion of the inductor current until the

voltage at the phase node falls below ground. Once the

lower MOSFET begins conducting, the current in the upper

MOSFET falls to zero as the current in the lower MOSFET

ramps up to assume the full inductor current. In Equation 25,

the required time for this commutation is t and the

1

approximated associated power loss is P

.

UP,1

t

I

⎛

⎜

⎝

⎞

⎟

⎠

1

M

PP

2

⎛

⎝

⎞

(EQ. 25)

P

≈ V

⋅

⋅ f

S

----

----- + --------

UP,1

IN

⎠

2

N

MOSFETS

At turn on, the upper MOSFET begins to conduct and this

transition occurs over a time t . In Equation 26, the

The choice of MOSFETs depends on the current each

MOSFET will be required to conduct, the switching frequency,

the capability of the MOSFETs to dissipate heat, and the

availability and nature of heat sinking and air flow.

2

approximate power loss is P

.

UP,2

I

t

2

⎛I

⎞

⎟

⎠

⎛

⎜

⎝

⎞

⎟

⎠

PP

2

M

(EQ. 26)

P

≈ V

⋅

⋅ f

--------

----

⎜

⎝

----- –

UP,2

IN

S

N

LOWER MOSFET POWER CALCULATION

The calculation for power loss in the lower MOSFET is

simple, since virtually all of the loss in the lower MOSFET is

due to current conducted through the channel resistance

A third component involves the lower MOSFET reverse-

recovery charge, Q . Since the inductor current has fully

rr

commutated to the upper MOSFET before the lower-

(r

). In Equation 23, I is the maximum continuous

M

DS(ON)

output current, I is the peak-to-peak inductor current (see

MOSFET body diode can recover all of Q , it is conducted

rr

PP

through the upper MOSFET across VIN. The power

Equation 1), and d is the duty cycle (V

/V ).

OUT IN

dissipated as a result is P

.

UP,3

2

I

⋅ (1 – d)

⎛

⎜

⎝

⎞

⎟

⎠

(EQ. 23)

I

L, PP

M

P

= r

⋅

DS(ON)

⋅ (1 – d) + ------------------------------------

-----

(EQ. 27)

LOW, 1

P

= V ⋅ Q ⋅ f

IN rr S

12

N

UP,3

Finally, the resistive part of the upper MOSFET is given in

An additional term can be added to the lower-MOSFET loss

equation to account for additional loss accrued during the

dead time when inductor current is flowing through the

lower-MOSFET body diode. This term is dependent on the

Equation 28 as P

.

UP,4

2

⎛

⎜

⎝

⎞

⎟

⎠

I

PP

I

M

(EQ. 28)

P

≈ r

⋅ d ⋅

DS(ON)

+

---------

12

-----

UP,4

N

diode forward voltage at I , V

, the switching

M

D(ON)

frequency, f , and the length of dead times, t and t , at

S

d1 d2

the beginning and the end of the lower-MOSFET conduction

interval respectively.

FN9289.6

February 1, 2011

26

ISL6312

The total power dissipated by the upper MOSFET at full load

can now be approximated as the summation of the results

from Equations 25, 26, 27 and 28. Since the power

equations depend on MOSFET parameters, choosing the

correct MOSFETs can be an iterative process involving

repetitive solutions to the loss equations for different

MOSFETs and different switching frequencies.

PVCC

BOOT

D

C

GD

R

HI1

G

UGATE

C

DS

R

LO1

R

GI1

C

G1

Package Power Dissipation

GS

Q1

When choosing MOSFETs it is important to consider the

amount of power being dissipated in the integrated drivers

located in the controller. Since there are a total of three

drivers in the controller package, the total power dissipated

by all three drivers must be less than the maximum

allowable power dissipation for the QFN package.

S

PHASE

FIGURE 16. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

PVCC

Calculating the power dissipation in the drivers for a desired

application is critical to ensure safe operation. Exceeding the

maximum allowable power dissipation level will push the IC

beyond the maximum recommended operating junction

temperature of +125°C. The maximum allowable IC power

dissipation for the 7x7 QFN package is approximately 3.5W

at room temperature. See “Layout Considerations” on

page 32 for thermal transfer improvement suggestions.

D

C

GD

R

HI2

G

LGATE

C

DS

R

LO2

R

GI2

C

G2

GS

Q2

S

When designing the ISL6312 into an application, it is

recommended that the following calculation is used to

ensure safe operation at the desired frequency for the

selected MOSFETs. The total gate drive power losses,

FIGURE 17. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

P

, due to the gate charge of MOSFETs and the

The total gate drive power losses are dissipated among the

resistive components along the transition path and in the

bootstrap diode. The portion of the total power dissipated in

the controller itself is the power dissipated in the upper drive

Qg_TOT

integrated driver’s internal circuitry and their corresponding

average driver current can be estimated with Equations 29

and 30, respectively.

path resistance, P

, the lower drive path resistance,

DR_UP

P

= P

+ P

+ I ⋅ VCC

Qg_Q2 Q

(EQ. 29)

Qg_TOT

Qg_Q1

P

, and in the boot strap diode, P

. The rest of the

DR_UP

BOOT

power will be dissipated by the external gate resistors (R

G1

and R ) of

and R ) and the internal gate resistors (R

3

2

G2

GI1

GI2

--

P

=

⋅ Q

⋅ PVCC ⋅ F

⋅ N

Q2

⎞

⋅ N

Q1 PHASE

Qg_Q1

G1

SW

the MOSFETs. Figures 16 and 17 show the typical upper

and lower gate drives turn-on transition path. The total power

dissipation in the controller itself, P , can be roughly

DR

estimated as:

P

= Q

⋅ PVCC ⋅ F

⋅ N

PHASE

Qg_Q2

G2

SW

(EQ. 30)

P

= P

+ P

+ (I ⋅ VCC)

BOOT Q

DR

DR_UP

DR_LOW

(EQ. 31)

3

2

⎛

--

I

=

⋅ Q

⋅ N

+ Q

⋅ N

⋅ F

+ I

SW Q

DR

G1

G2

Q2

⎠

PHASE

⎝

Q1

P

Qg_Q1

3

---------------------

P

=

BOOT

In Equations 29 and 30, P

is the total upper gate drive

R

P

Qg_Q1

is the total lower gate drive power

⎛

⎜

⎝

⎞

HI1

LO1

-------------------------------------- --------------------------------------- ---------------------

P

=

+

⋅

⎟

⎠

DR_UP

power loss and P

R

+ R

R

+ R

EXT1

3

Qg_Q2

HI1

EXT1

LO1

loss; the gate charge (Q and Q ) is defined at the

G1 G2

R

P

Qg_Q2

particular gate to source drive voltage PVCC in the

⎛

⎜

⎝

⎞

HI2

LO2

-------------------------------------- --------------------------------------- ---------------------

P

R

=

+

⋅

⎟

DR_LOW

corresponding MOSFET data sheet; I is the driver total

R

+ R

R

+ R

⎠

EXT2

2

Q

HI2

EXT2

LO2

quiescent current with no load at both drive outputs; N

Q1

R

and N are the number of upper and lower MOSFETs per

GI1

GI2

Q2

-------------

= R

+

R

= R

G2

+

EXT1

G1

EXT2

N

phase, respectively; N

PHASE

is the number of active

Q1

Q2

phases. The I VCC product is the quiescent power of the

Q*

controller without capacitive load and is typically 75mW at

300kHz.

FN9289.6

February 1, 2011

27

ISL6312

2. Plug the inductor L and DCR component values, and the

Inductor DCR Current Sensing Component

Selection

value for C chosen in step 1, into Equation 33 to

1

calculate the value for R .

1

The ISL6312 senses each individual channel’s inductor

current by detecting the voltage across the output inductor

DCR of that channel (as described in the “Continuous

Current Sampling” on page 12). As Figure 18 illustrates, an

R-C network is required to accurately sense the inductor

DCR voltage and convert this information into a current,

which is proportional to the total output current. The time

constant of this R-C network must match the time constant

of the inductor L/DCR.

L

(EQ. 33)

I

= I

OCP, min

-------------------------

R

=

OCP

1

DCR ⋅ C

1

3. Resistor R should be left unpopulated.

2

If the desired overcurrent trip level, I

minimum overcurrent trip level, I

divider R-C circuit should be used to set the desired trip

level. Follow the steps below to choose the component

values for the resistor divider R-C current sensing

network:

, is greater then the

, then a resistor

OCP

OCP,min

V

IN

I

L

UGATE(n)

LGATE(n)

1. Choose an arbitrary value for C . The recommended

1

L

DCR

V

OUT

MOSFET

DRIVER

value is 0.1μF.

INDUCTOR

2. Plug the inductor L and DCR component values, the

C

OUT

-

V (s)

L

value for C chosen in step 1, the number of active

1

channels N, and the desired overcurrent protection level

-

V (s)

C

I

into Equations 34 and 35 to calculate the values for

OCP

R and R .

R

1

2

C

1

L ⋅ I

OCP

(EQ. 34)

(EQ. 35)

I

> I

OCP, min

R

= --------------------------------------

R

OCP

2*

1

2

C

⋅ 0.0375 ⋅ N

ISL6312 INTERNAL CIRCUIT

1

L ⋅ I

OCP

R

= ---------------------------------------------------------------------------------

C

⋅ (I

⋅ DCR – 0.0375 ⋅ N)

OCP

I

n

1

Due to errors in the inductance or DCR it may be necessary

to adjust the value of R and R to match the time constants

SAMPLE

1

2

correctly. The effects of time constant mismatch can be seen

in the form of droop overshoot or undershoot during the

initial load transient spike, as shown in Figure 19. Follow the

steps below to ensure the R-C and inductor L/DCR time

constants are matched accurately.

+

-

ISEN-(n)

ISEN+(n)

-

V (s)

C

R

ISEN

*R is OPTIONAL

2

I

SEN

1. Capture a transient event with the oscilloscope set to

about L/DCR/2 (sec/div). For example, with L = 1μH and

DCR = 1mΩ, set the oscilloscope to 500μs/div.

FIGURE 18. DCR SENSING CONFIGURATION

The R-C network across the inductor also sets the

2. Record ΔV1 and ΔV2 as shown in Figure 19.

overcurrent trip threshold for the regulator. Before the R-C

components can be selected, the desired overcurrent

protection level should be chosen. The minimum overcurrent

trip threshold the controller can support is dictated by the

DCR of the inductors and the number of active channels. To

ΔV

calculate the minimum overcurrent trip level, I

, use

2

OCP,min

ΔV

1

Equation 32, where N is the number of active channels, and

DCR is the individual inductor’s DCR.

V

I

OUT

0.0375 ⋅ N

DCR

(EQ. 32)

I

= --------------------------

OCP, min

The overcurrent trip level of the ISL6312 cannot be set any

lower then the I level calculated above. If the

TRAN

OCP,min

ΔI

minimum overcurrent trip level is desired, follow the

steps below to choose the component values for the

R-C current sensing network:

1. Choose an arbitrary value for C . The recommended

1

FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR

value is 0.1µF.

FN9289.6

February 1, 2011

28

ISL6312

3. Select new values, R

1,NEW

and R

, for the time

2,NEW

COMPENSATION WITH LOAD-LINE REGULATION

constant resistors based on the original values, R

1,OLD

The load-line regulated converter behaves in a similar

manner to a peak current mode controller because the two

poles at the output filter L-C resonant frequency split with the

introduction of current information into the control loop. The

final location of these poles is determined by the system

function, the gain of the current signal, and the value of the

and R

, using Equations 36 and 37.

2,OLD

ΔV

1

(EQ. 36)

----------

R

= R

⋅

1, NEW

1, OLD

2, OLD

ΔV

2

ΔV

1

(EQ. 37)

----------

R

= R

2, NEW

ΔV

2

compensation components, R and C .

C

(OPTIONAL)

2

4. Replace R and R with the new values and check to see

1

2

that the error is corrected. Repeat the procedure if

necessary.

C

R

C

COMP

Loadline Regulation Resistor

If loadline regulation is desired, the IDROOP pin should be

shorted to the FB pin in order for the internal average

sense current to flow out across the loadline regulation

FB

IDROOP

VDIFF

ISL6312

resistor, labeled R in Figure 6. This resistor’s value sets

FB

R

FB

the desired loadline required for the application. The

desired loadline, R , can be calculated by Equation 38

LL

where V

current I

is the desired droop voltage at the full load

DROOP

.

FL

FIGURE 20. COMPENSATION CONFIGURATION FOR

LOAD-LINE REGULATED ISL6312 CIRCUIT

V

DROOP

R

= ------------------------

(EQ. 38)

LL

I

FL

Since the system poles and zero are affected by the values

of the components that are meant to compensate them, the

solution to the system equation becomes fairly complicated.

Fortunately, there is a simple approximation that comes very

close to an optimal solution. Treating the system as though it

were a voltage-mode regulator, by compensating the L-C

poles and the ESR zero of the voltage mode approximation,

yields a solution that is always stable with very close to ideal

transient performance.

Based on the desired loadline, the loadline regulation

resistor, R , can be calculated from Equation 39 or

FB

Equation 40, depending on the R-C current sense circuitry

being employed. If a basic R-C sense circuit consisting of C1

and R1 is being used, use Equation 39. If a resistor divider

R-C sense circuit consisting of R1, R2, and C1 is being

used, use Equation 40.

R

⋅ N ⋅ 300

Select a target bandwidth for the compensated system, f0.

The target bandwidth must be large enough to assure

adequate transient performance, but smaller than 1/3 of the

per-channel switching frequency. The values of the

compensation components depend on the relationships of f0

to the L-C pole frequency and the ESR zero frequency. For

each of the following three, there is a separate set of

equations for the compensation components.

LL

(EQ. 39)

R

= ---------------------------------

FB

DCR

R

⋅ N ⋅ 300 ⋅ (R + R )

1 2

DCR ⋅ R

LL

(EQ. 40)

R

= ----------------------------------------------------------------

2

In Equations 39 and 40, R is the loadline resistance; N is

LL

the number of active channels; DCR is the DCR of the

individual output inductors; and R1 and R2 are the current

sense R-C resistors.

In Equation 41, L is the per-channel filter inductance divided

by the number of active channels; C is the sum total of all

output capacitors; ESR is the equivalent series resistance of

If no loadline regulation is required, the IDROOP pin should

be left open and not connected to anything. To choose the

value for R in this situation, please refer to the

“COMPENSATION WITHOUT LOAD-LINE REGULATION”

on page 30.

the bulk output filter capacitance; and V is the

PP

peak-to-peak sawtooth signal amplitude as described in the

“Electrical Specifications” on page 6.

FB

Once selected, the compensation values in Equation 41

assure a stable converter with reasonable transient

Compensation

performance. In most cases, transient performance can be

improved by making adjustments to RC. Slowly increase the

value of RC while observing the transient performance on an

oscilloscope until no further improvement is noted. Normally,

CC will not need adjustment. Keep the value of CC from

Equation 41 unless some performance issue is noted.

The two opposing goals of compensating the voltage

regulator are stability and speed. Depending on whether the

regulator employs the optional load-line regulation as

described in Load-Line Regulation, there are two distinct

methods for achieving these goals.

FN9289.6

February 1, 2011

29

ISL6312

.

C

2

1

------------------------------- > f

Case 1:

0

2 ⋅ π ⋅ L ⋅ C

C

R

C

2 ⋅ π ⋅ f ⋅ V

⋅

pp

L ⋅ C

COMP

FB

0

-------------------------------------------------------

⋅

FB

R

C

= R

C

0.66 ⋅ V

IN

0.66 ⋅ V

IN

= ----------------------------------------------------

C

1

2 ⋅ π ⋅ V

⋅ R ⋅ f

0

PP

FB

ISL6312

IDROOP

VDIFF

R

FB

1

-------------------------------

≤ f < -------------------------------------

0

2 ⋅ π ⋅ C ⋅ ESR

Case 2:

2 ⋅ π ⋅ L ⋅ C

2

V

⋅ (2 ⋅ π) ⋅ f ⋅ L ⋅ C

0

PP

----------------------------------------------------------------

⋅

FB

R

C

= R

(EQ. 41)

FIGURE 21. COMPENSATION CIRCUIT WITHOUT LOAD-LINE

REGULATION

C

0.66 ⋅ V

IN

0.66 ⋅ V

IN

= -------------------------------------------------------------------------------------

(2 ⋅ π) ⋅ f ⋅ V

2

⋅ R

⋅ L ⋅ C

In the solutions to the compensation equations, there is a

single degree of freedom. For the solutions presented in

0

PP

FB

Equation 42, R is selected arbitrarily. The remaining

compensation components are then selected according to

Equation 42.

FB

1

Case 3:

f

> -------------------------------------

0

2 ⋅ π ⋅ C ⋅ ESR

2 ⋅ π ⋅ f ⋅ V ⋅ L

0

pp

--------------------------------------------

⋅

FB

R

C

= R

C

0.66 ⋅ V ⋅ ESR

In Equation 42, L is the per-channel filter inductance divided

by the number of active channels; C is the sum total of all

output capacitors; ESR is the equivalent-series resistance of

IN

0.66 ⋅ V ⋅ ESR ⋅

C

IN

= ----------------------------------------------------------------

2 ⋅ π ⋅ V ⋅ R ⋅ f

⋅

0

L

PP

FB

the bulk output-filter capacitance; and V is the peak-to-

PP

peak sawtooth signal amplitude as described in “Electrical

Specifications” on page 6.

The optional capacitor C , is sometimes needed to bypass

2

noise away from the PWM comparator (see Figure 20). Keep

C ⋅ ESR

L ⋅ C – C ⋅ ESR

a position available for C , and be prepared to install a

high-frequency capacitor of between 22pF and 150pF in

case any leading edge jitter problem is noted.

2

-------------------------------------------

⋅

FB

R

C

= R

1

L ⋅ C – C ⋅ ESR

= -------------------------------------------

COMPENSATION WITHOUT LOAD-LINE REGULATION

R

FB

The non load-line regulated converter is accurately modeled

as a voltage-mode regulator with two poles at the L-C

resonant frequency and a zero at the ESR frequency. A

type III controller, as shown in Figure 20, provides the

necessary compensation.

0.75 ⋅ V

IN

C

R

= ------------------------------------------------------------------------------------------------------------

2

(2 ⋅ π) ⋅ f ⋅ f

⋅ ( L ⋅ C) ⋅ R ⋅ V

0

HF

FB (P – P)

2

⎛ ⎞

⋅ 2π

⋅ f ⋅ f

⋅ L ⋅ C ⋅ R

FB

V

0

HF

PP

⎝

⎠

= ----------------------------------------------------------------------------------------

The first step is to choose the desired bandwidth, f , of the

0

C

⋅

⋅ (2 ⋅ π ⋅ f

⋅ L ⋅ C–1)

0.75

V

IN

HF

compensated system. Choose a frequency high enough to

assure adequate transient performance but not higher than

1/3 of the switching frequency. The type-III compensator has

0.75 ⋅ V ⋅ (2 ⋅ π ⋅ f

⋅

L ⋅ C–1)

an extra high-frequency pole, f . This pole can be used for

IN

HF

C

= ------------------------------------------------------------------------------------------------------------

(EQ. 42)

C

2

added noise rejection or to assure adequate attenuation at

the error-amplifier high-order pole and zero frequencies. A

good general rule is to choose f = 10f , but it can be

(2 ⋅ π) ⋅ f ⋅ f

⋅ ( L ⋅ C) ⋅ R ⋅ V

FB (P – P)

0

HF

Output Filter Design

HF

0

higher if desired. Choosing f to be lower than 10f can

HF

0

The output inductors and the output capacitor bank together

to form a low-pass filter responsible for smoothing the

pulsating voltage at the phase nodes. The output filter also

must provide the transient energy until the regulator can

respond. Because it has a low bandwidth compared to the

switching frequency, the output filter limits the system

transient response. The output capacitors must supply or

sink load current while the current in the output inductors

increases or decreases to meet the demand.

cause problems with too much phase shift below the system

bandwidth.

FN9289.6

February 1, 2011

30

ISL6312

In high-speed converters, the output capacitor bank is usually

output-voltage deviation than the leading edge. Equation 46

addresses the leading edge. Normally, the trailing edge

dictates the selection of L because duty cycles are usually

less than 50%. Nevertheless, both inequalities should be

evaluated, and L should be selected based on the lower of

the two results. In each equation, L is the per-channel

inductance, C is the total output capacitance, and N is the

number of active channels.

the most costly (and often the largest) part of the circuit.

Output filter design begins with minimizing the cost of this part

of the circuit. The critical load parameters in choosing the

output capacitors are the maximum size of the load step, ΔI,

the load-current slew rate, di/dt, and the maximum allowable

output-voltage deviation under transient loading, ΔV

.

MAX

Capacitors are characterized according to their capacitance,

ESR, and ESL (equivalent series inductance).

2 ⋅ N ⋅ C ⋅ V

O

(EQ. 45)

---------------------------------

L ≤

⋅ ΔV

– (ΔI ⋅ ESR)

MAX

At the beginning of the load transient, the output capacitors

supply all of the transient current. The output voltage will

initially deviate by an amount approximated by the voltage

drop across the ESL. As the load current increases, the

voltage drop across the ESR increases linearly until the load

current reaches its final value. The capacitors selected must

have sufficiently low ESL and ESR so that the total

2

(

)

ΔI

⋅ N ⋅ C

1.25

(EQ. 46)

⎛ ⎞

– (ΔI ⋅ ESR) ⋅ V – V

IN O

----------------------------

L ≤

⋅ ΔV

MAX

2

⎝

⎠

(

)

ΔI

Switching Frequency

output-voltage deviation is less than the allowable maximum.

Neglecting the contribution of inductor current and regulator

response, the output voltage initially deviates by an amount:

There are a number of variables to consider when choosing

the switching frequency, as there are considerable effects on

the upper MOSFET loss calculation. These effects are

outlined in “MOSFETs” on page 26, and they establish the

upper limit for the switching frequency. The lower limit is

established by the requirement for fast transient response

and small output-voltage ripple as outlined in

di

(EQ. 43)

----

ΔV ≈ ESL ⋅ + ESR ⋅ ΔI

dt

“COMPENSATION WITHOUT LOAD-LINE REGULATION”

on page 30. Choose the lowest switching frequency that

allows the regulator to meet the transient-response

requirements.

The filter capacitor must have sufficiently low ESL and ESR

so that ΔV < ΔV

.

MAX

Most capacitor solutions rely on a mixture of high frequency

capacitors with relatively low capacitance in combination

with bulk capacitors having high capacitance but limited

high-frequency performance. Minimizing the ESL of the

high-frequency capacitors allows them to support the output

voltage as the current increases. Minimizing the ESR of the

bulk capacitors allows them to supply the increased current

with less output voltage deviation.

Switching frequency is determined by the selection of the

frequency-setting resistor, R . Figure 22 and Equation 47

T

are provided to assist in selecting the correct value for R .

T

[

]

10.61 – (1.035 ⋅ log(f ))

(EQ. 47)

S

R

= 10

T

1000

The ESR of the bulk capacitors also creates the majority of

the output-voltage ripple. As the bulk capacitors sink and

source the inductor AC ripple current (see “Interleaving” on

page 10 and Equation 2), a voltage develops across the bulk

capacitor ESR equal to I

(ESR). Thus, once the output

C,PP

capacitors are selected, the maximum allowable ripple

voltage, V , determines the lower limit on the

100

PP(MAX)

inductance.

⎛

⎝

⎞

V

⋅

V

– N ⋅ V

IN

OUT

⎠

(EQ. 44)

L

-------------------------------------------------------------------

≥ ESR ⋅

f

⋅ V ⋅ V

IN PP(MAX)

10

S

100

1k

10k

SWITCHING FREQUENCY (Hz)

Since the capacitors are supplying a decreasing portion of

the load current while the regulator recovers from the

transient, the capacitor voltage becomes slightly depleted.

The output inductors must be capable of assuming the entire

load current before the output voltage decreases more than

FIGURE 22. R vs SWITCHING FREQUENCY

T

Input Capacitor Selection

The input capacitors are responsible for sourcing the AC

component of the input current flowing into the upper

MOSFETs. Their RMS current capacity must be sufficient to

handle the AC component of the current drawn by the upper

MOSFETs which is related to duty cycle and the number of

active phases.

ΔV

. This places an upper limit on inductance.

MAX

Equation 45 gives the upper limit on L for the cases when

the trailing edge of the current transient causes a greater

FN9289.6

February 1, 2011

31

ISL6312

0.3

0.2

0.1

0

0.3

0.2

0.1

0

I

= 0

= 0.25 I

I

= 0.5 I

O

L(P-P)

= 0.75 I

O

I

_(P-P)= 0

L

_(P-P)= 0.5 I

O

_(P-P)= 0.75 I

O

0

0.2

0.4

0.6

0.8

1.0

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V

V

)

O/ IN

DUTY CYCLE (V

V )

O

IN/

FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS CURRENT

vs DUTY CYCLE FOR 4-PHASE CONVERTER

FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS

CURRENT FOR 2-PHASE CONVERTER

For a four-phase design, use Figure 23 to determine the

input-capacitor RMS current requirement set by the duty

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting

cycle, maximum sustained output current (I ), and the ratio

O

of the peak-to-peak inductor current (I _(P-P)) to I . Select a

L

O

bulk capacitor with a ripple current rating which will minimize

the total number of input capacitors required to support the

RMS current calculated.

impedances and parasitic circuit elements. These voltage

spikes can degrade efficiency, radiate noise into the circuit

and lead to device overvoltage stress. Careful component

selection, layout, and placement minimizes these voltage

spikes. Consider, as an example, the turnoff transition of the

upper PWM MOSFET. Prior to turnoff, the upper MOSFET

was carrying channel current. During the turnoff, current

stops flowing in the upper MOSFET and is picked up by the

lower MOSFET. Any inductance in the switched current path

generates a large voltage spike during the switching interval.

Careful component selection, tight layout of the critical

components, and short, wide circuit traces minimize the

magnitude of voltage spikes.

The voltage rating of the capacitors should also be at least

1.25x greater than the maximum input voltage. Figures 24 and

25 provide the same input RMS current information for three-

phase and two-phase designs respectively. Use the same

approach for selecting the bulk capacitor type and number.

0.3

I

_(P-P)= 0

I

_(P-P)= 0.5 I

L

O

I

_(P-P)= 0.25 I

I

_(P-P)= 0.75 I

O

L

O

L

0.2

0.1

0

There are two sets of critical components in a DC/DC

converter using a ISL6312 controller. The power

components are the most critical because they switch large

amounts of energy. Next are small signal components that

connect to sensitive nodes or supply critical bypassing

current and signal coupling.

The power components should be placed first, which include

the MOSFETs, input and output capacitors, and the inductors. It

is important to have a symmetrical layout for each power train,

preferably with the controller located equidistant from each.

Symmetrical layout allows heat to be dissipated equally

across all power trains. Equidistant placement of the controller

to the first three power trains it controls through the integrated

drivers helps keep the gate drive traces equally short,

resulting in equal trace impedances and similar drive

capability of all sets of MOSFETs.

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V

V

)

IN/

O

FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS

CURRENT FOR 3-PHASE CONVERTER

Low capacitance, high-frequency ceramic capacitors are

needed in addition to the input bulk capacitors to suppress

leading and falling edge voltage spikes. The spikes result from

the high current slew rate produced by the upper MOSFET turn

on and off. Select low ESL ceramic capacitors and place one as

close as possible to each upper MOSFET drain to minimize

board parasitics and maximize suppression.

When placing the MOSFETs try to keep the source of the

upper FETs and the drain of the lower FETs as close as

FN9289.6

February 1, 2011

32

ISL6312

thermally possible. Input Bulk capacitors should be placed

Routing UGATE, LGATE, and PHASE Traces

close to the drain of the upper FETs and the source of the lower

FETs. Locate the output inductors and output capacitors

between the MOSFETs and the load. The high-frequency input

and output decoupling capacitors (ceramic) should be placed

as close as practicable to the decoupling target, making use of

the shortest connection paths to any internal planes, such as

vias to GND next or on the capacitor solder pad.

Great attention should be paid to routing the UGATE, LGATE,

and PHASE traces since they drive the power train MOSFETs

using short, high current pulses. It is important to size them as

large and as short as possible to reduce their overall

impedance and inductance. They should be sized to carry at

least one ampere of current (0.02” to 0.05”). Going between

layers with vias should also be avoided, but if so, use two vias

for interconnection when possible.

The critical small components include the bypass capacitors

for VCC and PVCC, and many of the components

surrounding the controller including the feedback network

and current sense components. Locate the VCC/PVCC

bypass capacitors as close to the ISL6312 as possible. It is

especially important to locate the components associated

with the feedback circuit close to their respective controller

pins, since they belong to a high-impedance circuit loop,

sensitive to EMI pick-up.

Extra care should be given to the LGATE traces in particular

since keeping their impedance and inductance low helps to

significantly reduce the possibility of shoot-through. It is also

important to route each channels UGATE and PHASE traces

in as close proximity as possible to reduce their inductances.

Current Sense Component Placement and Trace

Routing

One of the most critical aspects of the ISL6312 regulator

layout is the placement of the inductor DCR current sense

components and traces. The R-C current sense components

must be placed as close to their respective ISEN+ and

ISEN- pins on the ISL6312 as possible.

A multi-layer printed circuit board is recommended. Figure 26

shows the connections of the critical components for the

converter. Note that capacitors C

and C could each

xxIN

xxOUT

represent numerous physical capacitors. Dedicate one solid

layer, usually the one underneath the component side of the

board, for a ground plane and make all critical component

ground connections with vias to this layer. Dedicate another

solid layer as a power plane and break this plane into smaller

islands of common voltage levels. Keep the metal runs from the

PHASE terminal to output inductors short. The power plane

should support the input power and output power nodes. Use

copper filled polygons on the top and bottom circuit layers for

the phase nodes. Use the remaining printed circuit layers for

small signal wiring.

The sense traces that connect the R-C sense components to

each side of the output inductors should be routed on the

bottom of the board, away from the noisy switching

components located on the top of the board. These traces

should be routed side by side, and they should be very thin

traces. It’s important to route these traces as far away from

any other noisy traces or planes as possible. These traces

should pick up as little noise as possible.

Thermal Management

For maximum thermal performance in high current, high

switching frequency applications, connecting the thermal

GND pad of the ISL6312 to the ground plane with multiple

vias is recommended. This heat spreading allows the part to

achieve its full thermal potential. It is also recommended

that the controller be placed in a direct path of airflow if

possible to help thermally manage the part.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9289.6

February 1, 2011

33

ISL6312

C

R

2

FB

LOCATE CLOSE TO IC

(MINIMIZE CONNECTION PATH)

KEY

C

1

HEAVY TRACE ON CIRCUIT PLANE LAYER

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

+12V

R

1

FB

IDROOP

VDIFF

COMP

C

BIN1

C

BOOT1

VSEN

RGND

BOOT1

LOCATE NEAR SWITCHING TRANSISTORS;

(MINIMIZE CONNECTION PATH)

UGATE1

+5V

PHASE1

LGATE1

VCC

OFS

(CF1)

R

1

C

1

R

OFS

ISEN1-

ISEN1+

FS

+12V

REF

R

T

PVCC1_2

C

REF

C

(CF2)

BIN2

C

BOOT2

SS

UGATE2

R

SS

PHASE2

LGATE2

C

(C

)

HFOUT

BOUT

R

C

1

OVPSEL

LOAD

ISEN2-

ISEN2+

ISL6312

+12V

VID7

VID6

VID5

PVCC3

C

(CF2)

BIN3

LOCATE NEAR LOAD;

(MINIMIZE CONNECTION

PATH)

VID4

VID3

VID2

VID1

VID0

C

BOOT3

UGATE3

PHASE3

LGATE3

VRSEL

R

C

1

PGOOD

+12V

ISEN3-

ISEN3+

R

EN1

+12V

EN

C

BIN4

R

EN2

BOOT

VCC

UGATE

EN_PH4

PWM4

PVCC

PHASE

DRSEL

ISL6612

R

DR

R

1

C

1

LGATE

GND

PWM

GND

ISEN4-

ISEN4+

FIGURE 26. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS

FN9289.6

February 1, 2011

34

ISL6312

Package Outline Drawing

L48.7x7

48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 5, 4/10

4X

5.5

7.00

A

44X

6

0.50

B

PIN #1 INDEX AREA

37

48

6

1

36

PIN 1

INDEX AREA

4. 30 ± 0 . 15

12

25

(4X)

0.15

13

24

0.10 M C A B

48X 0 . 40± 0 . 1

TOP VIEW

4

0.23 +0.07 / -0.05

BOTTOM VIEW

SEE DETAIL "X"

C

0.10

0 . 90 ± 0 . 1

BASE PLANE

( 6 . 80 TYP )

4 . 30 )

SEATING PLANE

0.08 C

(

SIDE VIEW

( 44X 0 . 5 )

0 . 2 REF

5

C

( 48X 0 . 23 )

( 48X 0 . 60 )

0 . 00 MIN.

0 . 05 MAX.

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN9289.6

February 1, 2011

35


型号：	ISL6312CRZ-T13
厂家：	RENESAS TECHNOLOGY CORP
描述：	Switching Controller
文件：	总35页 (文件大小：1207K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6312CRZ-T13 [RENESAS]

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