ISL6363IRTZ-T_技术文档

Multiphase PWM Regulator for VR12™ Desktop CPUs

ISL6363

Features

Fully compliant with VR12™ specifications, the ISL6363

provides a complete solution for microprocessor core and

graphics power supplies. It provides two Voltage Regulators

(VRs) with three integrated gate drivers. The first output (VR1)

can be configured as a 4, 3, 2 or 1-phase VR while the second

output (VR2) is a 1-phase VR. The two VRs share a serial control

bus to communicate with the CPU and achieve lower cost and

smaller board area compared with a two-chip approach.

• Serial Data Bus (SVID)

• Dual Outputs:

- Configurable 4, 3, 2 or 1-phase for the 1st Output with 2

Integrated Gate Drivers

- 1-phase for the 2nd Output with Integrated Gate Driver

• Precision Core Voltage Regulation

- 0.5% System Accuracy Over-Temperature

- Enhanced Load Line Accuracy

Based on Intersil’s Robust Ripple Regulator R3 Technology™,

the PWM modulator, compared to traditional modulators, has

faster transient settling time, variable switching frequency

during load transients and has improved light load efficiency

with its ability to automatically change switching frequency.

• PS2 Compensation and High Frequency Load Transient

Compensation

• Differential Remote Voltage Sensing

• Lossless Inductor DCR Current Sensing

The ISL6363 has several other key features. Both outputs

support DCR current sensing with a single NTC thermistor for

DCR temperature compensation or accurate resistor current

sensing. Both outputs come with remote voltage sensing,

• Programmable V

BOOT

Voltage at Start-up

• Resistor Programmable Address, IMAX, TMAX for Both

Outputs

programmable V

voltage, serial bus address, IMAX, TMAX,

BOOT

• Adaptive Body Diode Conduction Time Reduction

adjustable switching frequency, OC protection and separate

power-good indicators. To reduce output capacitors, the

ISL6363 also has an additional compensation function for

PS1/2 mode and high frequency load transient compensation.

Applications

• VR12 Desktop Computers

Related Literature

• ISL6363EVAL1Z User Guide

1.15

1.10

1.7mΩ LOADLINE

V

CORE

50mV/DIV

1.05

1.1V - PS1

1.00

1.1V - PS0

0.95

0.90

COMP

1V/DIV

65A STEP LOAD

1V/DIV

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85

(A)

2µs/DIV

I

OUT

FIGURE 2. ACCURATE LOADLINE, V

vs I

OUT

FIGURE 1. FAST TRANSIENT RESPONSE

CORE

September 5, 2013

FN6898.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) and R3 Technology are trademarks owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

ISL6363

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

TEMP. RANGE

PACKAGE

(Pb-Free)

PKG.

DWG. #

PART MARKING

(°C)

ISL6363CRTZ

ISL6363 CRTZ

ISL6363 IRTZ

0 to +70

-40 to +85

48 Ld 6x6 TQFN

L48.6x6

ISL6363IRTZ

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6363. For more information on MSL please see techbrief TB363.

Pin Configuration

ISL6363

(48 LD TQFN)

TOP VIEW

48 47 46 45 44 43 42 41 40 39 38 37

SCOMP

PGOOD

VCC

PHASEG

UGATEG

BOOTG

LGATEG

PVCCG

VR_HOT#

NTCG

1

2

36

35

34

33

32

31

30

29

28

27

26

25

Temporary Pinout

Subject to Change

3

ISUMP

ISUMN

ISEN1

ISEN2

ISEN3

ISEN4

VSEN

4

5

GND PAD

(BOTTOM)

6

7

ISUMNG

ISUMPG

RTNG

8

9

10

11

12

PSICOMP

RTN

FBG

COMPG

14

13

15 16 17 18 19 20 21 22 23 24

Pin Descriptions

ISL6363

SYMBOL

DESCRIPTION

Bottom

Pad

GND

Common ground signal of the IC. Unless otherwise stated, signals are referenced to the GND pin. The pad should also be

used as the thermal pad for heat dissipation.

1

2

SCOMP

PGOOD

This pin is a placeholder for potential future functionality. This pin can be left floating.

Power-good open-drain output indicating when VR1 is able to supply a regulated voltage. Pull-up externally with a 680Ω

resistor to +5V or 1kΩ to +3.3V.

3

VCC

+5V bias supply pin. Connect a high quality 0.1µF capacitor from this pin to GND and place it as close to the pin as possible.

A small resistor (2.2Ω for example) between the +5V supply and the decoupling capacitor is recommended.

4, 5

ISUMP,

ISUMN

VR1 current sense input pins for current monitoring, droop current and overcurrent detection.

6

7

8

ISEN1

ISEN2

ISEN3

VR1 phase 1 current sense input pin for phase current balancing.

VR1 phase 2 current sense input pin for phase current balancing.

VR1 phase 3 current sense input pin for phase current balancing.

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ISL6363

Pin Descriptions (Continued)

ISL6363

SYMBOL

ISEN4

VSEN

DESCRIPTION

9

VR1 phase 4 current sense input pin for phase current balancing.

VR1 remote core voltage sense input.

10

11

PSICOMP This pin is used for improving transient response in PS2/3 mode of VR1 by switching in an additional type 3 compensation

network to improve system gain and phase margin. Connect a resistor and capacitor from this pin to the output of VR1 near

the feedback compensation network.

12

13

14

RTN

FB

VR1 remote voltage sensing return input. Connect this pin to the remote ground sensing location.

Inverting input of the error amplifier for VR1.

COMP

This is a dual function pin. This pin is the output of the error amplifier for VR1. A resistor connected from this pin to GND

programs IMAX for VR1 and V

for both VR1 and VR2. Refer to Table 7 on page 28.

BOOT

15

16

VW

A resistor from this pin to COMP programs the PWM switching frequency for VR1.

NTC

One of the thermistor network inputs to the thermal monitoring circuit used to control the VR_HOT# signal. Use this pin to

monitor the temperature of VR1. Place the NTC close to the desired thermal detection point on the PCB.

17

18

IMON

Current monitoring output pin for VR1. The current sense signal from ISUMN and ISUMP is output on this pin to generate a

voltage proportional to the output current of VR1.

VR_ON

Enable input signal for the controller. A high level logic signal on this pin enables the controller and initiates soft-start for VR1

and VR2.

19, 20, 21

SDA,

ALERT#,

SCLK

Data, alert and clock signal for the SVID communication bus between the CPU and VR1 and VR2.

22

23

PGOODG

Power-good open-drain output indicating when VR2 is able to supply a regulated voltage. Pull-up externally with a 680Ω

resistor to +5V or 1.0kΩ to 3.3V.

IMONG

Current monitoring output pin for VR2. The current sense signal from ISUMNG and ISUMPG is output on this pin to generate

a voltage proportional to the output current of VR2.

24

25

VWG

A resistor from this pin to COMPG programs the PWM switching frequency for VR1.

COMPG

This is a dual function pin. This pin is the output of the error amplifier for VR2. A resistor connected from this pin to GND

programs IMAX for VR2 and TMAX for both VR1 and VR2. Refer to Table 8 on page 28.

26

27

FBG

Inverting input of the error amplifier for VR2.

RTNG

VR2 remote voltage sensing return input. Connect this pin to the remote ground sensing location.

VR2 current sense input pin for current monitoring, droop current and overcurrent detection.

28, 29

ISUMPG,

ISUMNG

30

NTCG

One of the thermistor network inputs to the thermal monitoring circuit used to control the VR_HOT# signal. Use this pin to

monitor the temperature of VR2. Place the NTC close to the desired thermal detection point on the PCB.

31

32

VR_HOT# Open drain thermal overload output indicator.

PVCCG

Input voltage bias for the internal gate driver for VR2. Connect +12V to this pin. Decouple with at least a 1µF MLCC capacitor

and place it as close to the pin as possible.

33

34

LGATEG

BOOTG

Output of the VR2 low-side MOSFET gate driver. Connect this pin to the gate of the VR2 low-side MOSFET.

Connect a MLCC capacitor from this pin to the PHASEG pin. The boot capacitor is charged through an internal boot diode

connected from the PVCCG pin to the BOOTG pin.

35

36

UGATEG

PHASEG

Output of the VR2 high-side MOSFET gate drive. Connect this pin to the gate of the VR2 high-side MOSFET.

Current return path for the VR2 high-side MOSFET gate driver. Connect this pin to the node connecting the source of the

high-side MOSFET, the drain of the low-side MOSFET and the output inductor of VR2.

37

38

39

PWM4

PWM3

PWM output for phase 4 of VR1. When PWM4 is pulled to +5V VCC, the controller will disable phase 4 of VR1.

PWM output for phase 3 of VR1. When PWM3 is pulled to +5V VCC, the controller will disable phase 3 of VR1.

PHASE2

Current return path for the VR1 phase 2 high-side MOSFET gate driver. Connect this pin to the node connecting the source of

the high-side MOSFET, the drain of the low-side MOSFET and the output inductor of phase 2.

40

UGATE2

Output of the VR1 phase 2 high-side MOSFET gate drive. Connect this pin to the gate of the high-side MOSFET of phase 2.

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ISL6363

Pin Descriptions (Continued)

ISL6363

SYMBOL

DESCRIPTION

41

BOOT2

Connect an MLCC capacitor from this pin to the PHASE2 pin. The boot capacitor is charged through an internal boot diode

connected from the PVCCG pin to the BOOTG pin.

42

43

LGATE2

PVCC

Output of the VR1 phase 2 low-side MOSFET gate driver. Connect this pin to the gate of the low-side MOSFET of phase 2.

Input voltage bias for the internal gate drivers for VR1. Connect +12V to this pin. Decouple with at least a 1µF MLCC capacitor

and place it as close to the pin as possible.

44

45

LGATE1

BOOT1

Output of the VR1 phase 1 low-side MOSFET gate driver. Connect this pin to the gate of the low-side MOSFET of phase 1.

Connect an MLCC capacitor from this pin to the PHASE1 pin. The boot capacitor is charged through an internal boot diode

connected from the PVCC pin to the BOOT1 pin.

46

47

UGATE1

PHASE1

Output of the VR1 phase 1 high-side MOSFET gate drive. Connect this pin to the gate of the high-side MOSFET of phase 1.

Current return path for the VR1 phase 1 high-side MOSFET gate driver. Connect this pin to the node connecting the source of

the high-side MOSFET, the drain of the low-side MOSFET and the output inductor of phase 1.

48

ADDR

A resistor from this pin to GND programs the SVID address for VR1 and VR2. Refer to Table 9 on page 28.

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ISL6363

Block Diagram

VWG

COMPG

+

RTNG

FBG

+

_

Σ

E/A

BOOTG

VR2

MODULATOR

DRIVER

UGATEG

PHASEG

IDROOPG

ISUMPG

ISUMNG

+

_

CURRENT

SENSE

LGATEG

PGOODG

IMONG

OC FAULT

OV FAULT

NTCG

NTC

VCC

T_MONITOR

TEMP

MONITOR

PVCCG

VR_HOT#

IMAX

VBOOT

TMAX

COMPG

COMP

PVCC

ADDR

SET (A/D)

ADDR

SCOMP

PWM4

IMONG

IMON

VR_ON

SDA

A/D

D/A

DAC2

DAC1

DIGITAL

INTERFACE

PWM3

ALERT#

SCLK

MODE2

MODE1

MODE

BOOT2

UGATE2

PHASE2

VREADY

DRIVER

VW

COMP

+

LGATE2

DRIVER

+

VR1

MODULATOR

RTN

+

_

Σ

E/A

FB

PSICOMP

CIRCUIT

BOOT1

PSICOMP

IDROOP

UGATE1

PHASE1

ISUMP

ISUMN

+

_

CURRENT

SENSE

ISEN4

ISEN3

ISEN2

ISEN1

LGATE1

PGOOD

DRIVER

CURRENT

BALANCING

OC FAULT

IBAL FAULT

OV FAULT

VSEN

IMON

GND

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ISL6363

Simplified Application Circuit

Vin +12V

+5V

VCC PVCC PVCCG

Rntcg

BOOTG

NTCG

o

C

LG

UGATEG

GX Vcore

PGOODG

VWG

PHASEG

Rfsetg

LGATEG

Rsumg

Rprog2

ISUMPG

ISUMNG

Rng

COMPG

FBG

o

Cng

Rig

C

Vsumng

Cvsumng

+12V

Vin

+12V

VCC

UGATE

L4

Rdroopg

PVCC

PHASE

VCCSENSEG

VSSSENSEG

ISL6622

RTNG

BOOT

LGATE

GND

PWM4

PWM

IMONG

+12V

IMONG

ISL6363

VCC

L3

L2

L1

UGATE

SDA

ALERT#

SCLK

SDA

ALERT#

SCLK

PVCC

PHASE

ISL6622

BOOT

PWM3

PWM

LGATE

Rscomp

Raddr

GND

SCOMP

ADDR

BOOT2

UGATE2

PHASE2

Rntc

C

CPU Vcore

NTC

o

LGATE2

BOOT1

VR_HOT#

PGOOD

VR_ON

VR_HOT#

PGOOD

VR_ON

Rfset

UGATE1

PHASE1

VW

Rprog1

LGATE1

COMP

Rsum4

ISUMP

Rsum3

Rsum2

Rsum1

Rn

FB

o

Cn

C

PSICOMP

Ri

Vsumn

ISUMN

Cvsumv

Risen4

Cisen1

Cisen2Cisen3Cisen4

Rdroop

VCCSENSE

VSSSENSE

ISEN4

ISEN3

ISEN2

ISEN1

Risen3

Risen2

Risen1

VSEN

RTN

IMON

GND

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ISL6363

Table of Contents

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Gate Driver Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Multiphase R3 Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Start-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Voltage Regulation and Load Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Differential Voltage Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Dynamic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

VR_HOT#/ALERT# Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PSICOMP Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Adaptive Body Diode Conduction Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Supported Data and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Key Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Programming Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

NTC Network on the NTC and the NTCG pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Optional Slew Rate Compensation Circuit for 1-Tick VID Transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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ISL6363

Absolute Maximum Ratings

Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V

Supply Voltage, PVCC, PVCCG . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V

Absolute Boot Voltage (BOOT). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +36V

Phase Voltage (PHASE) . . . . . . . . . . . . . . . . . . -8V (<400ns, 20µJ) to +30V,

Thermal Resistance (Typical)

48 Ld TQFN Package (Notes 4, 5) . . . . . . .

θ

_JA(°C/W)

27

θ

_JC(°C/W)

1

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

(<200ns, V

- VGND < +36V)

BOOT

UGATE Voltage (UGATE) . . . . . . . . . . . . . . . . . . PHASE-0.3V to BOOT + 0.3V

PHASE-3.5V (<100ns Pulse Width, 2µJ) to BOOT + 0.3V

LGATE Voltage. . . . . . . . . . . . -3V (<20ns Pulse Width, 5µJ) to PVCC + 0.3V

-5V (<100ns Pulse Width, 2µJ) to PVCC + 0.3V

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to (VCC + 0.3V)

Open Drain Outputs, PGOOD, VR_HOT#, ALERT#. . . . . . . . . . -0.3V to +7V

ESD Rating

Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . 2500V

Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 250V

Charged Device Model (Tested per JESD22-C101A) . . . . . . . . . . 1000V

Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA

Recommended Operating Conditions

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

PVCC, PVCCG Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V

Ambient Temperature

CRTZ (Commercial) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

IRTZ (Industrial) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Operating Conditions: VCC = 5V, PVCC = 12V, PVCCG = 12V, T = 0°C to +70°C, (Commercial) or

A

-40°C to +85°C (Industrial), f

= 300kHz, unless otherwise noted.

SW

Boldface limits apply over the operating temperature range, 0°C to +70°C (Commercial) or -40°C to +85°C (Industrial).

MIN

MAX

(Note 6) TYP (Note 6) UNITS

PARAMETER

INPUT POWER SUPPLY

SYMBOL

TEST CONDITIONS

+5V Supply Current

I

VR_ON = 1V

VR_ON = 0V

VR_ON = 1V

VR_ON = 0V

VR_ON = 1V

VR_ON = 0V

18

4.1

1

20

5.5

2

mA

V

VCC

PVCC Supply Current

I

PVCC

1

PVCCG Supply Current

VCC Power-On-Reset Threshold

I

1

2

PVCCG

1

POR

V

rising

falling

rising

falling

4.35

4.15

4.35

4.15

4.5

r

CC

4

V

f

PVCC and PVCCG Power-On-Reset

Threshold

PPOR

4.5

V

r

f

PPOR

V

SYSTEM AND REFERENCES

System Accuracy

CRTZ

No load; closed loop, active mode range

VID = 0.75V to 1.52V

-0.5

-8

+0.5

+8

%

VID = 0.5V to 0.745V

VID = 0.25V to 0.495V

mV

-15

+15

IRTZ

No load; closed loop, active mode range

VID = 0.75V to 1.52V

-0.8

-10

-18

+0.8

+10

+18

%

mV

V

VID = 0.5V to 0.745V

VID = 0.25V to 0.495V

Internal V

BOOT

CRTZ

IRTZ

1.0945 1.100 1.1055

1.0912 1.1 1.1088

V

FN6898.1

September 5, 2013

8

ISL6363

Electrical Specifications Operating Conditions: VCC = 5V, PVCC = 12V, PVCCG = 12V, T = 0°C to +70°C, (Commercial) or

A

-40°C to +85°C (Industrial), f

= 300kHz, unless otherwise noted.

SW

Boldface limits apply over the operating temperature range, 0°C to +70°C (Commercial) or -40°C to +85°C (Industrial). (Continued)

MIN

MAX

PARAMETER

Maximum Output Voltage

SYMBOL

TEST CONDITIONS

VID = [11111111]

(Note 6) TYP (Note 6) UNITS

V

1.52

0.25

V

CC_CORE(max)

Minimum Output Voltage

V

VID = [00000001]

CC_CORE(min)

Maximum Output Voltage with Offset

V

Register 33h = 7Fh, VID = FFh

2.155

CC_CORE(max)

+ Offset

CHANNEL FREQUENCY

Nominal Channel Frequency

f

R

= 8.06kΩ, 3-channel operation,

= 1.1V

280

300

320

200

kHz

SW(nom)

fset

V

COMP

Minimum Adjustment Range

Maximum Adjustment Range

AMPLIFIERS

500

Current-Sense Amplifier Input Offset

Error Amp DC Gain

I

= 0A

-0.313

+0.313

mV

dB

FB

A

90

18

v0

Error Amp Gain-Bandwidth Product

ISEN

GBW

C = 20pF

L

MHz

Imbalance Voltage

Maximum of ISENs - Minimum of ISENs

1.1

mV

nA

Input Bias Current

20

POWER-GOOD AND PROTECTION MONITORS

PGOOD Low Voltage

V

I

= 4mA

0.15

0.4

1

V

OL

PGOOD

PGOOD Leakage Current

PGOOD Delay

I

PGOOD = 3.3V

µA

ms

Ω

OH

tpgd

3.8

7

ALERT# Low Resistance

VR_HOT# Low Resistance

ALERT# Leakage Current

VR_HOT# Leakage Current

GATE DRIVE SWITCHING TIME

UGATE Rise Time

13

1

7

Ω

µA

1

t

V

/V

= 12V, 3nF load,

26

ns

RUGATE; PVCC PVCCG

10% to 90%

LGATE Rise Time

t

V

= 12V, 3nF load, 10% to 90%

= 12V, 3nF load, 90% to 10%

18

12

10

ns

RLGATE; PVCC

UGATE Fall Time

V

FUGATE; PVCC

LGATE Fall Time

V

FLGATE; PVCC

UGATE Turn-On Non-Overlap

LGATE Turn-On Non-Overlap

GATE DRIVE RESISTANCE

Upper Drive Source Resistance

Upper Drive Sink Resistance

Lower Drive Source Resistance

Lower Drive Sink Resistance

BOOTSTRAP DIODE

; V

= 12V, 3nF load, adaptive

PDHUGATE PVCC

; V

PDHLGATE PVCC

V

= 12V, 15mA source current

2.0

W

PVCC

= 12V, 15mA sink current

= 12V, 15mA source current

= 12V, 15mA sink current

1.35

0.90

Forward Voltage

V

PVCC = 12V, I = 2mA

0.58

0.2

V

F

Reverse Leakage

I

V

= 25V

R

µA

R

FN6898.1

September 5, 2013

9

ISL6363

Electrical Specifications Operating Conditions: VCC = 5V, PVCC = 12V, PVCCG = 12V, T = 0°C to +70°C, (Commercial) or

A

-40°C to +85°C (Industrial), f

= 300kHz, unless otherwise noted.

SW

Boldface limits apply over the operating temperature range, 0°C to +70°C (Commercial) or -40°C to +85°C (Industrial). (Continued)

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 6) TYP (Note 6) UNITS

PROTECTION

Overvoltage Threshold

OV

VSEN rising above setpoint for >1µs

One ISEN above another ISEN for >1.2ms

4, 3, 2, 1-Phase Configuration PS0 Mode

116

50

232

71

mV

µA

H

Current Imbalance Threshold

VR1 Overcurrent Threshold

9

60

30

4-Phase Configuration, drop to 2-Phase in PS1

Mode

4-Phase Configuration, drop to 1-Phase in PS2/3

Mode

16

50

20

26

µA

3-Phase Configuration, drop to 2-Phase in PS1

3-Phase Configuration, drop to 1-Phase in PS2/3

40

20

30

µA

2-Phase Configuration, drop to 1-phase in

PS1/2/3 Mode

VR2 Overcurrent Threshold

LOGIC THRESHOLDS

All modes of operation

60

71

µA

VR_ON Input Low

V

0.3

V

IL

VR_ON Input High

V

0.7

3.5

IH

PWM

PWM Output Low

V

Sinking 5mA

Sourcing 5mA

PWM = 2.5V

1.0

V

0L

PWM Output High (Note 6)

PWM Tri-State Leakage

V

4.2

2

0H

µA

THERMAL MONITOR

NTC Source Current

NTC = 1.3V

Falling

58

60

63

µA

V

VR_HOT# Trip Voltage (VR1 and VR2)

VR_HOT# Reset Voltage (VR1 and VR2)

Therm_Alert Trip Voltage (VR1 and VR2)

Therm_Alert Reset Voltage (VR1 and VR2)

CURRENT MONITOR

0.86

0.873

0.89

Rising

0.905 0.929 0.935

0.9 0.913 0.93

0.945 0.961 0.975

V

Falling

V

Rising

V

IMON Output Current (VR1 and VR2)

ICCMAX_Alert Trip Voltage (VR1 and VR2)

ICCMAX_ALERT Reset Voltage (VR1 and VR2)

INPUTS

ISUM- pin current = 25µA

147

2.61

150

2.66

2.62

154

µA

V

Rising

Falling

2.695

2.650

2.585

V

VR_ON Leakage Current

I

VR_ON = 0V

-1

0

µA

VR_ON

VR_ON = 1V

18

35

1

SCLK, SDA Leakage

VR_ON = 0V, SCLK and SDA = 0V and 1V

VR_ON = 1V, SCLK and SDA = 1V

VR_ON = 1V, SCLK and SDA = 0V

-1

-5

1

-85

-60

-30

SLEW RATE (For VID Change)

Fast Slew Rate

10

mV/µs

Slow Slew Rate

NOTE:

2.5

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

FN6898.1

September 5, 2013

10

ISL6363

Gate Driver Timing Diagram

PWM

t

LGFUGR

t

FU

t

RU

1V

UGATE

LGATE

1V

t

RL

t

FL

t

UGFLGR

MASTER CLOCK CIRCUIT

VW

Theory of Operation

Multiphase R3 Modulator

MASTER

CLOCK

Clock1

Clock2

Clock3

COMP

Vcrm

MASTER

CLOCK

Phase

Sequencer

The ISL6363 is a multiphase regulator implementing Intel’s™

VR12™ protocol. It has two voltage regulators, VR1 and VR2, on

one chip. VR1 can be programmed for 1, 2, 3, or 4-phase

operation, and VR2 is dedicated for 1-phase operation. The

following description is based on VR1, but also applies to VR2

because the same architecture is implemented.

gmVo

Crm

SLAVE CIRCUIT 1

L1

I_L1

Phase1

Clock1

PWM1

Vo

S

R

VW

Q

Co

Vcrs1

The ISL6363 uses Intersil’s patented R3 (Robust Ripple Regulator)

modulator. The R3 modulator combines the best features of fixed

frequency PWM and hysteretic PWM while eliminating many of

their shortcomings. Figure 3 conceptually shows the multiphase

R3 modulator circuit, and Figure 4 shows the operation principles.

gm

Crs1

Crs2

Crs3

SLAVE CIRCUIT 2

L2

I_L2

Phase2

PWM2

Clock2

S

R

VW

Q

A current source flows from the VW pin to the COMP pin, creating

a voltage window set by the resistor between the two pins. This

voltage window is called VW window in the following discussion.

Vcrs2

gm

Inside the IC, the modulator uses the master clock circuit to

generate the clocks for the slave circuits. The modulator

SLAVE CIRCUIT 3

L3

I_L3

Phase3

PWM3

Clock3

S

R

VW

Q

discharges the ripple capacitor C with a current source equal to

rm

g V , where g is a gain factor. C voltage V

m o rm crm

is a sawtooth

m

waveform traversing between the VW and COMP voltages. It resets

to VW when it hits COMP, and generates a one-shot master clock

signal. A phase sequencer distributes the master clock signal to

the slave circuits. If VR1 is in 4-phase mode, the master clock

signal will be distributed to the four phases, and the Clock1~4

signals will be 90° out-of-phase. If VR1 is in 3-phase mode, the

master clock signal will be distributed to the three phases, and the

Clock1~3 signals will be 120° out-of-phase. If VR1 is in 2-phase

mode, the master clock signal will be distributed to Phases 1 and 2,

and the Clock1 and Clock2 signals will be 180° out-of-phase. If

VR1 is in 1-phase mode, the master clock signal will be distributed

to Phase 1 only and be the Clock1 signal.

Vcrs3

gm

FIGURE 3. R3 MODULATOR CIRCUIT

Each slave circuit has its own ripple capacitor C , whose voltage

rs

mimics the inductor ripple current. A g amplifier converts the

inductor voltage into a current source to charge and discharge

C . The slave circuit turns on its PWM pulse upon receiving the

m

rs

clock signal, and the current source charges C . When C

rs rs

voltage V hits VW, the slave circuit turns off the PWM pulse,

Crs

and the current source discharges C .

rs

FN6898.1

September 5, 2013

11

ISL6363

VW

Hysteretic

Window

Vcrm

COMP

Vcrm

Master

Clock

Master

Clock

Clock1

PWM1

Clock1

PWM1

Clock2

PWM2

Clock2

PWM2

Clock3

PWM3

Clock3

PWM3

VW

Vcrs1

Vcrs3

Vcrs2

Vcrs2 Vcrs3 Vcrs1

FIGURE 4. R3 MODULATOR OPERATION PRINCIPLES IN STEADY

STATE

FIGURE 5. R3 MODULATOR OPERATION PRINCIPLES IN LOAD

INSERTION RESPONSE

Diode Emulation and Period Stretching of the ISL6363 can

operate in diode emulation (DE) mode to improve light load

efficiency. In DE mode, the low-side MOSFET conducts when the

current is flowing from source to drain and does not allow reverse

current, emulating a diode. As Figure 6 shows, when LGATE is on,

the low-side MOSFET carries current, creating negative voltage on

the phase node due to the voltage drop across the ON-resistance.

The ISL6363 monitors the current through monitoring the phase

node voltage. It turns off LGATE when the phase node voltage

reaches zero to prevent the inductor current from reversing the

direction and creating unnecessary power loss.

Since the controller works with V , which are large-amplitude

crs

and noise-free synthesized signals, it achieves lower phase jitter

than conventional hysteretic mode and fixed PWM mode

controllers. Unlike conventional hysteretic mode converters, the

ISL6363 uses an error amplifier that allows the controller to

maintain a 0.5% output voltage accuracy.

Figure 5 shows the operation principles during load insertion

response. The COMP voltage rises during load insertion,

generating the master clock signal more quickly, so the PWM

pulses turn on earlier, increasing the effective switching frequency,

which allows for higher control loop bandwidth than conventional

fixed frequency PWM controllers. The VW voltage rises as the

COMP voltage rises, making the PWM pulses wider. During load

release response, the COMP voltage falls. It takes the master clock

circuit longer to generate the next master clock signal so the PWM

pulse is held off until needed. The VW voltage falls as the COMP

voltage falls, reducing the current PWM pulse width. This kind of

behavior gives the ISL6363 excellent response speed.

P H A S E

U G A TE

LG A TE

The fact that all the phases share the same VW window voltage

also ensures excellent dynamic current balance among phases.

IL

FIGURE 6. DIODE EMULATION

If the load current is light enough, as Figure 6 shows, the inductor

current will reach and stay at zero before the next phase node

pulse, and the regulator is in discontinuous conduction mode

(DCM). If the load current is heavy enough, the inductor current

will never reach 0A, and the regulator is in CCM although the

controller is in DE mode.

FN6898.1

September 5, 2013

12

ISL6363

Figure 7 shows the operation principle in diode emulation mode at

Voltage Regulation and Load Line

Implementation

After the start sequence, the ISL6363 regulates the output voltage

to the value set by the VID information per Table 1. The ISL6363

will control the no-load output voltage to an accuracy of ±0.5%

over the range of 0.75V to 1.52V. A differential amplifier allows

voltage sensing for precise voltage regulation at the

microprocessor die.

light load. The load gets incrementally lighter in the three cases

from top to bottom. The PWM on-time is determined by the VW

window size, therefore is the same, making the inductor current

triangle the same in the three cases. The ISL6363 clamps the

ripple capacitor voltage V in DE mode to make it mimic the

crs

inductor current. It takes the COMP voltage longer to hit V

,

crs

naturally stretching the switching period. The inductor current

triangles move further apart from each other such that the

inductor current average value is equal to the load current. The

reduced switching frequency helps increase light load efficiency.

TABLE 1. VID TABLE

VID

CCM/DCM BOUNDARY

VW

7

0

6

0

5

0

1

4

0

1

0

3

0

1

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

HEX

V (V)

O

0

1

2

0

1

2

3

4

5

6

7

8

9

0.00000

0.25000

0.25500

0.26000

0.26500

0.27000

0.27500

0.28000

0.28500

0.29000

0.29500

0.30000

0.30500

0.31000

0.31500

0.32000

0.32500

0.33000

0.33500

0.34000

0.34500

0.35000

0.35500

0.36000

0.36500

0.37000

0.37500

0.38000

0.38500

0.39000

0.39500

0.40000

0.40500

Vcrs

iL

LIGHT DCM

VW

Vcrs

iL

DEEP DCM

VW

Vcrs

iL

A

B

C

D

E

F

FIGURE 7. PERIOD STRETCHING

Start-up Timing

With the controller's V voltage above the POR threshold, the

CC

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

start-up sequence begins when VR_ON exceeds the logic high

threshold. Figure 8 shows the typical start-up timing of VR1 and

VR2. The ISL6363 uses digital soft-start to ramp-up DAC to the

voltage programmed by the SetVID command. PGOOD is asserted

high and ALERT# is asserted low at the end of the ramp-up.

Similar results occur if VR_ON is tied to VCC, with the soft-start

sequence starting 800µs after VCC crosses the POR threshold.

VCC

SLEW RATE

VID

VR_ON

2.5mV/µs

VID COMMAND

VOLTAGE

3.8ms

DAC

PGOOD

ALERT#

…...

FIGURE 8. VR1 SOFT-START WAVEFORMS

0

FN6898.1

September 5, 2013

13

ISL6363

TABLE 1. VID TABLE (Continued)

VID

TABLE 1. VID TABLE (Continued)

VID

7

0

6

0

1

5

1

0

4

0

1

0

3

0

1

0

1

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

HEX

V

(V)

7

0

6

1

5

0

1

4

0

1

0

1

3

1

0

1

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

HEX

V (V)

O

2

3

4

1

2

3

4

5

6

7

8

9

A

B

C

0.41000

0.41500

0.42000

0.42500

0.43000

0.43500

0.44000

0.44500

0.45000

0.45500

0.46000

0.46500

0.47000

0.47500

0.48000

0.48500

0.49000

0.49500

0.50000

0.50500

0.51000

0.51500

0.52000

0.52500

0.53000

0.53500

0.54000

0.54500

0.55000

0.55500

0.56000

0.56500

0.57000

0.57500

0.58000

0.58500

0.59000

0.59500

0.60000

0.60500

4

5

6

7

9

0.61000

0.61500

0.62000

0.62500

0.63000

0.63500

0.64000

0.64500

0.65000

0.65500

0.66000

0.66500

0.67000

0.67500

0.68000

0.68500

0.69000

0.69500

0.70000

0.70500

0.71000

0.71500

0.72000

0.72500

0.73000

0.73500

0.74000

0.74500

0.75000

0.75500

0.76000

0.76500

0.77000

0.77500

0.78000

0.78500

0.79000

0.79500

0.80000

0.80500

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

0

FN6898.1

September 5, 2013

14

ISL6363

TABLE 1. VID TABLE (Continued)

VID

TABLE 1. VID TABLE (Continued)

VID

7

0

1

6

1

0

5

1

0

4

1

0

1

3

0

1

0

1

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

HEX

V

(V)

7

1

6

0

1

5

0

1

0

4

1

0

1

0

3

1

0

1

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

HEX

V (V)

O

7

8

9

1

2

3

4

5

6

7

8

9

A

B

C

0.81000

0.81500

0.82000

0.82500

0.83000

0.83500

0.84000

0.84500

0.85000

0.85500

0.86000

0.86500

0.87000

0.87500

0.88000

0.88500

0.89000

0.89500

0.90000

0.90500

0.91000

0.91500

0.92000

0.92500

0.93000

0.93500

0.94000

0.94500

0.95000

0.95500

0.96000

0.96500

0.97000

0.97500

0.98000

0.98500

0.99000

0.99500

1.00000

1.00500

9

A

B

C

9

1.01000

1.01500

1.02000

1.02500

1.03000

1.03500

1.04000

1.04500

1.05000

1.05500

1.06000

1.06500

1.07000

1.07500

1.08000

1.08500

1.09000

1.09500

1.10000

1.10500

1.11000

1.11500

1.12000

1.12500

1.13000

1.13500

1.14000

1.14500

1.15000

1.15500

1.16000

1.16500

1.17000

1.17500

1.18000

1.18500

1.19000

1.19500

1.20000

1.20500

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

0

FN6898.1

September 5, 2013

15

ISL6363

TABLE 1. VID TABLE (Continued)

VID

TABLE 1. VID TABLE (Continued)

VID

7

1

6

1

5

0

1

4

0

1

0

3

0

1

0

1

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

HEX

V

(V)

7

1

6

1

5

1

4

0

1

3

1

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

HEX

V (V)

O

C

D

E

1

2

3

4

5

6

7

8

9

A

B

C

1.21000

1.21500

1.22000

1.22500

1.23000

1.23500

1.24000

1.24500

1.25000

1.25500

1.26000

1.26500

1.27000

1.27500

1.28000

1.28500

1.29000

1.29500

1.30000

1.30500

1.31000

1.31500

1.32000

1.32500

1.33000

1.33500

1.34000

1.34500

1.35000

1.35500

1.36000

1.36500

1.37000

1.37500

1.38000

1.38500

1.39000

1.39500

1.40000

1.40500

E

F

9

1.41000

1.41500

1.42000

1.42500

1.43000

1.43500

1.44000

1.44500

1.45000

1.45500

1.46000

1.46500

1.47000

1.47500

1.48000

1.48500

1.49000

1.49500

1.50000

1.50500

1.51000

1.51500

1.52000

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

As the load current increases from zero, the output voltage will

droop from the VID table value by an amount proportional to the

load current to achieve the load line. The ISL6363 can sense the

inductor current through the intrinsic DC Resistance (DCR) of the

inductors as shown in Figure 16 or through resistors in series

with the inductors as shown in Figure 22. In both methods,

capacitor C voltage represents the inductor total currents. A

droop amplifier converts C voltage into an internal current

source with the gain set by resistor R . The current source is used

for load line implementation, current monitor and overcurrent

protection.

n

i

0

1

2

3

4

5

6

7

8

Figure 9 shows the load line implementation. The ISL6363 drives

a current source I

E

out of the FB pin, described by Equation 1.

droop

E

2xV

Cn

(EQ. 1)

----------------

I

=

droop

E

R

i

E

When using inductor DCR current sensing, a single NTC element

is used to compensate the positive temperature coefficient of the

copper winding, thus sustaining the load line accuracy with

reduced cost.

E

FN6898.1

September 5, 2013

16

ISL6363

eliminate the effect of phase node parasitic PCB DCR.

Equations 5 through 7 give the ISEN pin voltages:

Rdroop

Vdroop

(EQ. 5)

(EQ. 6)

(EQ. 7)

V

= (R

+ R

) × I

VCC_SENSE

ISEN1

ISEN2

ISEN3

dcr1

dcr2

dcr3

pcb1

pcb2

pcb3

L1

L2

L3

FB

VR LOCAL VO

“CATCH”

RESISTOR

Idroop

E/A

VID

Where R

, R

and R

are inductor DCR; R

, R

pcb1 pcb2

dcr1 dcr2

dcr3

COMP

DAC

X 1

Σ

VDAC

and R

are parasitic PCB DCR between the inductor output

pcb3

RTN

VSS

side pad and the output voltage rail; and I , I and I are

inductor average currents.

L1 L2

L3

VSS_SENSE

INTERNAL

TO IC

L3

L2

L1

Rdcr3

Rpcb3

“CATCH”

RESISTOR

Phase3

Risen

ISEN3

IL3

IL2

IL1

FIGURE 9. DIFFERENTIAL SENSING AND LOAD LINE

IMPLEMENTATION

Cisen

Rdcr2

Rdcr1

Rpcb2

Rpcb1

V

o

INTERNAL

TO IC

Phase2

Risen

ISEN2

I

flows through resistor R

droop

and creates a voltage drop as

(EQ. 2)

droop

shown in Equation 2.

Cisen

V

= R

× I

droop droop

droop

Phase1

Risen

ISEN1

V

is the droop voltage required to implement load line.

droop

Changing R

Cisen

or scaling I

can both change the load line

also sets the overcurrent protection level, it is

droop

slope. Since I

droop

FIGURE 10. CURRENT BALANCING CIRCUIT

recommended to first scale I

then select an appropriate R

load line slope.

based on OCP requirement,

value to obtain the desired

droop

The ISL6363 will adjust the phase pulse-width relative to the

other phases to make V = V = V , thus, to achieve

ISEN1

ISEN2 ISEN3

I

R

= I = I , when there are R

= R

and

L1 L2 L3 dcr1

dcr2 dcr3

Differential Voltage Sensing

= R

= R .

pcb1

pcb2

pcb3

Figure 9 also shows the differential voltage sensing scheme.

Using the same components for L1, L2 and L3 will provide a good

match of R , R and R . Board layout will determine

VCC

and VSS are the remote voltage sensing signals

SENSE

dcr1 dcr2 dcr3

from the processor die. A unity gain differential amplifier senses

the VSS voltage and add it to the DAC output. The error

R

, R

and R

. It is recommended to have symmetrical

pcb1 pcb2

pcb3

layout for the power delivery path between each inductor and the

SENSE

amplifier regulates the inverting and the non-inverting input

voltages to be equal as shown in Equation 3:

output voltage rail, such that R

= R

= R .

pcb1

pcb2

pcb3

L3

Rdcr3

Rpcb3

Rpcb2

Rpcb1

V3p

(EQ. 3)

(EQ. 4)

VCC

+ V

= V

+ VSS

DAC SENSE

SENSE

Phase3

Risen

ISEN3

droop

IL3

V3n

Rewriting Equation 3 and substitution of Equation 2 gives

Risen

Cisen

VCC

– VSS

= V

– R

× I

droop droop

Risen

SENSE

DAC

INTERNAL

TO IC

L2

Rdcr2

V

o

V2p

Equation 4 is the exact equation required for load line

implementation.

Phase2

Risen

IL2

ISEN2

Cisen

V2n

The VCC

SENSE

and VSS signals come from the processor die.

SENSE

The feedback will be open circuit in the absence of the processor. As

Figure 9 shows, it is recommended to add a “catch” resistor to feed

the VR local output voltage back to the compensator, and add

another “catch” resistor to connect the VR local output ground to the

RTN pin. These resistors, typically 10Ω~100Ω, will provide voltage

feedback if the system is powered up without a processor installed.

L1

Rdcr1

V1p

Phase1

Risen

IL1

ISEN1

Cisen

V1n

Phase Current Balancing

FIGURE 11. DIFFERENTIAL-SENSING CURRENT BALANCING CIRCUIT

The ISL6363 monitors individual phase average current by

monitoring the ISEN1, ISEN2, ISEN3, and ISEN4 voltages.

Figure 10 shows the current balancing circuit recommended for

ISL6363 for a 3-Phase configuration as an example. Each phase

Sometimes it is difficult to implement symmetrical layout. For

the circuit shown in Figure 10, asymmetric layout causes

different R

, R

and R , thus current imbalance.

pcb1 pcb2

pcb3

Figure 11 shows a differential-sensing current balancing circuit

recommended for the ISL6363. The current sensing traces

should be routed to the inductor pads so they only pick up the

inductor DCR voltage. Each ISEN pin sees the average voltage of

node voltage is averaged by a low-pass filter consisting of R

isen

and C

, and presented to the corresponding ISEN pin. R

isen

should be routed to the inductor phase-node pad in order to

FN6898.1

September 5, 2013

17

ISL6363

three sources: its own phase inductor phase-node pad, and the

other two phases inductor output side pads. Equations 8 thru 10

give the ISEN pin voltages:

REP RATE = 10kHz

V

= V + V + V

1p 2n 3n

(EQ. 8)

ISEN1

V

= V + V + V

1n 2p

(EQ. 9)

ISEN2

ISEN3

3n

3p

= V + V + V

(EQ. 10)

1n

2n

The ISL6363 will make V

Equations 11 and 12:

= V

= V as shown in

ISEN3

ISEN1

ISEN2

V

+ V + V

= V + V + V

(EQ. 11)

(EQ. 12)

1p

2n

3n

1n 2p

3n

3p

REP RATE = 25kHz

V

+ V + V

= V + V + V

1n 2n

1n

2p

3n

Rewriting Equation 11 gives Equation 13:

V

– V

= V – V

(EQ. 13)

(EQ. 14)

1p

1n 2p 2n

and rewriting Equation 12 gives Equation 14:

V

– V

= V – V

2p

2n 3p 3n

Combining Equations 13 and 14 gives:

V

– V

= V – V

3n

(EQ. 15)

(EQ. 16)

1p

1n

2p

2n

3p

Therefore:

R

REP RATE = 50kHz

× I

= R

× I

= R

× I

dcr3 L3

dcr1

L1

dcr2

L2

Current balancing (I = I = I ) will be achieved when there is

L1 L2 L3

R

= R

. R , R

and R

will not have any

dcr1

effect.

dcr2

dcr3 pcb1 pcb2

pcb3

Since the slave ripple capacitor voltages mimic the inductor

currents, the R3 modulator can naturally achieve excellent

current balancing during steady state and dynamic operations.

Figure 12 shows current balancing performance of the

evaluation board with a load transient of 12A/51A at different

rep rates. The inductor currents follow the load current dynamic

change with the output capacitors supplying the difference. The

inductor currents can track the load current well at low rep rate,

but cannot keep up when the rep rate gets into the hundred-kHz

range, where it’s out of the control loop bandwidth. The controller

achieves excellent current balancing in all cases installed.

REP RATE = 100kHz

CCM SWITCHING FREQUENCY

The R

resistor between the COMP and the VW pins sets the

fset

VW windows size, therefore sets the switching frequency. When

the ISL6363 is in continuous conduction mode (CCM), the

switching frequency is not absolutely constant due to the nature

of the R3 modulator. As explained in the Multiphase R3

REP RATE = 200kHz

Modulator section on page 11, the effective switching frequency

will increase during load insertion and will decrease during load

release to achieve fast response. On the other hand, the

switching frequency is relatively constant at steady state.

Variation is expected when the power stage condition, such as

input voltage, output voltage, load, etc., changes. The variation is

usually less than 15% and doesn’t have any significant effect on

output voltage ripple magnitude. Equation 17 gives an estimate

of the frequency-setting resistor R

value. 8kΩ R gives

fset

approximately 300kHz switching frequency. Lower resistance

gives higher switching frequency.

FIGURE 12. CURRENT BALANCING DURING DYNAMIC OPERATION.

CH1: IL1, CH2: I

, CH3: IL2, CH4: IL3

LOAD

(EQ. 17)

R

(kΩ) = (Period(μs) – 0.29) × 2.65

fset

FN6898.1

September 5, 2013

18

ISL6363

Table 3 shows VR2 operational modes, programmed by the PS

command. VR2 operates in 1-phase CCM in PS0 and PS1, and

enters 1-phase DE mode in PS2 and PS3 mode.

Modes of Operation

TABLE 2. VR1 MODES OF OPERATION

OCP

THRESHOLD

(µA)

VR2 can be disabled completely by tying ISUMNG to 5V, and all

communication to VR2 will be blocked.

PWM4 PWM3 ISEN2

CONFIG. PS

MODE

4-PH CCM

2-PH CCM

1-PH DE

To Ext To Ext ToPower 4-phase

Driver Driver Stage

0

1

2

3

0

1

2

3

0

1

2

3

0

1

2

3

60

30

20

Dynamic Operation

CPU VR

Config.

VR1 and VR2 behave the same during dynamic operation. The

controller responds to VID changes by slewing to the new voltage

at a slew rate indicated in the SetVID command. There are three

SetVID slew rates, namely SetVID_fast, SetVID_slow and

SetVID_decay.

Tie to

5V VCC

3-phase

CPU VR

Config.

3-PH CCM

2-PH CCM

1-PH DE

60

40

20

SetVID_fast command prompts the controller to enter CCM and

to actively drive the output voltage to the new VID value at a

minimum 10mV/µs slew rate.

SetVID_slow command prompts the controller to enter CCM and

to actively drive the output voltage to the new VID value at a

minimum 2.5mV/µs slew rate.

Tie to

5V VCC

2-phase

CPU VR

Config.

2-PH CCM

1-PH DE

60

30

SetVID_decay command prompts the controller to enter DE

mode. The output voltage will decay down to the new VID value at

a slew rate determined by the load. If the voltage decay rate is

too fast, the controller will limit the voltage slew rate at

SetVID_slow slew rate.

Tie to 5V 1-phase

VCC

1-PH CCM

1-PH DE

60

CPU VR

Config.

ALERT# will be asserted low at the end of SetVID_fast and

SetVID_slow VID transitions.

VR1 can be configured for 4, 3, 2 or 1-phase operation. Table 2

shows VR1 configurations and operational modes, programmed

by the PWM4, PWM3 pins and the ISEN2 pin status, and the PS

command. For 3-phase configuration, tie the PWM4 pin to 5V. In

this configuration, phases 1, 2 and 3 are active. For 2-phase

configuration, tie the PWM4 and PWM3 pin to 5V. In this

configuration, phases 1 and 2 are active. For 1-phase

S e tV ID _ d e c a y

S e tV ID _ fa s t/s lo w

V _O

V ID

t3

configuration, tie the PWM4, PWM3 and the ISEN2 pin to 5V. In

this configuration, only phase 1 is active.

T _ a le rt

t1

t2

A L E R T #

In 4-phase configuration, VR1 operates in 4-phase CCM in PS0

mode. It enters 2-phase CCM operation in PS1 mode. It enters

1-phase DE operation in PS2 and PS3 modes.

FIGURE 13. SETVID DECAY PRE-EMPTIVE BEHAVIOR

In 3-phase configuration, VR1 operates in 3-phase CCM in PS0

mode. It enters 2-phase CCM operation in PS1 mode. It enters

1-phase DE operation in PS2 and PS3 modes.

Figure 13 shows SetVID Decay Pre-Emptive behavior. The

controller receives a SetVID_decay command at t1. The VR

enters DE mode and the output voltage V decays down slowly.

O

In 2-phase configuration, VR1 operates in 2-phase CCM in PS0

and PS1 mode. It enters 1-phase DE mode in PS2 and PS3

modes.

At t2, before V reaches the intended VID target of the

O

SetVID_decay command, the controller receives a SetVID_fast (or

SetVID_slow) command to go to a voltage higher than the actual

V . The controller will turn around immediately and slew V to

the new target voltage at the slew rate specified by the SetVID

O

In 1-phase configuration, VR1 operates in 1-phase CCM in PS0

and PS1, and enters 1-phase DE mode in PS2 and PS3.

command. At t3, V reaches the new target voltage and the

O

TABLE 3. VR2 MODES OF OPERATION

controller asserts the ALERT# signal.

PS

0

MODE

1-phase CCM

OCP THRESHOLD

60µA

The R3 modulator intrinsically has voltage feed-forward. The

output voltage is insensitive to a fast slew rate input voltage

change.

1

2

1-phase DE

3

FN6898.1

September 5, 2013

19

ISL6363

5. The CPU reads Status_1 register value to know that the alert

VR_HOT#/ALERT# Behavior

assertion is due to TZONE register bit 6 flipping.

VR Temperature

6. The controller clears ALERT#.

3% Hysteresis

10

Temp Zone

Bit 7 =1

1111 1111

0111 1111

0011 1111

0001 1111

7

7. The temperature continues rising.

1

Bit 6 =1

8. The temperature crosses the threshold where the TZONE

register Bit 7 changes from 0 to 1.

Bit 5 =1

12

9. The controller asserts the VR_HOT# signal. The CPU throttles

back and the system temperature starts dropping eventually.

Temp Zone

Register

2

8

10. The temperature crosses the threshold where the TZONE

register bit 6 changes from 1 to 0. This threshold is 1 ADC step

lower than the one when VR_HOT# gets asserted, to provide

3% hysteresis.

0001 1111 0011 1111 0111 1111

Status 1

Register = “001”

1111 1111

0111 1111

0011 1111

0001 1111

3

= “011”

= “001”

13

15

16

5

GerReg

Status1

GerReg

Status1

SVID

11. The controllers de-assert the VR_HOT# signal.

12. The temperature crosses the threshold where the TZONE

register bit 5 changes from 1 to 0. This threshold is 1 ADC step

lower than the one when ALERT# gets asserted during the

temperature rise to provide 3% hysteresis.

ALERT#

6

4

14

VR_HOT#

9

11

FIGURE 14. VR_HOT#/ALERT# BEHAVIOR

13. The controller changes Status_1 register bit 1 from 1 to 0.

14. The controller asserts ALERT#.

The controller drives 60µA current source out of the NTC pin and

the NTCG pin alternatively at 1kHz frequency with 50% duty

cycle. The current source flows through the respective NTC

resistor networks on the pins and creates voltages that are

monitored by the controller through an A/D converter (ADC) to

generate the TZONE value. Table 4 shows the programming table

for TZONE. The user needs to scale the NTC and the NTCG

network resistance such that it generates the NTC (and NTCG) pin

voltage that corresponds to the left-most column. Do not use any

capacitor to filter the voltage.

15. The CPU reads Status_1 register value to know that the alert

assertion is due to TZONE register bit 5 flipping.

16. The controller clears ALERT#.

Protection Functions

VR1 and VR2 both provide overcurrent, current-balance and

overvoltage fault protections. The controller also provides

over-temperature protection. The following discussion is based on

VR1 and also applies to VR2.

TABLE 4. TZONE TABLE

The controller determines overcurrent protection (OCP) by

comparing the average value of the droop current I

with an

VNTC (V)

0.84

0.88

0.92

0.96

1.00

1.04

1.08

1.12

1.16

1.2

TMAX (%)

>100

100

97

TZONE

FFh

droop

internal current source threshold as Table 2 shows. It declares

OCP when I is above the threshold for 120µs.

droop

FFh

For overcurrent conditions above 1.5x the OCP level, the PWM

outputs will immediately shut off and PGOOD will go low to

maximize protection. This protection is also referred to as

way-overcurrent protection or fast-overcurrent protection, for

short-circuit protections.

7Fh

3Fh

1Fh

0Fh

07h

03h

01h

00h

94

91

88

The controller monitors the ISEN pin voltages to determine

current-balance protection. If the ISEN pin voltage difference is

greater than 9mV for 1ms, the controller will declare a fault and

latch off.

85

82

79

76

The controller takes the same actions for all of the above fault

protections: de-assertion of PGOOD and turn-off of the high-side

and low-side power MOSFETs. Any residual inductor current will

decay through the MOSFET body diodes.

>1.2

<76

Figure 14 shows how the NTC and the NTCG network should be

designed to get correct VR_HOT#/ALERT# behavior when the

system temperature rises and falls, manifested as the NTC and the

NTCG pin voltage falls and rises. The series of events are:

The controller will declare an overvoltage fault and de-assert PGOOD

if the output voltage exceeds the VID set value by +200mV. The

ISL6363 will immediately declare an OV fault, de-assert PGOOD,

and turn on the low-side power MOSFETs. The low-side power

MOSFETs remain on until the output voltage is pulled down below

the VID set value when all power MOSFETs are turned off. If the

output voltage rises above the VID set value +200mV again, the

protection process is repeated. This behavior provides the

maximum amount of protection against shorted high-side power

MOSFETs while preventing output ringing below ground.

1. The temperature rises so the NTC pin (or the NTCG pin)

voltage drops. TZONE value changes accordingly.

2. The temperature crosses the threshold where the TZONE

register Bit 6 changes from 0 to 1.

3. The controller changes Status_1 register bit 1 from 0 to 1.

4. The controller asserts ALERT#.

FN6898.1

September 5, 2013

20

ISL6363

All the above fault conditions can be reset by bringing VR_ON low

or by bringing VCC below the POR threshold. When VR_ON and

VCC return to their high operating levels, a soft-start will occur

C1

R2

CONTROLLER IN

PS0/1 MODE

CONTROLLER IN

PS2/3 MODE

C3.1

C2

R3

C2

R3

Table 5 summarizes the fault protections.

FB

R1

VSEN

TABLE 5. FAULT PROTECTION SUMMARY

FAULT DURATION

VSEN

COMP

E/A

C2.2

R3.2

COMP

BEFORE

PROTECTION

FAULT

RESET

PSICOMP

FAULT TYPE

Overcurrent

PROTECTION ACTION

FIGURE 15. PSICOMP FUNCTION

120µs

1ms

PWM tri-state, PGOOD VR_ON

latched low

toggle or

VCC toggle

When the PSICOMP switch is off, C2.2 and R3.2 are

Phase Current

Unbalance

disconnected from the FB pin. However, the controller still

actively drives the PSICOMP pin to allow for smooth transitions

between modes of operation.

Way-Overcurrent

(1.5xOC)

Immediately

The PSICOMP function ensures excellent transient response in

both PS0, PS1 and PS2/3 modes of operation. If the PSICOMP

function is not needed C2.2 and R3.2 can be disconnected.

Overvoltage

+200mV

PGOOD latched low.

Actively pulls the

output voltage to

below VID value, then

tri-state.

Adaptive Body Diode Conduction Time

Reduction

In DCM, the controller turns off the low-side MOSFET when the

inductor current approaches zero. During on-time of the low-side

MOSFET, phase voltage is negative and the amount is the

CURRENT MONITOR

The ISL6363 provides the current monitor function for both VRs.

IMON pin reports VR1 inductor current and IMONG pins reports

VR2 inductor current. Since they are designed following the same

principle, the following discussion will be only based on the IMON

pin but also applies to the IMONG pin.

MOSFET r

voltage drop, which is proportional to the

DS(ON)

inductor current. A phase comparator inside the controller

monitors the phase voltage during on-time of the low-side

MOSFET and compares it with a threshold to determine the

zero-crossing point of the inductor current. If the inductor current

has not reached zero when the low-side MOSFET turns off, it will

flow through the low-side MOSFET body diode, causing the phase

node to have a larger voltage drop until it decays to zero. If the

inductor current has crossed zero and reversed the direction when

the low-side MOSFET turns off, it will flow through the high-side

MOSFET body diode, causing the phase node to have a spike until

it decays to zero. The controller continues monitoring the phase

voltage after turning off the low-side MOSFET and adjusts the

phase comparator threshold voltage accordingly in iterative steps,

such that the low-side MOSFET body diode conducts for

The IMON pin outputs a high-speed analog current source that is

3 times of the droop current flowing out of the FB pin. Thus

becoming Equation 18:

I

= 3 × I

(EQ. 18)

IMON

droop

As the “Simplified Application Circuit” on page 6 shows, a

resistor R is connected to the IMON pin to convert the IMON

imon

pin current to voltage. A capacitor can be paralleled with R

to filter the voltage information.

imon

The IMON pin voltage range is 0V to 2.7V. The controller monitors

the IMON pin voltage and considers that VR1 has reached

ICCMAX on IMON pin voltage is 2.7V.

approximately 40ns to minimize the body diode-related loss.

Supported Data and Configuration Registers

The controller supports the following data and configuration

registers.

PSICOMP Function

Figure 15 shows the PSICOMP function. A switch turns on to

short the FB and the PSICOMP pins when the controller is in PS2

mode. The RC network C2.2 and R3.2 is connected in parallel

with R1 and C2/R3 compensation network in PS2/3 mode. This

additional RC network increases the high frequency content of

the signal passing from the output voltage to the COMP pin which

will improve transient response in PS2/3 mode of operation.

TABLE 6. SUPPORTED DATA AND CONFIGURATION

REGISTERS

REGISTER

NAME

DEFAULT

VALUE

INDEX

00h

DESCRIPTION

Vendor ID

Uniquely identifies the VR

vendor. Assigned by Intel.

12h

01h

02h

05h

Product ID

Uniquely identifies the VR

product. Intersil assigns this

number.

1Fh

Product

Revision

Uniquely identifies the revision

of the VR control IC. Intersil

assigns this data.

Protocol ID

Identifies what revision of SVID 01h

protocol the controller supports.

FN6898.1

September 5, 2013

21

ISL6363

TABLE 6. SUPPORTED DATA AND CONFIGURATION

REGISTERS (Continued)

TABLE 6. SUPPORTED DATA AND CONFIGURATION

REGISTERS (Continued)

REGISTER

NAME

DEFAULT

VALUE

REGISTER

NAME

DEFAULT

VALUE

INDEX

06h

DESCRIPTION

INDEX

31h

DESCRIPTION

Capability

Identifies the SVID VR

capabilities and which of the

optional telemetry registers are

supported.

81h

VID Setting

Data register containing

currently programmed VID

voltage. VID data format.

00h

32h

33h

Power State

Register containing the current 00h

programmed power state.

10h

Status_1

Data register read after ALERT# 00h

signal. Indicating if a VR rail has

settled, has reached VRHOT

condition or has reached ICC

max.

Voltage Offset Sets offset in VID steps added to 00h

the VID setting for voltage

margining. Bit 7 is a sign bit,

0 = positive margin,

11h

12h

Status_2

Data register showing status_2 00h

communication.

1 = negativemargin.Remaining

7 bits are # VID steps for the

margin.

00h = no margin,

01h = +1 VID step

Temperature Data register showing

Zone

00h

temperature zones that have

been entered.

02h = +2 VID steps

1Ch

21h

Status_2_

LastRead

This register contains a copy of 00h

the Status_2 data that was last

read with the GetReg (Status_2)

command.

34h

Multi VR Config Data register that configures

multiple VRs behavior on the

same SVID bus.

VR1: 00h

VR2: 01h

ICC max

Data register containing the ICC Refer to

max the platform supports, set Table 7

at start-up by resistors Rprog1

and Rprog2. The platform

Key Component Selection

Inductor DCR Current-Sensing Network

design engineer programs this

value during the design process.

Binary format in amps, i.e.,

Phase1 Phase2 Phase3

Rsum

100A = 64h

ISUM+

Rsum

22h

Temp max

Data register containing the

Refer to

temperature max the platform Table 8

support, set at startup by

resistor Rprog2. The platform

design engineer programs this

value during the design process.

Binary format in °C, i.e.,

Rntcs

L

Cn Vcn

Ri

Rp

Rntc

Ro

DCR

+100°C = 64h

ISUM-

24h

SR-fast

SR-slow

Slew Rate Normal. The fastest 0Ah

slew rate the platform VR can

sustain. Binary format in

Ro

mV/µs. i.e., 0Ah = 10mV/µs.

25h

26h

Is 4x slower than normal. Binary 02h

format in mV/µs. i.e.,

02h = 2.5mV/µs

Io

FIGURE 16. DCR CURRENT-SENSING NETWORK

V

If programmed by the platform, 00h

Figure 16 shows the inductor DCR current-sensing network for a

3-phase solution. An inductor current flows through the DCR and

creates a voltage drop. Each inductor has two resistors in R

and R connected to the pads to accurately sense the inductor

current by sensing the DCR voltage drop. The R

BOOT

the VR supports V

voltage

BOOT

during start-up ramp. The VR will

ramp to V and hold at

sum

BOOT

until it receives a new

o

V

BOOT

and R

sum

o

SetVID command to move to a

different voltage.

resistors are connected in a summing network as shown, and feed

the total current information to the NTC network (consisting of

30h

Vout max

This register is programmed by FBh

the master and sets the

maximum VID the VR will

support. If a higher VID code is

received, the VR will respond

with “not supported”

R

, R and R ) and capacitor C . R is a negative

ntcs ntc ntc

p

n

temperature coefficient (NTC) thermistor, used to

temperature-compensate the inductor DCR change.

The inductor output side pads are electrically shorted in the

schematic, but have some parasitic impedance in actual board

layout, which is why one cannot simply short them together for the

acknowledge.

FN6898.1

September 5, 2013

22

ISL6363

current-sensing summing network. It is recommended to use

1Ω~10Ω R to create quality signals. Since R value is much

smaller than the rest of the current sensing circuit, the following

and solving for the solution, Equation 24 gives Cn value.

o

L

-----------------------------------------------------------

C

=

(EQ. 24)

n

R

sum

--------------

R

×

analysis will ignore it for simplicity.

ntcnet

N

-----------------------------------------

× DCR

R

sum

The summed inductor current information is presented to the

--------------

R

+

ntcnet

N

capacitor C . Equations 19 thru 23 describe the

n

frequency-domain relationship between inductor total current

For example, given N = 3, R

= 3.65kΩ, R = 11kΩ,

p

sum

= 2.61kΩ, R = 10kΩ, DCR = 0.88mΩ and L = 0.36µH,

I (s) and C voltage V (s):

o

n

Cn

R

ntcs

ntc

Equation 24 gives C = 0.406µF.

n

⎛

⎜

⎝

⎞

⎟

⎠

R

DCR

----------------------------------------- -----------

ntcnet

V

(s) =

×

× I (s) × A (s)

Assuming the compensator design is correct, Figure 17 shows the

expected load transient response waveforms if C is correctly

(EQ. 19)

Cn

o

cs

R

N

sum

N

--------------

+

R

n

ntcnet

selected. When the load current I

output voltage V

CORE

has a square change, the

also has a square response.

core

(R

+ R ) × R

ntc p

ntcs

--------------------------------------------------

R

A

=

(EQ. 20)

(EQ. 21)

ntcnet

R

+ R

ntc p

ntcs

If C value is too large or too small, V (s) will not accurately

Cn

n

represent real-time I (s) and will worsen the transient response.

o

s

------

1 +

Figure 18 shows the load transient response when C is too

n

ω

L

----------------------

1 +

(s) =

small. V

will sag excessively upon load insertion and may

cs

CORE

s

------------

create a system failure. Figure 19 shows the transient response

when C is too large. V is sluggish in drooping to its final

ω

sns

n

CORE

DCR

-----------

=

value. There will be excessive overshoot if load insertion occurs

during this time, which may potentially hurt the CPU reliability.

ω

(EQ. 22)

(EQ. 23)

L

1

------------------------------------------------------

=

sns

R

sum

N

I

O

--------------

R

×

ntcnet

-----------------------------------------

× C

n

R

sum

N

--------------

R

+

ntcnet

Where N is the number of phases.

V

O

Transfer function A (s) always has unity gain at DC. The inductor

cs

DCR value increases as the winding temperature increases,

giving higher reading of the inductor DC current. The NTC R

FIGURE 17. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS

ntc

values decreases as its temperature decreases. Proper

selections of R

, R

, R and R parameters ensure that

sum ntcs

p

ntc

V

represent the inductor total DC current over the temperature

I

Cn

O

range of interest.

There are many sets of parameters that can properly

temperature-compensate the DCR change. Since the NTC network

and the R

resistors form a voltage divider, V is always a

sum

cn

V

O

fraction of the inductor DCR voltage. It is recommended to have a

higher ratio of V to the inductor DCR voltage, so the droop circuit

cn

has higher signal level to work with.

FIGURE 18. LOAD TRANSIENT RESPONSE WHEN C IS TOO SMALL

n

A typical set of parameters that provide good temperature

compensation are: R

= 3.65kΩ, R = 11kΩ, R

= 2.61kΩ and

= 10kΩ (ERT-J1VR103J). The NTC network parameters may

sum

p

ntcs

R

ntc

I

O

need to be fine tuned on actual boards. One can apply full load DC

current and record the output voltage reading immediately; then

record the output voltage reading again when the board has

reached the thermal steady state. A good NTC network can limit the

output voltage drift to within 2mV. It is recommended to follow the

Intersil evaluation board layout and current-sensing network

parameters to minimize engineering time.

V

O

FIGURE 19. LOAD TRANSIENT RESPONSE WHEN C IS TOO LARGE

n

V

(s) also needs to represent real-time I (s) for the controller to

Cn

o

achieve good transient response. Transfer function A (s) has a

cs

pole w

and a zero w . One needs to match w and w so

sns

L

A

(s) is unity gain at all frequencies. By forcing w equal to w

cs

L

sns

FN6898.1

September 5, 2013

23

ISL6363

R

and C form an R-C branch in parallel with R , providing a

ip

lower impedance path than R at the beginning of i change. R

ip

i

I

O

i

o

I

L

and C do not have any effect at steady state. Through proper

ip

selection of R and C values, i

ip ip droop

can resemble i rather than

o

i , and V will not ring back. The recommended value for R is

L

O

ip

100Ω. C should be determined through tuning the load

transient response waveforms on an actual board. The

ip

V

O

recommended range for C is 100pF~2000pF. However, it

ip

RING

BACK

should be noted that the R -C branch may distort the i

ip ip

droop

waveform. Instead of being triangular as the real inductor

current, i may have sharp spikes, which may adversely

droop

average value detection and therefore may affect

FIGURE 20. OUTPUT VOLTAGE RING BACK PROBLEM

affect i

droop

OCP accuracy. User discretion is advised.

ISUM+

Resistor Current-Sensing Network

Phase1 Phase2 Phase3

Rntcs

Cn.1

Vcn

Cn.2

Rp

L

Rn

Rntc

ISUM-

Ri

OPTIONAL

DCR

Rsum

Cip

Rip

ISUM+

ISUM-

OPTIONAL

Rsen

Vcn

Cn

Ri

Ro

FIGURE 21. OPTIONAL CIRCUITS FOR RING BACK REDUCTION

Figure 20 shows the output voltage ring back problem during

load transient response. The load current i has a fast step

o

change, but the inductor current I cannot accurately follow.

L

Instead, I responds in first order system fashion due to the

nature of current loop. The ESR and ESL effect of the output

L

Io

capacitors makes the output voltage V dip quickly upon load

O

FIGURE 22. RESISTOR CURRENT-SENSING NETWORK

current change. However, the controller regulates V according to

O

the droop current I

, which is a real-time representation of I ;

Figure 22 shows the resistor current-sensing network for a

2-phase solution. Each inductor has a series current-sensing

droop

L

therefore it pulls V back to the level dictated by I , causing the

O

L

ring back problem. This phenomenon is not observed when the

output capacitor have very low ESR and ESL, such as all ceramic

capacitors.

resistor R . R

and R are connected to the R pads to

sen sum

o

sen

accurately capture the inductor current information. The R

sum

and R resistors are connected to capacitor C . R

and C

n

o

n

sum

form a filter for noise attenuation. Equations 25 thru 27 give

Figure 21 shows two optional circuits for reduction of the ring

back.

V

(s) expression

Cn

R

sen

N

(EQ. 25)

(EQ. 26)

C is the capacitor used to match the inductor time constant. It

n

usually takes the parallel of two (or more) capacitors to get the

------------

V

(s) =

× I (s) × A

(s)

Rsen

Cn

o

desired value. Figure 21 shows that two capacitors C and C

n.1 n.2

1

----------------------

1 +

A

(s) =

Rsen

are in parallel. Resistor R is an optional component to reduce

s

n

------------

the V ring back. At steady state, C + C provides the desired

ω

O

n.1 n.2

sns

C capacitance. At the beginning of i change, the effective

n

o

1

capacitance is less because R increases the impedance of the

n

---------------------------

ω

=

(EQ. 27)

Rsen

R

C

branch. As Figure 18 explains, V tends to dip when C is too

sum

n.1

small, and this effect will reduce the V ring back. This effect is

O n

O

--------------

× C

n

N

more pronounced when C is much larger than C . It is also

n.1 n.2

Transfer function A

(s) always has unity gain at DC.

Rsen

Current-sensing resistor R

more pronounced when R is bigger. However, the presence of

n

value will not have significant

sen

R increases the ripple of the V signal if C is too small. It is

n

n.2

variation over-temperature, so there is no need for the NTC

network.

recommended to keep C greater than 2200pF. R value

n.2

n

usually is a few ohms. C , C and R values should be

n.1 n.2

n

determined through tuning the load transient response

waveforms on an actual board.

The recommended values are R

sum

= 1kΩ and C = 5600pF.

n

FN6898.1

September 5, 2013

24

ISL6363

LOAD LINE SLOPE

Overcurrent Protection

Refer to Equation 1 on page 16 and Figures 16, 20 and 22;

Refer to Figure 9.

resistor R sets the droop current I

. Tables 2 (page 19)

i

droop

and 3 (page 19) show the internal OCP threshold. It is

recommended to design I without using the R

For inductor DCR sensing, substitution of Equation 29 into

Equation 2 gives the load line slope expression:

resistor.

droop

comp

For example, the OCP threshold is 60µA for 3-phase solution. We

will design I to be 40.9µA at full load, so the OCP trip level is

V

2R

R

ntcnet

DCR

---------------------- ----------------------------------------- -----------

droop

R

-----------------

LL =

=

×

(EQ. 36)

I

R

sum

N

o

i

--------------

+

R

droop

ntcnet

N

1.5x of the full load current.

For resistor sensing, substitution of Equation 33 into Equation 2

gives the load line slope expression:

For inductor DCR sensing, Equation 28 gives the DC relationship

of V (s) and I (s).

cn

o

V

2R

× R

sen droop

droop

(EQ. 37)

⎛

⎜

⎝

⎞

⎟

⎠

-----------------

-----------------------------------------

=

LL =

R

I

N × R

DCR

N

ntcnet

o

i

----------------------------------------- -----------

V

=

×

× I

Cn

o

(EQ. 28)

R

sum

--------------

R

+

Substitution of Equation 30 and rewriting Equation 36, or

substitution of Equation 34 and rewriting Equation 37 give the

same result in Equation 38:

ntcnet

N

Substitution of Equation 28 into Equation 1 gives Equation 29:

R

I

2

DCR

N

ntcnet

o

---- ----------------------------------------- -----------

× I

o

I

=

×

---------------

(EQ. 29)

R =

droop

× LL

(EQ. 38)

droop

R

I

i

sum

droop

--------------

+

R

ntcnet

N

One can use the full load condition to calculate R

droop

. For

Therefore:

example, given I

= 51A, I

= 40.9µA and

= 2.37kΩ.

omax

LL = 1.9mΩ, Equation 38 gives R

droopmax

2R

× DCR × I

o

ntcnet

droop

-------------------------------------------------------------------------------

R

=

(EQ. 30)

i

R

sum

N

⎛

⎝

⎞

⎠

--------------

It is recommended to start with the R

value calculated by

N ×

R

+

× I

droop

ntcnet

droop

Equation 38, and fine tune it on the actual board to get accurate

load line slope. One should record the output voltage readings at

no load and at full load for load line slope calculation. Reading

the output voltage at lighter load instead of full load will increase

the measurement error.

Substitution of Equation 20 and application of the OCP condition

in Equation 30 gives Equation 31:

(R

+ R ) × R

ntc p

ntcs

--------------------------------------------------

2 ×

× DCR × I

omax

R

+ R

ntc p

ntcs

-------------------------------------------------------------------------------------------------------------------------

=

R

(EQ. 31)

i

Compensator

Figure 17 shows the desired load transient response waveforms.

Figure 23 shows the equivalent circuit of a voltage regulator (VR)

with the droop function. A VR is equivalent to a voltage source

(R

+ R ) × R

R

⎛

⎜

⎝

⎞

⎟

⎠

ntcs

ntc

p

sum

N

-------------------------------------------------- --------------

N ×

+

× I

droopmax

is the

droopmax

R

+ R

p

ntcs

ntc

Where I

is the full load current, I

omax

corresponding droop current. For example, given N = 3,

(= VID) and output impedance Z (s). If Z (s) is equal to the

out out

R

= 3.65kΩ, R = 11kΩ, R

= 2.61kΩ, R = 10kΩ,

= 40.9µA,

droopmax

load line slope LL, i.e., constant output impedance, in the entire

frequency range, V will have square response when I has a

sum

DCR = 0.88mΩ, I

p

ntcs ntc

= 51A and I

omax

O

o

Equation 31 gives R = 606Ω.

square change.

i

For resistor sensing, Equation 32 gives the DC relationship of

I

Z_out(s) = LL

O

V

(s) and I (s).

cn

o

R

sen

------------

(EQ. 32)

V

=

× I

Cn

o

N

VR

V

VID

LOAD

O

Substitution of Equation 32 into Equation 1 gives Equation 33:

R

2

sen

N

---- ------------

× I

o

I

=

×

(EQ. 33)

droop

R

i

FIGURE 23. VOLTAGE REGULATOR EQUIVALENT CIRCUIT

Therefore

2R

× I

sen

o

(EQ. 34)

---------------------------

=

R

Intersil provides a Microsoft Excel-based spreadsheet to help

design the compensator and the current sensing network, so the

VR achieves constant output impedance as a stable system.

Figure 26 shows a screenshot of the spreadsheet.

i

N × I

droop

Substitution of Equation 34 and application of the OCP condition

in Equation 30 gives Equation 35:

2R

× I

sen

omax

A VR with an active droop function is a dual-loop system consisting

of a voltage loop and a droop loop which is a current loop.

However, neither loop alone is sufficient to describe the entire

system. The spreadsheet shows two loop gain transfer functions,

T1(s) and T2(s), that describe the entire system. Figure 24

conceptually shows T1(s) measurement set-up and Figure 25

--------------------------------------

=

R

(EQ. 35)

i

N × I

droopmax

Where I

omax

is the full load current, I

droopmax

is the corresponding

droop current. For example, given N = 3, R = 1mΩ, I

and I

droopmax

= 53A

sen omax

= 40.9µA, Equation 35 gives R = 863Ω.

i

FN6898.1

September 5, 2013

25

ISL6363

conceptually shows T2(s) measurement set-up. The VR senses the

T1(s) is the total loop gain of the voltage loop and the droop loop.

It always has a higher crossover frequency than T2(s) and has

more meaning of system stability.

inductor current, multiplies it by a gain of the load line slope, then

adds it on top of the sensed output voltage and feeds it to the

compensator. T(1) is measured after the summing node, and T2(s)

is measured in the voltage loop before the summing node. The

spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s)

can be actually measured on an ISL6363 regulator.

T2(s) is the voltage loop gain with closed droop loop. It has more

meaning of output voltage response.

Design the compensator to get stable T1(s) and T2(s) with

sufficient phase margin, and output impedance equal or smaller

than the load line slope.

V

L

V

L

O

Q1

I

Q2

V

GATE

DRIVER

I

C

O

V

GATE Q2

DRIVER

C

IN

O

out

IN

OUT

LOAD LINE SLOPE

EA

20

EA

MOD.

COMP

VID

ISOLATION

TRANSFORMER

CHANNEL B

CHANNEL A

CHANNEL B

LOOP GAIN =

CHANNEL A

NETWORK

ANALYZER

CHANNEL B

CHANNEL A

NETWORK

ANALYZER

CHANNEL B

EXCITATION OUTPUT

FIGURE 24. LOOP GAIN T1(s) MEASUREMENT SET-UP

FIGURE 25. LOOP GAIN T2(s) MEASUREMENT SET-UP

FN6898.1

September 5, 2013

26

ISL6363

Programming Resistors

There are three programming resistors: R

TABLE 8. RPROG2 PROGRAMMING TABLE

RPROG2 (kΩ) IMAX_GR (A)

, R

and

prog1 prog2

TMAX (°C)

120

110

105

95

R

. Table 7 shows how to select R

based on V

or an

value. When the controller

and

addr prog1

BOOT

IMAX_CR register settings. VR1 can power to 0V V

BOOT

7.15

13.0

30

25

20

25

30

35

30

25

20

25

30

35

internally-set V

BOOT

based on R

prog1

works with an actual CPU, select R

such that VR1 powers up

= 0V as required by the SVID command. In the absence

prog1

to V

BOOT

20.5

of a CPU, such as testing of the only the VR, select R

that VR1 powers up to the internally-set V

is 1.1V. Determine the maximum current VR1 can support and

set the IMAX_CR register value accordingly by selecting the

such

prog1

, which by default

27.4

BOOT

38.3

52.3

appropriate R

value. The CPU will read the IMAX_CR register

prog1

and ensures that the CPU CORE current doesn’t exceed the value

specified by IMAX_CR.

66.5

80.6

Table 8 shows how to select R

prog2

based on TMAX and

95.3

IMAX_GR register settings. There are four TMAX temperatures to

choose from: +120°C, +110°C, +105°C, and +95°C. There are

also four IMAX_GR values to choose from: 35A, 30A, 25A and

20A.

113

137

165

TABLE 7. RPROG1 PROGRAMMING TABLE

196

95

IMAX

CORE

IMAX

CORE

IMAX

CORE

IMAX

CORE

226

95

RPROG1

(kΩ)

BOOT

(V)

Nph = 4 (A) Nph = 3 (A) Nph = 2 (A) Nph = 1 (A)

Open Circuit

95

7.15

13.0

20.5

27.4

38.3

52.3

66.5

80.6

95.3

113

137

165

196

226

1.1

0

100

108

116

124

132

140

148

140

132

124

116

108

100

92

75

81

50

54

58

62

66

70

74

70

66

62

58

54

50

46

25

27

29

31

33

35

37

35

33

31

29

27

25

23

Table 9 shows how to select R

prog2

based on TMAX and

IMAX_GR register settings. There are four TMAX temperatures to

choose from: +120°C, +110°C, +105°C, and +95°C. There are

also four IMAX_GR values to choose from: 35A, 30A, 25A and

20A.

87

93

99

TABLE 9. RADDR PROGRAMMING TABLE

105

111

105

99

RADDR

(kΩ)

0

VR1 AND VR1 SVID ADDRESS

0,1

2,3

4,5

6,7

8,9

A,B

C,D

0,1

0

7.15

13

0

93

20.5

27.4

38.3

52.3

66.5

80.6

95.3

113

0

87

0

81

0

75

Open

Circuit

0

69

137

165

196

226

Open Circuit

FN6898.1

September 5, 2013

28

ISL6363

For example, given LL = 1.9mΩ, R

= 2.825kΩ,

NTC Network on the NTC and the NTCG pins

droop

= 53A, Equation 42 gives

omax

V

= 2.7V at I

Rimon

The controller drives 60µA current source out of the NTC pin and

the NTCG pin alternatively at 1kHz frequency with 50% duty

cycle. The current source flows through the respective NTC

resistor networks on the pins and creates voltages that are

monitored by the controller through an A/D converter to generate

the TZONE value. Table 10 shows the programming table for

TZONE. The user needs to scale the NTC (and NTCG) network

resistance such that it generates the NTC (and NTCG) pin voltage

that corresponds to the left-most column. Do not use any

capacitor to filter the voltage. On ADC Output = 7, the controller

issues thermal alert to the CPU, on ADC Output <7, the controller

asserts the VR_HOT# signal.

R

= 25.2kΩ.

imon

A capacitor C

imon

pin voltage. The R

is recommended to have a time constant long enough such that

switching frequency ripples are removed.

can be paralleled with R

to filter the IMON

time constant is the user’s choice. It

imon

C

imon imon

Current Balancing

The ISL6363 achieves current balancing through matching the

ISEN pin voltages. R

switching ripple of the phase node voltages. It is recommended

to use a rather long R time constant such that the ISEN

and C form filters to remove the

isen

C

isen isen

voltages have minimal ripple and represent the DC current

flowing through the inductors. Recommended values are

TABLE 10. TZONE PROGRAMMING TABLE

VNTC (V)

0.64

0.68

0.72

0.76

0.80

0.84

0.88

0.92

0.96

1.00

1.04

1.08

1.12

1.16

1.2

ADC OUTPUT

%TMAX

>100%

100%

97%

TZONE

FFh

7Fh

3Fh

1Fh

0Fh

07h

03h

01h

00h

R = 10kΩ and C = 0.22µF.

s

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Optional Slew Rate Compensation Circuit for

1-Tick VID Transition

Rdroop

Vcore

Cvid

Rvid

OPTIONAL

FB

Ivid

Idroop_vid

94%

91%

E/A

VIDs

88%

COMP

VID<0:6>

DAC

Σ _VDAC

85%

RTN

VSS

VSSSENSE

82%

X 1

79%

INTERNAL

TO IC

76%

>1.2

<76%

VID<0:6>

Current Monitor

Vfb

Ivid

Refer to Equation 18 for the IMON pin current expression.

Referencing the “Simplified Application Circuit” on page 6, the

IMON pin current flows through R . The voltage across R is

imon imon

expressed in Equation 39:

(EQ. 39)

V

= 3 × I

× R

droop imon

Rimon

Vcore

Rewriting Equation 38 gives Equation 40:

I

o

------------------

I

=

× LL

Idroop_vid

(EQ. 40)

droop

R

droop

Substitution of Equation 40 into Equation 39 gives Equation 41:

FIGURE 27. OPTIONAL SLEW RATE COMPENSATION CIRCUIT FOR

1-TICK VID TRANSITION

3I × LL

o

--------------------

V

=

× R

(EQ. 41)

Rimon

imon

R

droop

During a large VID transition, the DAC steps through the VIDs at a

controlled slew rate. For example, the DAC may change a tick

Rewriting Equation 41 and application of full load condition gives

Equation 42:

(5mV) per 0.5µs, controlling output voltage V

10mV/µs.

slew rate at

CORE

V

× R

droop

Rimon

--------------------------------------------

=

R

(EQ. 42)

imon

3I × LL

o

FN6898.1

September 5, 2013

29

ISL6363

Figure 27 shows the waveforms of 1-tick VID transition. During

1-tick VID transition, the DAC output changes at approximately

15mV/µs slew rate, but the DAC cannot step through multiple

VIDs to control the slew rate. Instead, the control loop response

It is desired to let I (t) cancel I

(t). So there are:

vid

droop_vid

dV

C

× LL dV

core

fb

out

(EQ. 45)

-----------

----------------------- -----------------

×

C

×

=

vid

dt

R

dt

droop

speed determines V

FB pin voltage slew rate. However, the controller senses the

inductor current increase during the up transition, as the

slew rate. Ideally, V will follow the

CORE

and:

(EQ. 46)

(EQ. 47)

R

× C

= C × LL

out

vid

I

V

waveform shows, and will droop the output voltage

droop_vid

CORE

The result is expressed in Equation 47:

accordingly, making V

slew rate slow. Similar

CORE

behavior occurs during the down transition.

R

= R

vid

droop

To control V

CORE

slew rate during 1-tick VID transition, one can

and:

add the R -C branch, whose current I cancels I

.

dV

vid vid vid

droop_vid

core

-----------------

C

× LL

dt

out

When V

CORE

increases, the time domain expression of the

(EQ. 48)

----------------------- -----------------

C

=

×

vid

R

dV

fb

droop

induced I

change is:

droop

-----------

dt

–t

-------------------------

out

⎛

⎜

⎝

⎞

⎟

⎠

C

× LL dV

C

× LL

out

core

(EQ. 43)

----------------------- -----------------

I

(t) =

×

1 – e

For example: given LL = 1.9mΩ, R

C

= 2.37kΩ,

droop

R

dt

droop

= 1320µF, dV

/dt = 10mV/µs and dV /dt = 15mV/µs,

out

CORE

fb

Equation 47 gives R = 2.37kΩ and Equation 48 gives

vid

Where C

is the total output capacitance.

out

C

= 700pF.

vid

In the mean time, the R -C branch current I time domain

expression is:

vid vid vid

It is recommended to select the calculated R value and start

vid

with the calculated C value and tweak it on the actual board to

vid

–t

------------------------------

vid

get the best performance.

⎛

⎜

⎝

⎞

⎟

⎠

dV

R

× C

vid

fb

(EQ. 44)

-----------

I

(t) = C

×

vid

×

1 – e

vid

During normal transient response, the FB pin voltage is held

constant, therefore is virtual ground in small signal sense. The

dt

R

- C network is between the virtual ground and the real

vid vid

ground, and hence has no effect on transient response.

FN6898.1

September 5, 2013

30

ISL6363

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not guaranteed. Please go to web to make

sure you have the latest Rev.

DATE

REVISION

FN6898.1

CHANGE

September 5, 2013

Stamped Not Recommend For New Designs No Recommended Replacement.

Changed Products information verbiage to About Intersil verbiage.

Updated Copyright on page 1 from Americas Inc to Americas LLC

September 29, 2011

FN6898.0

Initial Release.

About Intersil

Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management

semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal

computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting

www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at

http://www.intersil.com/en/support/qualandreliability.html#reliability

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6898.1

September 5, 2013

31

ISL6363

Package Outline Drawing

L48.6x6

48 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 4/07

4X

4.4

6.00

0.40

44X

A

6

B

PIN #1 INDEX AREA

48

37

6

1

36

PIN 1

INDEX AREA

4 .40 ± 0.15

25

12

0.15

(4X)

13

24

0.10 M C A B

0.05 M C

TOP VIEW

48X 0.45 ± 0.10

BOTTOM VIEW

4

48X 0.20

SEE DETAIL "X"

C

0.10

C

MAX 0.80

BASE PLANE

SEATING PLANE

0.08

( 44 X 0 . 40 )

( 5. 75 TYP )

(

C

SIDE VIEW

4. 40 )

5

0 . 2 REF

C

( 48X 0 . 20 )

( 48X 0 . 65 )

0 . 00 MIN.

0 . 05 MAX.

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN6898.1

September 5, 2013

32


型号：	ISL6363IRTZ-T
厂家：	RENESAS TECHNOLOGY CORP
描述：	Multiphase PWM Regulator for VR12 Desktop CPUs, TQFN, /Reel 开关
文件：	总32页 (文件大小：948K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6363IRTZ-T [RENESAS]

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