ISL6540CRZA-T [RENESAS]
SWITCHING CONTROLLER, 2000kHz SWITCHING FREQ-MAX, PQCC28, 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHD-1, QFN-28;
| 型号： | ISL6540CRZA-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SWITCHING CONTROLLER, 2000kHz SWITCHING FREQ-MAX, PQCC28, 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHD-1, QFN-28 开关 |
| 文件： | 总20页 (文件大小：422K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6540
®
heet
July 23, 2008
FN9214.1
Single-Phase Buck PWM Controller with
Integrated High Speed MOSFET Driver
and Pre-Biased Load Capability
Features
• VIN and Power Rail Operation from +3.3V to +20V
• Fast Transient Response - 0 to 100% Duty Cycle
- 15MHz Bandwidth Error Amplifier with 6V/μs Slew Rate
- Voltage-Mode PWM Leading and Trailing-edge
Modulation Control
The ISL6540 is a single-phase voltage-mode PWM controller
with input voltage feedforward compensation to maintain a
constant loop gain for optimal transient response, especially for
applications with a wide input voltage range. Its integrated high
speed synchronous rectified MOSFET drivers and other
sophisticated features provide complete control and protection
for a DC/DC converter with minimum external components,
resulting in minimum cost and less engineering design efforts.
- Input Voltage Feedforward Compensation
• 2.9V to 5.6V High Speed 2A/4A MOSFET Gate Drivers
- Tri-state for Power Stage Shutdown
• Internal Linear Regulator (LR) - 5.6V Bias from VIN
• External LR Drive for Optimal Thermal Performance
• Voltage Margining with Independently Adjustable Upper and
Lower Settings for System Stress Testing & Over Clocking
The output voltage of the converter can be precisely regulated
with an internal reference voltage of 0.591V, and has a system
tolerance of ±0.85% over commercial temperature and line load
variations. An external voltage can be used in place of the
internal reference for voltage tracking/DDR applications.
• Reference Voltage I/O for DDR/Tracking Applications
• Precise 0.591V Internal Reference with Buffered Output
- ±0.85%/±1.25% Over Commercial/Industrial Range
• Source and Sink Overcurrent Protections
The ISL6540 has an internal linear regulator or external linear
regulator drive options for applications with only a single supply
rail. The internal oscillator is adjustable from 250kHz to 2MHz.
The integrated voltage margining, programmable pre-biased
soft-start, differential remote sensing amplifier, and
programmable input voltage POR features enhance the
ISL6540 value.
- Low- and High-Side MOSFET r
Sensing
DS(ON)
• Overvoltage and Undervoltage Protections
• Small Converter Size - QFN package
• Oscillator Programmable from 250kHz to 2MHz
• Differential Remote Voltage Sensing with Unity Gain
• Programmable Soft-start with Pre-Biased Load Capability
• Power Good Indication with Programmable Delay
• EN Input with Voltage Monitoring Capability
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ISL6540
(28 LD 5x5 QFN)
TOP VIEW
Applications
• Power Supply for some Microprocessors and GPUs
• Wide and Narrow Input Voltage Range Buck Regulators
• Point of Load Applications
28 27 26 25 24 23 22
VSEN+
1
2
3
4
5
6
7
21 BOOT
20 UGATE
19 PHASE
• Low-Voltage and High Current Distributed Power Supplies
VSEN-
REFOUT
REFIN
SS
Ordering Information
GND
PART
PGND
LGATE
PVCC
18
17
16
15
BOTTOM
SIDE PAD
NUMBER*
(Note)
PART
TEMP.
PACKAGE PKG.
MARKING RANGE (°C) (Pb-Free) DWG. #
ISL6540CRZ
ISL6540CRZ
0 to 70
0 to 70
28 Ld QFN L28.5x5
28 Ld QFN L28.5x5
OFS+
ISL6540CRZA ISL6540CRZ
ISL6540IRZA ISL6540IRZ
*Add “-T” suffix for tape and reel.
LINDRV
OFS-
-40 to 85 28 Ld QFN L28.5x5
8
9
10 11 12 13 14
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6540
Block Diagram
FN9214.1
July 23, 2008
2
ISL6540
Typical Application I (Internal Linear Regulator with Remote Sense)
+3.3V to +20V
L
IN
R
D
CC
BOOT
C
HFIN
C
BIN
C
F2
C
F1
R
BOOT
VCC
PVCC
VIN
Internal 5.6V Bias
Linear Regulator
BOOT
HSOC
R
HSOC
VFF
C
C
F3
BOOT
C
HSOC
UGATE
PHASE
Q1
L
OUT
EN
REFIN
V
OUT
VCC
C
HFOUT
C
BOUT
REFOUT
LGATE
PGND
LSOC
Q2
PG
PG_DLY
FS
R
C
LSOC
C
PG_DLY
ISL6540
10Ω
10Ω
LSOC
R
FS
COMP
C
2
C
R
3
3
Z
FB
C
1
MARCTRL
OFS+
R
2
Z
IN
R
1
FB
R
OFS+
VMON
R
MARG
R
V
SENSE+
FB
VSEN+
R
OFS-
OFS-
SS
C
SEN
R
OS
V
SENSE-
VSEN-
LINDRV
GND GND
C
SS
FN9214.1
July 23, 2008
3
ISL6540
Typical Application II (External Linear Regulator without Remote Sense)
+3.3V to +20V
L
IN
D
BOOT
C
HFIN
C
BIN
C
F2
R
CC
R
C
BOOT
F1
C
R
LC
LC
R
DRV
VCC
PVCC
BOOT
LINDRV
R
HSOC
HSOC
VIN
C
BOOT
C
F3
C
HSOC
VFF
REFOUT
REFIN
EN
UGATE
PHASE
Q1
L
OUT
V
VCC
OUT
C
BOUT
C
Q2
HFOUT
LGATE
PGND
LSOC
PG
C
PG_DLY
R
LSOC
PG_DLY
FS
ISL6540
R
FS
C
LSOC
COMP
C
2
Z
C
R
3
FB
3
C
1
MARCTRL
OFS+
R
2
Z
IN
R
1
FB
R
OFS+
R
VMON
OS
R
MARG
R
VCC
OFS-
OFS-
SS
VSEN+
VSEN-
R
vmon1
R
GND
GND
vmonOS
C
SS
FN9214.1
July 23, 2008
4
ISL6540
Typical Application III (Dual Data Rate I or II)
VDDQ
1.8V or 2.5V
L
IN
D
BOOT
5V
C
HFIN
C
BIN
R
CC
C
F2
C
F1
VIN
VCC
PVCC
BOOT
R
EN1
VFF
EN
R
HSOC
HSOC
C
BOOT
C
R
F4
EN2
C
V
HSOC
TT
(DDR I)
(DDR II)
1.25V
0.9V
UGATE
Q1
L
OUT
1K
PHASE
LGATE
PGND
LSOC
REFIN
C
HFOUT
C
BOUT
REFOUT
PG
15nF
DIMM
1K
Q2
R
C
LSOC
PG_DLY
PG_DLY
FS
ISL6540
C
R
LSOC
FS
COMP
C
2
Z
FB
C
R
3
3
C
1
MARCTRL
OFS+
R
2
Z
IN
R
1
FB
R
OFS+
R
VMON
R
MARG
FB
VSEN+
R
OFS-
OFS-
SS
C
SEN
VSEN-
LINDRV GND GND
C
SS
FN9214.1
July 23, 2008
5
ISL6540
Absolute Maximum Ratings
Thermal Information
Input Voltage, VIN, VFF . . . . . . . . . . . . . . . . . . . . . . -0.3V to +22.0V
Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Thermal Resistance (Notes 1, 2)
θ
(°C/W)
θ
(°C/W)
JA
JC
QFN Package. . . . . . . . . . . . . . . . . . 32
5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
Boot Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +36V
BOOT
Phase Voltage, V
. . . . . . . . . . V
- 6V to V + 0.3V
PHASE
Boot to Phase Voltage, V
BOOT
. . . . . . . . . . . . . . . . . . .6V
PHASE
BOOT
- V
BOOT
Other Input or Output Voltages . . . . . . . . . . . . . -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Recommended Operating Conditions
Input Voltage, VIN, VFF . . . . . . . . . . . . . . . . . . . . 3.3V to 20V ±10%
Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . 2.9V to 5.6V
Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . 2.9V to 5.6V
Boot to Phase Voltage (Overcharged), V
- V
. . . . . .<6V
BOOT
PHASE
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
JA
2. θ , "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.
JC
3. Test conditions identified as “GBD” are guaranteed by design simulation.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
INPUT SUPPLY CURRENTS
I
Nominal VCC Supply Current
Nominal PVCC Supply Current
Nominal Vin Supply Current
Shutdown VCC Supply Current
VIN = VCC = PVCC = 5V, Fs = 600kHz,
UGATE and LGATE Open
-
-
-
8
5
1
-
-
-
mA
mA
mA
VCC
I
VIN = VCC = PVCC = 5V; Fs = 600kHz,
UGATE and LGATE Open
PVCC
I
VIN = VCC = PVCC = 5V; Fs = 600kHz,
UGATE and LGATE Open
VIN
I
EN = 0V, VCC = PVCC = VIN = 5V
-
-
-
7
1
1
-
-
-
mA
mA
mA
PVCC_S
I
Shutdown PVCC Supply Current EN = 0V, VCC = PVCC = VIN = 5V
Shutdown VIN Supply Current EN = 0V, VCC = PVCC = VIN = 5V
POWER-ON RESET
VCC_S
I
VIN_S
POR
POR
POR
Rising VCC Threshold
Falling VCC Threshold
VCC Hysterisis
-
-
2.90
-
V
V
VCC_R
2.58
184
-
-
VCC_F
202
217
2.90
-
mV
V
VCC_H
POR
POR
POR
Rising PVCC Threshold
Falling PVCC Threshold
PVCC Hysterisis
-
PVCC_R
PVCC_F
PVCC_H
2.58
187
-
-
204
-
V
223
1.54
-
mV
V
POR
POR
POR
Rising VFF Threshold
Falling VFF Threshold
VFF Hysterisis
VFF_R
VFF_F
VFF_H
1.35
124
-
V
135
146
mV
ENABLE
V
Input Reference Voltage
Hysteresis Source Current
Maximum Input Voltage
0.480
0.496
10
0.512
V
μA
V
EN_REF
I
7
-
15
-
EN_HYS
V
VCC+0.3
EN
FN9214.1
July 23, 2008
6
ISL6540
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OSCILLATOR
OSC
RANGE
Nominal Frequency Range
Total Variation
GBD
250
-17
-22
-
-
2000
kHz
%
ΔOSC
COM
FS = 250kHz, 600 kHz, VFF = 3.3V to 20V
FS = 250kHz, 600 kHz, VFF = 3.3V to 20V
-
+17
ΔOSC
-
0.16*VFF
1.0
+22
%
IND
ΔV
Ramp Amplitude
-
-
-
V
OSC
P-P
V
V
Ramp Bottom
-
OSC_MIN
VFF
Minimum Usable VFF Voltage
VCC = 5V
-
3.3
V
PWM
D
Maximum Duty Cycle
Minimum Duty Cycle
Leading and Trailing-edge Modulation
Leading and Trailing-edge Modulation
-
-
100
0
-
-
%
%
MAX
D
MIN
REFERENCE TRACKING
V
Input Voltage Range
0.07
-
0
VCC-1.8V
V
REFIN
V
External Reference Offset
Maximum Drive Current
Output Voltage Range
REFIN = 0.6V
-1.2
1.8
mV
mA
V
REFIN_OS
I
C
C
C
= 1μF, VCC = 5V, REFOUT = 1.25V
= 1μF
-
0.01
-6
-
19
-
-
REFOUT
L
L
L
V
VCC-1.8V
REFOUT
V
Maximum Output Voltage Offset
Minimum Load Capacitance
Input Disable Voltage
= 1μF REFOUT = 1.25V
-
9
-
mV
μF
V
REFOUT_OS
REFOUT_MIN
C
REFOUT = 1.25V
1.0
VCC
V
-
-
REFIN_DIS
REFERENCE
V
V
Reference Voltage
System Accuracy
T
T
T
T
= 0°C to 70°C
= -40°C to 85°C
= 0°C to 70°C
= -40°C to 85°C
0.586
0.584
-0.85
-1.20
0.591
0.595
0.596
0.70
V
V
REF_COM
A
A
A
A
V
0.591
REF_IND
-
-
%
%
SYS_COM
V
0.85
SYS_IND
ERROR AMPLIFIER
DC Gain
R
R
R
= 10K, C = 100p, at COMP Pin
-
-
-
88
15
6
-
-
-
dB
L
L
L
L
UGBW
SR
Unity Gain-Bandwidth
Slew Rate
= 10K, C = 100p, at COMP Pin
MHz
V/μs
L
= 10K, C = 100p, at COMP Pin
L
DIFFERENTIAL AMPLIFIER
UG
UGBW
SR
DC Gain
Standard Instrumentation Amplifier
COMP = 10pF
-
-
0
20
-
-
dB
MHz
V/μs
mV
μA
V
Unity Gain Bandwidth
Slew Rate
-
10
-
Offset
-3
-
0
3
I
Negative Input Source Current
Input Common Mode Range Max
Input Common Mode Range Min
VSEN- Disable Voltage
6
VSEN-
-
VCC-1.8
-0.2
VCC
-
-
-
-
V
V
-
V
VSEN_DIS
OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA)
DC Gain
C
C
= 0.1μF, at SS Pin
= 0.1μF, at SS Pin
-
88
38
-
dB
SS
Drive Capability
28
50
μA
SS
FN9214.1
July 23, 2008
7
ISL6540
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
GATE DRIVERS
R
Ugate Source Resistance
Ugate Source Saturation Current
Ugate Sink Resistance
500mA Source Current, PVCC = 5.0V
-
-
-
-
-
-
-
-
1.0
2.0
1.0
2.0
1.0
2.0
0.4
4.0
-
-
-
-
-
-
-
-
Ω
A
Ω
A
Ω
A
Ω
A
UGATE
I
V
= 2.5V, PVCC = 5.0V
UGATE
UGATE-PHASE
500mA Sink Current, PVCC = 5.0V
= 2.5V, PVCC = 5.0V
R
UGATE
I
Ugate Sink Saturation Current
Lgate Source Resistance
Lgate Source Saturation Current
Lgate Sink Resistance
V
UGATE
UGATE-PHASE
500mA Source Current, PVCC = 5.0V
V = 2.5V, PVCC = 5.0V
R
LGATE
I
LGATE
LGATE
500mA Sink Current, PVCC = 5.0V
= 2.5V, PVCC = 5.0V
R
LGATE
I
Lgate Sink Saturation Current
V
LGATE
LGATE
INTERNAL LINEAR REGULATOR
Maximum Current
Saturated Equivalent Impedance VIN = 3.3V
Linear Regulator Voltage VIN = 22V, Load = 0 to 100mA
EXTERNAL LINEAR REGULATOR
I
-
-
200
2
-
mA
Ω
VIN
R
3.25
5.72
LIN
5.42
5.6
V
PVCC
LIN_DRV
Maximum Sinking Drive Current
0.25
-
0.9
mA
OVERCURRENT PROTECTION (OCP)
I
Low Side OCP (LSOC) Current
Source
LSOC = 0V to Vcc - 1.0V, T = 0°C to 70°C
79
76
-
98
98
±2
100
100
-
118
122
-
μA
μA
mV
μA
LSOC
A
LSOC = 0V to Vcc - 1.0V, T =-40°C to 85°C
A
I
LSOC Maximum Offset Error
Vcc = 2.9V and 5.6V T
< 10μs
HSOC = 0.8V to 22V T = 0°C to 70°C
LSOC_OFSET
SAMPLE
I
I
High Side OCP (HSOC) Current
Source
92
92
86
-
112
115
115
-
HSOC
HSOC
A
HSOC = 0.8V to 22V T =-40°C to 85°C
A
I
HSOC = 0.3V to 0.8V
μA
HSOC_LOW
I
HSOC Maximum Offset Error
VCC = 2.9V and 5.5V T
< 10μs
SAMPLE
±2
mV
HSOC_OFSET
MARGINING CONTROL
V
V
N
Minimum Margining Voltage of
Internal Reference
R
= 10kΩ, R
= 6.01kΩ,
= 6.01kΩ,
-185
185
-197
197
-208
208
mV
mV
MARG
MARG
MARG
MARG
MAR_CRTL = 0V
OFS-
Maximum Margining Voltage of
Internal Reference
R
= 10kΩ, R
MARG OFS+
MAR_CRTL = VCC
Margining Transfer Ratio
Positive Margining Threshold
Negative Margining Threshold
Tri-state Input Level
N
= (V -V ) / V
OFS- OFS+
4.9
5
5.1
MARG
MARG
-
-
-
1.5
-
-
-
V
V
V
MAR_CTRL
MAR_CTRL
MAR_CTRL
0.8
Disable Mode
1.325
POWER GOOD MONITOR
V
Undervoltage Rising Trip Point
Undervoltage Falling Trip Point
Overvoltage Rising Trip Point
Overvoltage Falling Trip Point
PGOOD Delay
-7%
-13%
13%
7%
-
-9%
-15%
15%
9%
5
-11%
-17%
17%
11%
-
V
UVR
SS
V
V
V
UVF
SS
V
OVR
SS
V
V
OVF
SS
T
I
C
I
= 0.1μF
ms
μA
V
PG_DLY
PG_DLY
PGOOD Delay Source Current
PGOOD Delay Threshold Voltage
PGOOD Low Output Voltage
Maximum Sinking Current
Maximum Open Drain Voltage
27
30
33
PG_DLY
V
1.44
-
1.48
-
1.56
0.200
-
PG_DLY
I
= 5mA
V
PG_LOW
PGOOD
I
V
= 0.8V
10
-
mA
V
PG_MAX
PGOOD
V
VCC = 3.3V
-
6
-
PG_MAX
FN9214.1
July 23, 2008
8
ISL6540
OFS- (Pin 7)
This pin sets the negative margining offset voltage.
Resistors should be connected to GND (R ) and OFS+
Functional Pin Description
VSEN+ (Pin 1)
OFS-
This pin provides differential remote sense for the ISL6540.
It is the positive input of a standard instrumentation amplifier
topology with unity gain, and should connect to the positive
rail of the load/processor. The voltage at this pin should be
set equal to the internal system reference voltage (0.591V
typical.)
(R
) from this pin. With MAR_CTRL logic low, the
MARG
internal 0.591V reference is developed at the OFS- pin
across resistor R
. The voltage on OFS- is driven from
OFS-
OFS+ through R
. The resulting voltage differential
MARG
between OFS+ and OFS- is divided by 5 and imposed on the
system reference. The maximum designed offset of -1V
between OFS+ and OFS- pins translates to a -200mV offset
of the system reference.
VSEN- (Pin 2)
This pin provides differential remote sense for the regulator.
It is the negative input of the instrumentation amplifier, and
should connect to the negative rail of the load/processor.
Typically 50μA is sourced from this pin. The output of the
remote sense buffer is disabled (High Impedance) by pulling
VSEN- to VCC.
VCC (Pin 8, Analog Circuit Bias)
This pin provides power for the ISL6540 analog circuitry.
The pin should be connected to a 2.9V to 5.6V bias through
an RC filter from PVCC to prevent noise injection into the
analog circuitry. This pin can be powered off the internal or
external linear regulator options.
REFOUT (Pin 3)
This pin connects to the unmargined system reference
through an internal buffer. It has a 19mA drive capability with
an output common mode range of GND to VCC. The
REFOUT buffer requires at least 1μF of capacitive loading to
be stable. This pin should not be left floating.
MARCTRL (Pin 9)
The MARCTRL pin controls margining function, a logic high
enables positive margining, a logic low sets negative
margining, a high impedance disables margining.
PG_DLY (Pin 10)
REFIN (Pin 4)
Provides the ability to delay the output of the PGOOD
assertion by connecting a capacitor from this pin to GND. A
0.1μF capacitor produces approximately a 5ms delay.
When the external reference pin (REFIN) is NOT within ~800
mV of VCC, the REFIN pin is used as the system reference
instead of the internal 0.591V reference. The recommended
REFIN input voltage range is ~60mV to VCC - 1.8V.
PGOOD (Pin 11)
Provides an open drain Power Good signal when the output
is within 9% of nominal output regulation point with 6%
hysteresis (15%/9%), and after soft-start is complete.
PGOOD monitors the VMON pin.
SS (Pin 5)
This pin provides softstart functionality for the ISL6540. A
capacitor connected to ground along with the internal 38mA
Operational Transconductance Amplifier (OTA), sets the
soft-start interval of the converter. This pin is directly
connected to the non-inverting input of the Error Amplifier.
To prevent noise injection into the error amplifier the SS
capacitor should be located within 150 mils of the SS and
GND pins.
EN (Pin 12)
This pin is compared with an internal 0.49V reference and
enables the soft-start cycle. This pin also can be used for
voltage monitoring. A 10μA current source to GND is active
while the part is disabled, and is inactive when the part is
enabled. This provides functionality for programmable
hysteresis when the EN pin is used for voltage monitoring.
OFS+ (Pin 6)
This pin sets the positive margining offset voltage. Resistors
VFF (Pin 13)
should be connected to GND (R
) and OFS-( R
)
OFS+
MARG
from this pin. With MAR_CTRL logic low, the internal 0.591V
reference is developed at the OFS+ pin across resistor
The voltage at this pin is used for input voltage feed forward
compensation and sets the internal oscillator ramp peak to
peak amplitude at 0.16 * VFF. An external RC filter may be
required at this pin in noisy input environments. The
minimum recommended VFF voltage is 2.97V.
R
R
. The voltage on OFS+ is driven from OFS- through
. The resulting voltage differential between OFS+
OFS+
MARG
and OFS- is divided by 5 and imposed on the system
reference. The maximum designed offset of 1V between
OFS+ and OFS- pins translates to a 200mV offset.
VIN (Pin 14, Internal Linear Regulator Input)
This pin should be tied directly to the input rail when using
the internal or external linear regulator options. It provides
power to the External/Internal Linear drive circuitry. When
used with an external 3.3V to 5V supply, this pin should be
tied directly to PVCC.
FN9214.1
July 23, 2008
9
ISL6540
LIN_DRV (Pin 15, External Linear Regulator Drive)
HSOC (Pin 22)
This pin allows the use of an external pass element to power
the IC for input voltages above 5.0V. It should be connected
to GND when using an external 5V supply or the internal
linear regulator. When using the external linear regulator
option, this pin should be connected to the gate of a PMOS
pass element, a pull up resistor must be connected between
the PMOS device’s gate and source for proper operation.
The high side sourcing current limit is set by connecting this
pin with a resistor and capacitor to the drain of the high side
MOSEFT. A 100μA current source develops a voltage
across the resistor which is then compared with the voltage
developed across the high side MOSFET. An initial ~120ns
blanking period is used to eliminate sampling error due to
the switching noise before the current is measured.
PVCC (Pin 16, Driver Bias Voltage)
LSOC (Pin 23)
This pin is the output of the internal series linear regulator. It
also provides the bias for both low side and high side
MOSFET drivers. The maximum voltage differential between
PVCC and PGND is 6V. Its recommended operational
voltage range is 2.9V to 5.6V. At minimum a 10μF capacitor
is required for decoupeing PVCC to PGND. For proper
operation the PVCC capacitor must be within 150mils of the
PVCC and the PGND pins and must be connected to these
pins with dedicated traces.
The low side source and sinking current limit is set by
placing a resistor (R
) and capacitor between this pin
LSOC
and PGND. A 100μA current source develops a voltage
across R which is then compared with the voltage
LSOC
developed across the low side MOSFET when on. The
sinking current limit is set at 1x of the nominal sourcing limit
in ISL6540. An initial ~120ns blanking period is used to
eliminate the sampling error due to switching noise before
the current is measured.
LGATE (Pin 17)
FS (Pin 24)
This pin provides the drive for the low side MOSFET and
should be connected to its gate.
This pin provides oscillator switching frequency adjustment
by placing a resistor (R ) from this pin to GND.
FS
PGND (Pin 18, Power Ground)
COMP (Pin 25)
This pin connects to the low side MOSFET's source and
provides the ground return path for the lower MOSFET
driver and internal power circuitries. In addition, PGND is the
This pin is the error amplifier output. It should be connected
to the FB pin through the desired compensation network.
FB (Pin 26)
return path for the low side MOSFET’s r
sensing circuit.
current
DS(ON)
This pin is the inverting input of the error amplifier and has a
maximum usable voltage of VCC-1.8V. When using the
internal differential remote sense functionality, this pin
should be connected to VMON by a standard feedback
network. In the event the remote sense buffer is disabled,
the VMON pin should be connected to VOUT by a resistor
divider along with FB’s compensation network.
PHASE (Pin 19)
This pin connects to the source of the high side MOSFET
and the drain of the low side MOSFET. This pin represents
the return path for the high side gate driver. During normal
switching, this pin is used for high side and low side current
sensing.
GND (Pin 27, Analog Ground)
UGATE (Pin 20)
Signal ground for the IC. All voltage levels are measured
with respect to this pin. This pin should not be left floating.
This pin provides the drive for the high side MOSFET and
should be connected to its gate.
VMON (Pin 28)
BOOT (Pin 21)
This pin is the output of the differential remote sense
instrumentation amplifier. It is connected internally to the
OV/UV/POOD comparators. The VMON pin should be
connected to the FB pin by a standard feedback network. In
the event of the remote sense buffer is disabled, the VMON
pin should be connected to VOUT by a resistor divider along
with FB’s compensation network. An RC filter should be
used if VMON is to be connected directly to FB instead of to
VOUT through a separate resistor divider network.
This pin provides the bootstrap bias for the high side driver.
The absolute maximum voltage differential between BOOT
and PHASE is 6.0V (including the voltage added due to the
overcharging of the bootstrap capacitor); its operational
voltage range is 2.5V to 5.6V with respect to PHASE. It is
recomended that a 2.2Ω resistor be placed in series with the
bootstrap diode to prevent over chargeing of the BOOT
capacitor during normal operation.
GND (Bottom Side Pad, Analog Ground)
Signal ground for the IC. All voltage levels are measured
with respect to this pin. This pin should not be left floating.
FN9214.1
July 23, 2008
10
ISL6540
Soft-start
The POR function activates the internal 38μA OTA which
Functional Description
Initialization
begins charging the external capacitor (C ) on the SS pin to a
SS
The ISL6540 automatically initializes upon receipt of power
without requiring any special sequencing of the input
supplies. The Power-On Reset (POR) function continually
monitors the input supply voltages (PVCC,VFF, VCC) and
the voltage at the EN pin. Assuming the EN pin is pulled to
above ~0.49V, the POR function initiates soft-start operation
after all input supplies exceed their POR thresholds.
target voltage of VCC. The ISL6540’s soft-start logic continues
to charge the SS pin until the voltage on COMP exceeds the
bottom of the oscillator ramp, at which point, the driver outputs
are enabled, with the low side MOSFET first being held low for
200ns to provide for charging of the bootstrap capacitor. Once
the driver outputs are enabled, the OTA’s target voltage is then
changed to the margined (if margining is being used) reference
HIGH = ABOVE POR; LOW = BELOW POR
voltage (V
), and the SS pin is ramped up or down
REF_MARG
accordingly. This method reduces startup surge currents due to
a pre-charged output by inhibiting regulator switching until the
control loop enters its linear region. By ramping the positive
VCC POR
VFF POR
AND
SOFT-START
input of the error amplifier to VCC and then to V
, it is
PVCC POR
EN POR
REF_MARG
even possible to mitigate surge currents from outputs that are
pre-charged above the set output voltage. As the SS pin
connects directly to the non-inverting input of the Error
Amplifier, noise on this pin should be kept to a minimum
through careful routing and part placement. To prevent noise
injection into the error amplifier the SS capacitor should be
located within 150mils of the SS and GND pins. Soft-start is
declared done when the drivers have been enabled and the SS
FIGURE 1. SOFT-START INITIALIZATION LOGIC
With all input supplies above their POR thresholds, driving
the EN pin above 0.49 V initiates a soft-start cycle. In
addition to normal TTL logic, the enable pin can be used as
a voltage monitor with programmable hysteresis through the
use of the internal 10μA sink current and an external resistor
divider. This feature is especially designed for applications
that have input rails greater than a 3.3V and require a
specific input rail POR and Hysteresis levels for better
undervoltage protection. Consider for a 12V application
pin is within ±3mV of V
.
REF_MARG
Power Good
The power good comparator references the voltage on the
soft-start pin to prevent accidental tripping during margining.
The trip points are shown on Figure 3. Additionally, power
good will not be asserted until after the completion of the soft-
start cycle. A 0.1μF capacitor at the PG_DLY pin will add an
additional ~5ms delay to the assertion of power good.
choosing R
= 100kΩ and R
= 5.76kΩ there by
) to 10V and the falling
UP
setting the rising threshold (V
DOWN
EN_RTH
) to 9V, for 1V of hysteresis (V
threshold (V
).
EN_FTH
EN_HYS
Care should be taken to prevent the voltage at the EN pin
from exceeding VCC when using the programmable UVLO
functionality.
PG_DLY does not delay the deassertion of power good.
VMON
+15%
+9%
VIN
R
UP
V
V
REF_MARG
REF
Sys_Enable
-9%
R
DOWN
I
=10μA
-15%
EN_HYS
V
GOOD
GOOD
EN_HYS
-------------------------
R
R
=
UP
I
EN_HYS
UV
OV
UV
R
• V
EN_REF
– V
EN_REF
UP
FIGURE 3. UNDERVOLTAGE-OVERVOLTAGE WINDOW
--------------------------------------------------------
=
DOWN
V
EN_FTH
1.5V
30μA
--------------
⋅
PG_DLY
T
= C
PG_DLY
V
= V
– V
EN_HYS
EN_FTH
EN_RTH
FIGURE 2. ENABLE POR CIRCUIT
Under and Overvoltage Protection
The Undervoltage (UV) and Overvoltage (OV) protection
circuitry compares the voltage on the VMON pin with the
FN9214.1
July 23, 2008
11
ISL6540
reference that tracks with the margining circuitry to prevent
accidental tripping. UV and OV functionality is not enabled
until the end of soft-start.
across the resistor (R
) a sinking OCP event is
LSOC
triggered. To avoid non-synchronous operation at light load,
the peak to peak output inductor ripple current should not be
greater than twice of the sinking current limit.
An OV event is detected asynchronously and causes the
high side MOSFET to turn off, the low side MOSFET to turn
on (effectively a 0% duty cycle), and PGOOD to pull low.
The regulator stays in this state and overrides sourcing and
sinking OCP protections until the OV event is cleared.
The high side sourcing current limit is set by connecting the
HSOC pin with a resistor (R
) and a capacitor to the
HSOC
drain of the high side MOSEFT. A 100μA current source
develops a voltage across the resistor which is then
compared with the voltage developed across the high side
MOSFET while on. When the voltage drop across the
MOSFET exceeds the voltage drop across the resistor, a
sourcing OCP event occurs. A 1000pF or greater filter
capacitor should be used in parallel with R to prevent on
chip parasitics from impacting the accuracy of the OCP
measurement and to smooth the voltage across R
presence of switching noise on the input bus.
An UV event is detected asynchronously and results in the
PGOOD pulling low.
Overcurrent Protection
HSOC
The ISL6540 monitors both the high side MOSFET and low
side MOSFET for overcurrent events. Dual sensing allows the
ISL6540 to detect overcurrent faults at the very low and very
high duty cycles that can result from the ISL6540’s wide input
range. The OCP function is enabled with the drivers at startup
and detects the peak current during each sensing period. A
resistor and a capacitor between the LSOC pin and GND set
the low side source and sinking current limits. A 100μA current
source develops a voltage across the resistor which is then
compared with the voltage developed across the low side
MOSFET at conduction mode. The measurement comparator
uses offset correcting circuitry to provide precise current
measurements with roughly ±2mV of offset error. An ~120ns
blanking period, implemented on the upper and lower MOSFET
current sensing circuitries, is used to reduce the current
sampling error due to the leading-edge switching noise. An
additional 120ns low pass filter is used to further reduce
measurement error due to noise. In sourcing current
in the
HSOC
Sourcing OCP faults cause the regulator to disable (Ugate and
Lgate drives pulled low, PGOOD pulled low, soft-start capacitor
discharged) itself for a fixed period of time after which a normal
soft-start sequence is initiated. The period of time the regulator
waits before attempting a soft-start sequence is set by three
charge and discharge cycles of the soft-start capacitor.
Simple High Side OCP Equation
I
• r
OC_SOURCE
DS(ON)HighSide
----------------------------------------------------------------------------------------
=
R
HSOC
100μA
Detailed High Side OCP Equation
ΔI
2
⎛
⎝
⎞
⎠
----
I
+
• r
OC_SOURCE
applications, the LSOC voltage is inverted and compared with
the voltage across the MOSFET while on. When this voltage
exceeds the LSOC set voltage, a sourcing OCP fault is
triggered. A 1000pF or greater filter capacitor should be used in
DS(ON),U
---------------------------------------------------------------------------------------
R
N
=
HSOC
I
• N
U
HSOC
= Number of high side MOSFETs
U
parallel with R
to prevent on chip parasitics from
LSOC
impacting the accuracy of the OCP measurement.
Sinking OCP faults cause the low side MOSFET drive to be
disabled, effectively operating the ISL6540 in a non-
Simple Low Side OCP Equation
I
• r
OC_SOURCE
DS(ON)LowSide
--------------------------------------------------------------------------------------
=
R
synchronous manner. The fault is maintained for three clock
cycles at which point it is cleared and normal operation is
restored. OVP fault implementation overrides sourcing and
sinking OCP events, immediately turning on the low side
MOSFET and turning off the high side MOSFET. The OC trip
LSOC
100μA
Detailed Low Side OCP Equations
ΔI
2
⎛
⎝
⎞
⎠
----
I
+
• r
OC_SOURCE
DS(ON),L
point varies mainly due to the MOSFETs r
variations
--------------------------------------------------------------------------------------
R
=
DS(ON)
LSOC
V
I
• N
L
LSOC
and system noise. To avoid overcurrent tripping in the
normal operating load range, find the R and/or R
- V
V
OUT
V
IN
HSOC
resistor from the previous detailed equations with:
LSOC
IN
OUT
L
------------------------------- ---------------
ΔI =
•
F
S
1. Maximum r
2. Minimum I
at the highest junction temperature;
DS(ON)
and/or I
I
• N • R
LSOC
ΔI
2
LSOC
L
------------------------------------------------------- ----
I
=
–
OC_SINK
from specification table;
HSOC
r
LSOC
DS(ON),L
3. Determine the overcurrent trip point greater than the
maximum output continuous current at maximum
inductor ripple current.
N
= Number of low side MOSFETs
L
The ISL6540’s sinking current limit is set to the same voltage
as its sourcing limit. In sinking applications, when the voltage
across the MOSFET is greater than the voltage developed
FN9214.1
July 23, 2008
12
ISL6540
range between 3.3V to 20V ±10%. The internal linear
Frequency Programming
regulator is to provide power for both the internal MOSFET
drivers through the PVCC pin and the analog circuitry
through the VCC pin. The VCC pin should be connected to
the PVCC pin with an RC filter to prevent high frequency
driver switching noise from entering the analog circuitry.
When VIN drops below 5.6V, the pass element will saturate;
PVCC will track VIN, minus the dropout of the linear
By tying a resistor to GND from FS pin, the switching
frequency can be set between 250kHz and 2MHz.
Oscillator/VFF
The Oscillator is a triangle waveform, providing for leading
and falling edge modulation. The bottom of the oscillator
waveform is set at 1.0V. The ramp's peak to peak amplitude
is determined from the voltage on the VFF (Voltage Feed
Forward) pin by the equation: DVosc = 0.16*VFF. An internal
RC filter of 233kΩ and 2pF (341kHz) provides filtering of the
VFF voltage. An external RC filter may be required to
augment this filter in the event that it is insufficient to prevent
noise injection or control loop interactions. Voltages below
2.9V on the VFF pin may result in undesirable operation due
to extremely small peak to peak oscillator waveforms. The
oscillator waveform should not exceed VCC -1.0V. For high
VFF voltages the internal/external 5.6 V linear regulator
should be used. 5.6V on VCC provides sufficient headroom
for 100% duty cycle operation when using the maximum
VFF voltage of 22V. In the event of sustained 100% duty
cycle operation, defined as 32 clock cycles where no LG
pulse is detected, LG will be pulsed on to refresh the
design’s Bootstrap capacitor.
regulator: PVCC = VIN-2xI
. When used with an external
VIN
5V supply, the VIN pin should be tied directly to PVCC.
External Series Linear Regulator
The LIN_DRV pin provides sinking drive capability for an
external pass element linear regulator controller. The
external linear options are especially useful when the
internal linear dropout is too large for a given application.
When using the external linear regulator option, the
LIN_DRV pin should be connected to the gate of a PMOS
device, and a resistor should be connected between its gate
and source. A resistor and a capacitor should be connected
from gate to source to compensate the control loop. A PNP
device can be used instead of a PMOS device in which case
the LIN_DRV pin should be connected to the base of the
PNP pass element. The maximum sinking capability of the
LIN_DRV pin is 0.5mA, and should not be exceeded if using
an external resistor for a PMOS device. The designer should
take care in designing a stable system when using external
pass elements. The VCC pin should be connected to the
PVCC pin with an RC filter to prevent high frequency driver
switching noise from entering the analog circuitry.
100
10
1
High Speed MOSFET Gate Driver
The integrated driver has similar drive capability and
features to Intersil's ISL6605 stand alone gate driver. The
PWM tri-state feature helps prevent a negative transient on
the output voltage when the output is being shut down. This
eliminates the Schottky diode that is used in some systems
for protecting the microprocessor from reversed-output-
voltage damage. See the ISL6605 datasheet for
100
1000
10000
FREQUENCY (kHz)
FIGURE 4. R RESISTANCE vs. FREQUENCY
FS
specification parameters that are not defined in the current
ISL6540 electrical specifications table.
A 1-2Ω resistor is recommended to be in series with the
bootstrap diode when using VCCs above 5.0V to prevent the
bootstrap capacitor from overcharging due to the negative
swing of the trailing edge of the phase node.
10
–0.973
Fs[Hz] ≈ 1.178×10 • R [Ω]
(R TO GND)
T
T
Internal Series Linear Regulator
The VIN pin is connected to PVCC with a 2Ω internal series
linear regulator, which is internally compensated. The
external Series Linear regulator option should be used for
applications requiring pass elements of less than 2Ω. When
using the internal regulator, the LIN_DRV pin should be
connected directly to GND. The PVCC and VIN pins should
have a bypasses capacitor (at least 10μF on PVCC is
required) connected to PGND. For proper operation the
PVCC capacitor must be within 150mils of the PVCC and the
PGND pins, and be connected to these pins with dedicated
traces. The internal series linear regulator’s input (VIN) can
Margining Control
When the MAR_CTRL is pulled high or low, the positive or
negative margining functionality is respectively enabled.
When MAR_CTRL is left floating, the function is disabled.
Upon UP margining, an internal buffer drives the OFS- pin
from VCC to maintain OFS+ at 0.591V. The resistor divider,
R
and R , causes the voltage at OFS- to be
MARG
OFS+
increased. Similarly, upon DOWN margining, an internal
buffer drives the OFS+ pin from VCC to maintain OFS- at
0.591V. The resistor divider, R
MARG
and R
, causes the
OFS-
FN9214.1
July 23, 2008
13
ISL6540
voltage at OFS+ to be increased. In both modes the voltage
difference between OFS+ and OFS- is then sensed with an
instrumentation amplifier and is converted to the desired
margining voltage by a 5:1 ratio. The maximum designed
margining range of the ISL6540 is ±200mV, this sets the
VCC
REFERENCE
=0.591V
ISL6540
STATE
MACHINE
V
REF
MINIMUM value of R
or R
at approximately 5.9K
of 10K for a MAXIMUM of 1V across R
OFS+
OFS-
REFIN
for an R
.
MARG
MARG
800mV
The OFS pins are completely independent and can be set to
different margining levels. The maximum usable reference
voltage for the ISL6540 is VCC-1.8V, and should not be
exceeded when using the margining functionality, i.e,
REFOUT
V
REF_MARG
MARGINING
BLOCK
V
< VCC - 1.8V.
OTA
REF_MARG
V
R
MARG
REF
5
-------------- --------------------
V
=
•
MARG_UP
R
OFS+
FIGURE 5. SIMPLIFIED REFERENCE BUFFER
V
R
REF
5
MARG
Internal Reference and System Accuracy
-------------- --------------------
V
=
•
MARG_DOWN
R
OFS-
The internal reference is trimmed to 0.591V. The total DC
system accuracy of the system is within 0.85% over
commercial temperature range, and 1.25% over industrial
temperature range. System accuracy includes error amplifier
offset, OTA error, and bandgap error. Differential remote
sense offset error is not included. As a result, if the
differential remote sense is used, then an extra 3mV of offset
error enters the system. The use of REFIN may add up to
1.8mV of additional offset error.
An alternative calculation provides for a desired percentage
change in the output voltage when using the internal 0.591V
reference:
R
R
MARG
MARG
--------------------
V
= 20 •
--------------------
V
= 20 •
pct_DOWN
PCT_UP
R
R
OFS-
OFS+
When not used in a design OFS+, OFS-, and MARCTRL
should be left floating. To prevent damage to the part, OFS+
and OFS- should not be tied to VCC or PVCC.
Differential Remote Sense Buffer
The differential remote sense buffer is essentially an
instrumentation amplifier with unity gain. The offset is
trimmed to 3mV for high system accuracy. As with any
instrumentation amplifier typically 6μA are sourced from the
VSEN- pin. The output of the remote sense buffer is
connected directly to the internal OV/UV comparator. As a
result, a resistor divider should be placed on the input of the
buffer for proper regulation, as shown in Figure 6. The
VMON pin should be connected to the FB pin by a standard
feed-back network. A small capacitor, CSEN in Figure 6, can
be added to filter out noise, typically CSEN is chosen so the
corresponding time constant does not reduce the overall
phase margin of the design, typically this is 2x to 10x
switching frequency of the regulator.
Reference Output Buffer
The internal buffer’s output tracks the unmargined system
reference. It has a 19mA drive capability, with maximum and
minimum output voltage capabilities of VCC and GND
respectively. Its capacitive loading can range from 1μF to
above 17.6μF, which is designed for 1 to 8 DIMM systems in
DDR (Dual Data Rate) applications. 1μF of capacitance
should always be present on REFOUT. It is not designed to
drive a resistive load and any such load added to the system
should be kept above 300kΩ total impedance.
Reference Input
The REFIN pin allows the user to bypass the internal 0.591V
reference with an external reference. Asynchronously if
REFIN is NOT within ~800mV of VCC, the external
reference pin is used as the control reference instead of the
internal 0.591V reference. The minimum usable REFIN
voltage is ~60mV while the maximum is VCC - 1.8V -
As some applications will not use the differential remote
sense, the output of the remote sense buffer can be disabled
(high impedance) by pulling VSEN- within 800mV of VCC.
As the VMON pin is connected internally to the
OV/UV/PGOOD comparator, an external resistor divider
must then be connected to VMON to provide correct voltage
information for the OV/UV comparator. An RC filter should
be used if VMON is to be connected directly to FB instead of
to VOUT through a separate resistor divider network. This
filter prevents noise injection from disturbing the
V
(if present). The limitation is set by the error
MARG
amplifier's maximum common mode input range of VCC -
1.8V for the industrial temperature ranges.
OV/UV/PGOOD comparators on VMON. VMON may also be
connected to the SS pin, which completely bypasses the
OV/UV/PGOOD functionality.
FN9214.1
July 23, 2008
14
ISL6540
VSENSE-
(REMOTE)
VSENSE+
(REMOTE)
10Ω
10Ω
VOUT (LOCAL)
GND (LOCAL)
R
FB
R
OS
C
SEN
Z
Z
IN
FB
VSEN+
VCC
VSEN-
VMON
COMP
FB
OV/UV
COMP
ERROR AMP
800mV
GAIN=1
V
SS
FIGURE 6. SIMPLIFIED UNITY GAIN DIFFERENITAL SENSING IMPLEMENTATION
part of ground or power plane in a printed circuit board. The
components shown in Figure 8 should be located as close
together as possible. Please note that the capacitors C
Application Guidelines
Layout Considerations
IN
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
and C each represent numerous physical capacitors.
O
Locate the ISL6540 within 3 inches of the MOSFETs, Q1
and Q2. The circuit traces for the MOSFETs’ gate and
source connections from the ISL6540 must be sized to
handle up to 4A peak current.
Proper grounding of the IC is important for correct operation
in noisy environments. The PGND pin should be connected
to board ground at the source of the low side MOSFET with
a wide short trace. The GND pin should be connected to a
large copper fill under the IC which is subsequently
connected to board ground at a quite location on the board,
typically found at an input or output bulk (electrolytic)
capacitor.
V
IN
ISL6540
+V
Q1
IN
UGATE
Q1
Q2
BOOT
L
O
D1
V
OUT
PHASE
C
L
O
BOOT
PHASE
+5V
PVCC
PGND
V
OUT
C
IN
ISL6540
C
O
SS
LGATE
PGND
C
Q2
O
C
PVCC
C
SS
GND
RETURN
FIGURE 7. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Figure 7 shows the critical power components of the
converter. To minimize the voltage overshoot/undershoot
the interconnecting wires indicated by heavy lines should be
FN9214.1
July 23, 2008
15
ISL6540
Figure 8 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
C
2
current paths on the SS pin and locate the capacitor, C
C
3
R
SS
3
R
C
2
1
close to the SS pin (as described earlier) as the internal
current source is only 38μA. Provide local decoupling
between PVCC and PGND pins as described earlier. Locate
COMP
-
R
FB
1
+
the capacitor, C
PHASE pins.
as close as practical to the BOOT and
BOOT
E/A
VREF
Compensating the Converter
VMON
R
FB
The ISL6540 single-phase converter is a voltage-mode
-
VSEN-
VSEN+
controller. This section highlights the design considerations for
a voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
network is recommended (see Figure 9).
C
SEN
R
OS
+
V
OSCILLATOR
OUT
V
IN
C
2
V
OSC
PWM
CIRCUIT
C
R
1
2
COMP
FB
L
DCR
C
UGATE
PHASE
HALF-BRIDGE
DRIVE
C
3
R
1
ISL6540
R
3
VMON
ESR
LGATE
ISL6540
EXTERNAL CIRCUIT
FIGURE 9. COMPENSATION CONFIGURATION FOR ISL6540
WHEN USING DIFFERENTIAL REMOTE SENSE
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Figure 10 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, when using an internal
differential remote sense amplifier. The output voltage
The compensation network consists of the error amplifier
(internal to the ISL6540) and the external R -R , C -C
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
1
3
1
3
(V
) is regulated to the reference voltage, VREF, level.
OUT
The error amplifier output (COMP pin voltage) is compared
with the oscillator (OSC) triangle wave to provide a pulse-
frequency (F ; typically 0.1 to 0.3 of F ) and adequate
0
SW
phase margin (better than 45°). Phase margin is the
width modulated wave with an amplitude of V at the
IN
difference between the closed loop phase at F and 180°.
0dB
The equations that follow relate the compensation network’s
poles, zeros and gain to the components (R , R , R , C , C ,
PHASE node. The PWM wave is smoothed by the output
filter (L and C). The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.
1
2
3
1
2
and C ) in Figures 9 and 10. Use the following guidelines for
3
The modulator transfer function is the small-signal transfer
locating the poles and zeros of the compensation network:
function of V
DC gain, given by d
output filter, with a double pole break frequency at F and a
zero at F . For the purpose of this analysis C and ESR
CE
represent the total output capacitance and its equivalent
series resistance.
/V
. This function is dominated by a
V /V , and shaped by the
OUT COMP
1. Select a value for R (1kΩ to 10kΩ, typically). Calculate
1
MAX IN OSC
value for R for desired converter bandwidth (F ). If
2
0
LC
setting the output voltage to be equal to the reference set
voltage as shown in Figure 22, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 10), in order
to compensate for the attenuation introduced by the
1
1
---------------------------
F
=
---------------------------------
F
=
LC
CE
2π ⋅ C ⋅ ESR
2π ⋅ L ⋅ C
resistor divider, the below obtained R value needs be
2
multiplied by a factor of (R +R )/R . The remainder
OS FB OS
of the calculations remain unchanged, as long as the
compensated R value is used.
2
FN9214.1
July 23, 2008
16
ISL6540
frequency response of the modulator (G
), feedback
MOD
compensation (G ) and closed-loop response (G ):
V
⋅ R ⋅ F
0
⋅ V ⋅ F
IN LC
FB
CL
OSC
1
---------------------------------------------
=
R
2
d
d
⋅ V
MAX
1 + s(f) ⋅ ESR ⋅ C
MAX
V
IN
----------------------------- -----------------------------------------------------------------------------------------------------------
G
(f) =
(f) =
⋅
MOD
2
OSC
A small capacitor, CSEN in Figure 10, can be added to filter
out noise, typically CSEN is chosen so the corresponding
time constant does not reduce the overall phase margin
of the design, typically this is 2x to 10x switching
1 + s(f) ⋅ (ESR + DCR) ⋅ C + s (f) ⋅ L ⋅ C
1 + s(f) ⋅ R ⋅ C
2
1
----------------------------------------------------
G
⋅
FB
s(f) ⋅ R ⋅ (C + C )
1
1
2
frequency of the regulator. As the ISL6540 supports
1 + s(f) ⋅ (R + R ) ⋅ C
3
1
3
100% duty cycle, d
equals 1. The ISL6540 also uses
-------------------------------------------------------------------------------------------------------------------------
MAX
feedforward compensation, as such V
C
⋅ C
⎛
⎛
⎜
⎝
⎞⎞
⎟⎟
⎠⎠
is equal to
1
2
OSC
0.16 multiplied by the voltage at the VFF pin. When tieing
--------------------
(1 + s(f) ⋅ R ⋅ C ) ⋅ 1 + s(f) ⋅ R ⋅
2
⎜
3
3
C
+ C
2
⎝
1
VFF to V the above equation simplifies to:
IN
G
(f) = G
(f) ⋅ G (f)
MOD FB
where, s(f) = 2π ⋅ f ⋅ j
CL
0.16 ⋅ R ⋅ F
1
0
----------------------------------
R
=
2
F
LC
As before when tieing VFF to VIN terms in the above
equations can be simplified as follows:
2. Calculate C such that F is placed at a fraction of the F
,
1
Z1 LC
at 0.1 to 0.75 of F (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
LC
d
⋅ V
1 ⋅ V
IN
MAX
V
IN
-----------------------------
--------------------------
=
= 6.25
0.16 ⋅ V
OSC
IN
filter and/or the higher the ratio F /F , the lower the F
CE LC Z1
frequency (to maximize phase boost at F ).
LC
COMPENSATION BREAK FREQUENCY EQUATIONS
1
----------------------------------------------
C
=
1
2π ⋅ R ⋅ 0.5 ⋅ F
1
--------------------------------------------
2
LC
1
------------------------------
F
=
F
=
P1
Z1
C
⋅ C
2
2π ⋅ R ⋅ C
1
2
1
3. Calculate C such that F is placed at F
.
--------------------
⋅
2
2π ⋅ R
2
P1 CE
C
+ C
2
1
C
1
1
1
-------------------------------------------------------
=
C
-------------------------------------------------
2π ⋅ (R + R ) ⋅ C
------------------------------
2π ⋅ R ⋅ C
F
=
F
=
2
2π ⋅ R ⋅ C ⋅ F – 1
CE
Z2
P2
2
1
1
3
3
3
3
4. Calculate R such that F is placed at F . Calculate C
3
3
Z2
LC
Figure 11 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
such that F is placed below F
(typically, 0.5 to 1.0
P2 SW
times F ). F
represents the regulator’s switching
frequency. Change the numerical factor to reflect desired
SW SW
placement of this pole. Placement of F lower in frequency
P2
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
compensation gain at F against the capabilities of the error
P2
R
1
amplifier. The closed loop gain, G , is constructed on the
CL
log-log graph of Figure 11 by adding the modulator gain,
---------------------
R
=
3
F
SW
------------
– 1
F
G
(in dB), to the feedback compensation gain, G (in
LC
MOD
FB
1
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
------------------------------------------------
2π ⋅ R ⋅ 0.7 ⋅ F
C
=
3
3
SW
It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
F
F
F
P1
F
Z1 Z2
P2
R2
-------
⎛
⎝
⎞
⎠
20log
d
⋅ V
IN
R1
MAX
20log---------------------------------
V
0
OSC
G
FB
G
CL
G
MOD
FREQUENCY
LOG
F
F
F
0
LC
CE
FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FN9214.1
July 23, 2008
17
ISL6540
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
V
- V
V
OUT
V
IN
IN
F
OUT
the switching frequency, F
.
SW
------------------------------- ---------------
ΔI =
•
ΔV
= ΔI x ESR
OUT
x L
S
Component Selection Guidelines
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6540 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the
transient and slow the current load rate seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (effective series resistance) and
voltage rating requirements rather than actual capacitance
requirements.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1.0μF
ceramic capacitors in the 1206 surface-mount package.
Follow on specifications have only increased the number
and quality of required ceramic decoupling capacitors.
L
× I
L × I
O TRAN
O
TRAN
-------------------------------
------------------------------
t
=
t
=
FALL
RISE
V
– V
V
IN
OUT
OUT
where: I
is the transient load current step, t
is the
is the
TRAN
response time to the application of load, and t
RISE
FALL
response time to the removal of load. With a lower input
source such as 1.8V or 3.3V, the worst case response time
can be either at the application or removal of load and
dependent upon the output voltage setting. Be sure to check
both of these equations at the minimum and maximum
output levels for the worst case response time.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor's ESR value is related to
the case size with lower ESR available in larger case sizes.
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter.
Work with your capacitor supplier and measure the
capacitor’s impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q1 and the source of Q2.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
FN9214.1
July 23, 2008
18
ISL6540
MOSFET Selection/Considerations
The ISL6540 requires 2 N-Channel power MOSFETs. These
should be selected based upon r , gate supply
0.60
0.50
0.40
0.30
0.20
0.10
0.00
DS(ON)
0.5Io
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
0.25Io
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). The
upper MOSFET exhibits turn-on and turn-off switching
losses as well as the reverse recover loss, while the
synchronous rectifier exhibits body-diode conduction losses
during the leading and trailing edge dead times.
ΔI=0Io
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY CYCLE (D)
1
FIGURE 12. INPUT-CAPACITOR CURRENT MULTIPLIER FOR
SINGLE-PHASE BUCK CONVERTER
r
2
DS(ON),L
ΔI
2
⎛
⎝
⎞
⎠
---------------------------
P
P
=
I
+
•
• (1 – D) + P
-------
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
below.
LOWER
O
DEAD
N
L
12
ΔI
ΔI
⎛
⎝
⎞
⎠
⎛
⎞
⎠
------
=
I
+
• V
• t
+ I
–
• V • t
• F
------
DEAD
O
DT DT
O
DL DL S
⎝
12
12
r
2
DS(ON),U
ΔI
2
⎛
⎞
⎠
---------------------------
P
P
=
I
+
•
• D + P
+ P
-------
V
2
UPPER
O
SW
Qrr
⎝
O
ΔI
-------
N
U
12
2
2
----------
D =
I
=
I
(D – D ) +
D
IN, RMS
O
VIN
12
ΔI
12
ΔI
⎛
⎝
⎞
⎛
⎞
------
=
I
+
• t
+ I
–
• t
• VIN • F
S
------
SW
O
OFF
O
ON
⎠
⎝
⎠
12
OR
I
= K
• I
P
= Q • VIN • F
rr S
IN, RMS
ICM
O
Qrr
where D is the duty cycle = V / VIN; Q is the reverse
rr
O
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-
GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
recover charge; t and t are leading and trailing edge
DL
DT
dead time, and t
& t
are the switching intervals.
ON
OFF
These equations do not include the gate-charge losses that
are proportional to the total gate charge and the switching
frequency and partially dissipated by the internal gate
resistance of the MOSFETs. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
ISL6540 DC/DC Converter Application Circuit
Detailed information on the application circuit, including a
complete Bill-of-Materials and circuit board description, can
be found in application note AN1204. See Intersil’s home
page on the web: http://www.intersil.com.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9214.1
July 23, 2008
19
ISL6540
Package Outline Drawing
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/07
4X
3.0
5.00
0.50
24X
A
6
B
PIN #1 INDEX AREA
28
22
6
PIN 1
INDEX AREA
1
21
3 .10 ± 0 . 15
15
7
(4X)
0.15
8
14
0.10 M C A B
- 0.07
TOP VIEW
28X 0.55 ± 0.10
BOTTOM VIEW
4
28X 0.25
+ 0.05
SEE DETAIL "X"
C
0.10
0 . 90 ± 0.1
C
BASE PLANE
SEATING PLANE
0.08
C
( 4. 65 TYP )
(
( 24X 0 . 50)
SIDE VIEW
3. 10)
(28X 0 . 25 )
( 28X 0 . 75)
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN9214.1
July 23, 2008
20
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