ISL6549IBZ_技术文档

DATASHEET

ISL6549

Rev X.00

Single 12V Input Supply Dual Regulator —Synchronous Rectified Buck PWM and

Linear Power Controller

The ISL6549 provides the power control and protection for

two output voltages in high-performance applications. The

Features

• Single 12V bias supply (no 5V supply is required)

dual-output controller drives two N-Channel MOSFETs in a

synchronous rectified buck converter topology and one

N-Channel MOSFET in a linear configuration. The controller is

ideal for applications where regulation of both the processing

unit and memory supplies is required.

• Provides two regulated voltages

- One synchronous rectified buck PWM controller

- One linear controller

• Both controllers drive low cost N-Channel MOSFETs

• Small converter size

- Adjustable frequency 150kHz to 1MHz

- Small external component count

The synchronous rectified buck converter incorporates

simple, single feedback loop, voltage-mode control with fast

transient response. Both the switching regulator and linear

regulator provide a maximum static regulation tolerance of

±1% over line, load, and temperature ranges. Each output is

user-adjustable by means of external resistors.

• Excellent output voltage regulation

- Both outputs: ±1% over temperature

• 12V down conversion

An integrated soft-start feature brings both supplies into

regulation in a controlled manner. Each output is monitored

via the FB pins for undervoltage events. If either output drops

below 75% of the nominal output level, both converters are

shut off and go into retry mode.

• PWM and linear output voltage range: down to 0.8V

• Simple single-loop voltage-mode PWM control design

• Fast PWM converter transient response

- High-bandwidth error amplifier

• Undervoltage fault monitoring on both outputs

• Pb-free plus anneal available (RoHS compliant)

The ISL6549 is available in a 14 Ld SOIC package,

16 Ld QSOP, or 16 Ld 4x4 QFN packages.

Applications

Related Literature

• Technical Brief TB363 Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)

•

Processor and memory supplies

• ASIC power supplies

• Embedded processor and I/O supplies

• DSP supplies

Ordering Information

PART NUMBER

PART MARKING

ISL6549CB

TEMP. RANGE (°C)

PACKAGE

PKG. DWG. #

M14.15

ISL6549CB

0 to 70

14 Ld SOIC

ISL6549CBZ (Note)

ISL6549CR

6549CBZ

14 Ld SOIC (Pb-free)

16 Ld 4x4 QFN

M14.15

ISL6549CR

6549CRZ

0 to 70

L16.4x4

M16.15A

M14.15

ISL6549CRZ (Note)

ISL6549CA

0 to 70

16 Ld 4x4 QFN (Pb-free)

16 Ld QSOP

ISL6549CA

6549CAZ

0 to 70

ISL6549CAZ (Note)

ISL6549CAZA (Note)

ISL6549IBZ (Note)

ISL6549IRZ (Note)

ISL6549IAZ (Note)

ISL6549LOW-EVAL1

ISL6549HI-EVAL1

Add “-T” suffix for tape and reel.

0 to 70

16 Ld QSOP (Pb-free)

14 Ld SOIC (Pb-free)

16 Ld 4x4 QFN (Pb-free)

16 Ld QSOP (Pb-free)

6549CAZ

0 to 70

6549IBZ

-40 to 85

6549IRZ

L16.4x4

M16.15A

6549IAZ

Evaluation Board 1-5A

Evaluation Board up to 20A

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Rev X.00

Page 1 of 18

ISL6549

Pinouts

ISL6549 (SOIC)

ISL6549 (QFN)

ISL6549 (QSOP)

TOP VIEW

16 15 14 13

BOOT

1

14

UGATE

BOOT

FS_DIS

COMP

FB

1

2

3

4

5

6

7

8

16

UGATE

2

3

4

5

6

7

13 PHASE

FS_DIS

COMP

FB

15 PHASE

1

2

3

4

12

11

10

9

COMP

FB

PGND

LGATE

PVCC5

VCC5

12

PGND

14

PGND

METAL

GND

PAD

11

13

LGATE

12

LDO_DR

LDO_FB

AGND

PVCC5

10

LDO_DR

LDO_FB

GND

PVCC5

(BOTTOM)

LDO_DR

LDO_FB

11

VCC5

9

VCC5

10 VCC12

8 VCC12

DGND

9

VCC12

5

6

7

8

Block Diagram

VCC5

VCC12

POWER-ON

RESET (POR)

5V

VOLTAGE

REFERENCE

REGULATOR

PVCC5

LDO_FB

RESTART

BOOT

SOFT-START

UGATE

PHASE

LDO_DR

EA2

DIS

INHIBIT

GATE

SOFT-START

LOGIC

PWM

COMP

EA1

DIS

LGATE

PGND

FS_DIS

GND

OSCILLATOR

UV1

UV2

FB

COMP

Rev X.00

Page 2 of 18

ISL6549

Simplified Power System Diagram

+V

IN1

+12V

+V

IN2

Q1

Q2

V

LINEAR

CONTROLLER

OUT1

Q3

PWM

CONTROLLER

V

OUT2

+

ISL6549

Typical Application Schematic

+V

IN1

+12V

C

BP12

VCC12

BOOT

PVCC5

VCC5

C

BP

+

+V

IN2

C

VIN1

+

C

BP5

C

VIN2

C

BOOT

Q1

Q2

UGATE

PHASE

L

OUT

LDO_DR

LDO_FB

Q3

V

OUT1

V

+

OUT2

LGATE

C

OUT1

+

C

OUT2

ISL6549

FB

FS_DIS

GND

COMP

PGND

Rev X.00

Page 3 of 18

ISL6549

Absolute Maximum Ratings

Thermal Information

VCC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +14V

PVCC5, VCC5 . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +7V

VCC5 (if used with external supply). . . . . . . . . . .GND - 0.3V to +6V

BOOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +27V

Thermal Resistance



(°C/W)



(°C/W)

JC

JA

SOIC Package (Note 1) . . . . . . . . . . . .

QFN Package (Notes 2, 3). . . . . . . . . .

QSOP Package (Note 1) . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C

(SOIC - Lead Tips Only)

105

52

110

N/A

14

N/A

PHASE. . . . . . . . . . . . . . . . . . . . . . . . V

- 7V to V

+ 0.3V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V

BOOT

V

- V

PHASE

BOOT

UGATE. . . . . . . . . . . . . . . . . . . . . . V

- 0.3V to V

+ 0.3V

PHASE

BOOT

LGATE . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to PVCC5 + 0.3V

LDO_DR . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC12 + 0.3V

FB, LDO_FB, COMP, FS_DIS . . . . . . . GND - 0.3V to VCC5 + 0.3V

ESD Classification

Recommended Operating Conditions

External Supply Voltage on VCC5. . . . . . . . . . . . . . . . . . +5.0V ±5%

Supply Voltage on VCC12 . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

Ambient Temperature Range (C). . . . . . . . . . . . . . . . . . 0°C to 70°C

Ambient Temperature Range (I) . . . . . . . . . . . . . . . . -40°C to +85°

Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0°C to +125°C

Human Body Model (Per JESD22-A114C) . . . . . . . . . . . . . . Class 2

Machine Model (Per EIA/JESD22-A115-A) . . . . . . . . . . . . . .Class B

Charge Device Model (Per JESD22-C101C). . . . . . . . . . . . Class IV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1.  is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2.  is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

3. For  , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions, unless otherwise noted. VCC12 = 12V

Temperature = 0 to +70°C (typical = +25°C) for Commercial; Temperature = -40 to + 85°C (typical = +25°C) for

Industrial. Refer to Block Diagram, Simplified Power System Diagram, and Typical Application Schematic.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VCC SUPPLY CURRENT

Nominal Supply Current VCC12 (disabled)

I

UGATE, LGATE and LDO_DR open;

FS_DIS = GND

2

5

3

7.5

18

6

mA

CC12 dis

Nominal Supply Current VCC5 (disabled)

I

UGATE, LGATE and LDO_DR open;

FS_DIS = GND (Note 4)

CC5 dis

Nominal Supply Current VCC12

(includes PVCC5 current)

I

UGATE, LGATE and LDO_DR open;

12

4

CC12

F

= 620kHz

OSC

UGATE, LGATE and LDO_DR open;

= 620kHz

Nominal Supply Current VCC5

I

CC5

F

OSC

Maximum PVCC5 Current Available (Note 5)

VCC12 to PVCC5 Current Limit (Note 5)

PVCC5 Voltage

I

100

150

mA

V

PVCC5

I

PVCC5CL

V

ISL6549C; No external load

ISL6549I; No external load

4.95

4.85

5.25

5.8

PVCC5

POWER-ON RESET

Rising VCC5 Threshold

Falling VCC5 Threshold

Rising VCC12 Threshold

Falling VCC12 Threshold

OSCILLATOR AND SOFT-START

Switching Frequency

VCC12 = 12V

VCC5 = 5V

3.7

3.3

8.8

7.0

4.2

3.8

9.5

7.5

4.5

4.1

V

10.0

8.0

VCC5 = 5V

F

ISL6549C; R

= 45.3k

540

525

620

700

kHz

OSC

FS_DIS

ISL6549I; R

= 45.3k

FS_DIS

Rev X.00

Page 4 of 18

ISL6549

Electrical Specifications Recommended Operating Conditions, unless otherwise noted. VCC12 = 12V

Temperature = 0 to +70°C (typical = +25°C) for Commercial; Temperature = -40 to + 85°C (typical = +25°C) for

Industrial. Refer to Block Diagram, Simplified Power System Diagram, and Typical Application Schematic.

(Continued)

PARAMETER

Sawtooth Amplitude (Note 6)

Soft-Start Interval

SYMBOL

TEST CONDITIONS

MIN

TYP

1.5

MAX

UNITS

V

DV

OSC

SS

T

F

= 620kHz

6.8

ms

OSC

REFERENCE VOLTAGE

Reference Voltage

V

ISL6549C; For Error Amp 1 and 2

ISL6549I; For Error Amp 1 and 2

0.792

0.788

0.8

0.808

0.812

V

REF

PWM CONTROLLER ERROR AMPLIFIER

DC Gain (Note 6)

R

= 10K, C = 10pF

96

20

dB

MHz

V/µs

µA

V

L

Gain-Bandwidth Product (Note 6)

Slew Rate (Note 6)

GBWP

SR

= 10K, C = 10pF

L

= 10K, C = 10pF

8

L

FB Input Current

I 

V

= 0.8V

0.1

4.8

0.6

-2.8

75

1.0

80

I

FB

COMP High Output Voltage

COMP Low Output Voltage

COMP High Output, Source Current

V

High

OUT

V

Low

V

OUT

I

High

mA

%

Undervoltage Level (V /V

)

V

70

17

FB REF

UV

PWM CONTROLLER GATE DRIVERS

UGATE Maximum Voltage

V

VCC12 = 12V; PHASE = 12V

17.5

5.25

0

18

6

HUGATE

LGATE Maximum Voltage

V

VCC12 = 12V; based on PVCC5 voltage

VCC12 = 12V; PHASE = 0V

V

HLGATE

UGATE and LGATE Minimum Voltage

UGATE Source Output Impedance

UGATE Sink Output Impedance

LGATE Source Output Impedance

LGATE Sink Output Impedance

LINEAR REGULATOR (LDO_DR)

DC Gain (Note 6)

V

0.5

LGATE

DS(ON)

R

VCC12 = 12V; I

= 100mA

0.8

0.7

0.8

0.4



GATE

Gain

R

= 10K, C = 10pF

100

2

dB

MHz

Vµs

µA

V

L

Gain-Bandwidth Product (Note 6)

Slew Rate (Note 6)

GBWP

SR

= 10K, C = 10pF

L

= 10K, C = 10pF

6

L

LDO_FB Input Current

I 

V

= 0.8V

0.1

11.0

0.0

2.0

0.5

75

1.0

11.5

0.5

I

LDO_FB

LDO_DR High Output Voltage

LDO_DR Low Output Voltage

LDO_DR High Output Source Current

LDO_DR Low Output Sink Current

V

High VCC12 = 12V

Low

OUT

V

OUT

I

High

Low

V

= 2.0V

mA

%

OUT

I

OUT

Undervoltage Level (V

NOTES:

/V

LDO_FB REF

)

V

Percent of Nominal

70

80

UV

4. Current in VCC5 is actually higher disabled, due to extra current required to pull down against the FS_DIS pin. VCC12 current is lower disabled.

5. Guaranteed by design, not production tested. Exceeding the maximum current from PVCC5 may result in degraded performance and unsafe

operation.

6. Guaranteed by design, not production tested.

Rev X.00

Page 5 of 18

ISL6549

FB

Functional Pin Description

FB is the available external inverting input pin of the error

amplifier. Connect the output of the switching regulator to

this pin through a properly sized resistor divider, to set the

output voltage. The voltage at this pin is regulated to the

internal reference voltage. This pin is also monitored for

undervoltage detection.

VCC12

This is the power supply pin for the IC; it sources the internal

5V regulator used for the gate drivers. Provide a local

decoupling capacitor to GND. The voltage at this pin is

monitored for Power-On Reset (POR) purposes. The

16 Ld QFN and 16 Ld QSOP have two VCC12 pins; tie them

together on the board.

COMP

COMP is the available external output pin of the error amplifier.

This pin is used to compensate the voltage-mode control

feedback loop of the standard synchronous rectified buck

converter. Connect an appropriate compensation network

between this and the FB pin. See “PWM Controller Feedback

Compensation” on page 10 for more information.

VCC5

This pin supplies the internal 5V bias for analog and logic

functions. Provide a local decoupling capacitor to GND, and a

resistor to PVCC. The voltage at this pin is monitored for

Power-On Reset (POR) purposes. See “Internal PVCC5

Regulator” on page 7 for more details.

FS_DIS

GND, AGND, DGND

This input pin has two functions. A resistor to GND sets the

internal oscillator frequency for the switching regulator. In

addition, if the pin is pulled down towards GND with a low

impedance (<1k, such as an external FET), it will disable

both regulator outputs until released (at which time a new soft-

start cycle will begin).

These pins are the signal ground for the IC. All voltage levels

are measured with respect to these pins. Connect all to the

ground plane via the shortest available path.

PVCC5

This pin is the internal 5V linear regulator for the BOOT supply

(for the UGATE driver), and the source for the LGATE.

Provide a local decoupling capacitor to PGND. Do not use this

pin as a voltage source for other circuits. See “Internal PVCC5

Regulator” on page 7 for more details.

LDO_DR

This output pin provides the gate voltage for the linear

regulator pass transistor. Connect this pin to the gate terminal

of an external N-channel MOSFET transistor. This pin (along

with the LDO_FB pin) also provides a means of compensating

the error amplifier, should the application require it.

PGND

This pin is the power ground return for the lower gate driver.

(LGATE). Connect to the ground plane on the board via the

shortest available path.

LDO_FB

This input pin is the FB inverting input on the linear regulator

error amplifier. Connect the output of the linear regulator to

this pin through a properly sized resistor divider, to set the

output voltage. The voltage at this pin is regulated to the

internal reference voltage. This pin is also monitored for

undervoltage detection.

UGATE

This output pin drives the upper MOSFET gate from the

internal 5V regulator. Connect it to the gate of the upper

MOSFET via a short, low inductance trace.

BOOT

Bottom Pad (QFN Package Only)

The BOOT pin, along with the external capacitor (from

PHASE to BOOT), an internal diode, and the internal 5.5V

regulator, creates the bootstrap voltage for the upper gate

driver (UGATE). The maximum voltage is around 5.5V (above

PHASE).

The QFN package’s metal bottom pad is resistively tied to the

internal IC GND. For best thermal and electrical performance,

connect this pad to the GND pins, and to the ground plane of

the PCB through 4 vias equidistantly situated inside the solder

landing pad.

PHASE

This pin represents the return path for the upper gate drive.

Connect it to the source of the upper MOSFET via a short, low

inductance trace.

LGATE

This output pin drives the lower MOSFET gate from the

internal 5V regulator. Connect it to the gate of the lower

MOSFET via a short, low inductance trace.

Rev X.00

Page 6 of 18

ISL6549

collapse, shutting down everything until the load current is

reduced or removed.

Description

Operation Overview

Initialization

The ISL6549 monitors and precisely controls two output

voltage levels. Refer to the “Block Diagram” on page 2,

“Simplified Power System Diagram” on page 3, and “Typical

Application Schematic” on page 3. The controller is intended

for use in applications where only a 12V bias input is

available. The IC integrates both a standard buck PWM

controller and a linear controller. The PWM controller

The ISL6549 automatically initializes upon application of input

power (at the VCC12) pin. The ISL6549 creates its own

PVCC5 and VCC5 supplies for internal use. The POR

function continually monitors the input bias supply voltage at

the VCC12 and VCC5 pins. The POR function initiates soft-

start operation after both these supply voltages exceed their

POR rising threshold voltages.

regulates the output voltage (V

) to a level programmed

OUT1

by a resistor divider. The linear controller is designed to

regulate the lower current local memory voltage (V

through an external N-Channel MOS pass transistor.

Soft-Start

)

OUT2

The POR function initiates the digital soft-start sequence. Both

the linear regulator error amplifier and PWM error amplifier

reference inputs are forced to track a voltage level

Internal PVCC5 Regulator

proportional to the soft-start voltage. As the soft-start voltage

slews up, the PWM comparator regulates the output relative

to the tracked soft-start voltage, slowly charging the output

capacitor(s). Simultaneously, the linear output follows the

smooth ramp of the soft-start function into normal regulation.

The preferred and recommended configuration is as follows:

+12V to VCC12 pin, a resistor (~10) between PVCC5 and

VCC5 pins, and decoupling caps on all three pins to ground.

This creates the PVCC5 voltage for the gate drivers, and

externally filters it for bias on the VCC5 pin. It also guarantees

that all 3 voltages track each other during power-up and

power-down.

Figure 1 shows the soft-start sequence. Both the VCC12 and

VCC5 pins must be above their respective rising POR trip

points. In most cases, as shown here, the last one exceeding

its threshold is the VCC12 around 9.5V. The ramp time is

based on the internal oscillator period multiplied by 4096. So

for a 600kHz (1.67µs) example, the soft-start ramp time would

be 6.8ms.

The PVCC5 pin cannot be used as an input and it should not

be used as an output for other circuits; its current capability is

reserved for the gate drivers and VCC5 bias. Similarly, the

VCC5 pin should not be used as an output. Although not

preferred, the VCC5 pin can be used with an external 5V

supply (±5%). However, proper precautions must be followed,

which mainly have to do with proper sequencing, to prevent

latch-up or related problems. Note in the power-up diagram

(Figure 1), the 5V lags the 12V by a few msecs and a volt or

so; that is expected. Both the VCC12 and VCC5 pins must

exceed their rising POR trip points before the soft-start is

enabled; the trip order is not important as long as both have

some voltage. The 12V can be present with no 5V at all, but

the 5V should not precede the 12V. Similarly, on power down,

the 5V should discharge with or before the 12V.

VCC12 (2V/DIV)

VCC12 > 9.5V

VCC5 (2V/DIV)

V

(1V/DIV)

OUT1

OUT2

Under normal operation, the internal regulator can supply up

to 100mA (which includes the VCC5 bias current, with the

resistor between the pins). The amount of current is

determined primarily by the switching parameters: the

oscillator frequency and the loading of the FET gates.

Overloading of the internal regulator is not recommended;

even if there is enough current, the gate driver waveforms

may be degraded. See “Switcher FET Considerations” on

page 13 for more details.

GND>

FIGURE 1. 12V POWER-UP INTO SOFT-START

Figure 2 shows more detail of the output ramps, by increasing

the time and voltage resolution. The clock for the DAC

producing the steps is approximately 9.4kHz (600kHz/64), so

each step is just over 100µs long. The step voltage is 1/64 of

the final value for each output; around 31mV for V

15.6mV for V

OUT2

steps of voltage (and current) that effectively charge the

output capacitor, the potentially large peak current resulting

from a sudden, uncontrolled voltage rise are eliminated, by

spreading it out over the whole ramp time.

The PVCC5 pin has a current limit that provides some

protection against a shorted gate driver dragging down the

12V rail. The temperature of the IC will increase as the current

and corresponding on-chip power dissipation increases.

There is no thermal shutdown, so even if the current limit is

effective, the IC can be subject to very high temperatures. If

the current limit is exceeded, the regulator voltage will likely

and

in this example. By providing many small

OUT1

Rev X.00

Page 7 of 18

ISL6549

.

Undervoltage Protection

V

OUT1

The FB and LDO_FB pins are each monitored during

converter operation by their own Undervoltage (UV)

comparator. If either FB voltage drops below 75% of the

reference voltage (75% of 0.8V = 0.6V), a fault signal is

internally generated, and the fault logic shuts down BOTH

regulators. The UV comparators are enabled when the

soft-start ramp is about one-quarter (25%) done.

V

OUT2

(0.5V/DIV)

V

(2.5V)

OUT2

GND>

V

(1.5V)

OUT1

FIGURE 2. EXPANDED VIEW: VOLTAGE RAMP AND TIME

A few clock cycles are used for initialization to insure that soft-

start begins near zero volts. The ramps are the same, whether

triggered by releasing FS_DIS or by exceeding the POR trip

levels.

GND>

DELAY INTERVAL

Both outputs use the same soft-start ramp, and the ramp time

is determined by the switching frequency. Thus, there is no

simple way to disable or sequence them independently, or to

change the ramp rate independently of the clock.

INTERNAL SOFT-START FUNCTION

If the switcher output is already pre-charged to a voltage when

the regulator starts up, the ISL6549 will detect this condition

(see Figure 3). The red trace shows the normal ramp, when

the output starts at GND. The green trace shows the case

when the output is pre-charged to a voltage less than the final

output. The upper or lower FET does not turn on until the soft-

start ramp voltage exceeds the output; then the output starts

ramping seamlessly from there. If the output voltage is pre-

charged above the normal output level, as shown in the

magenta trace, neither FET will turn on until the end of the

soft-start ramp; then the output will be quickly pulled down to

the final value.

GND>

SOFT-START

DELAY

SOFT-START

DELAY

T1

T2

T0

T3

T4

(T1 TO T2 NOT TO SCALE) TIME

FIGURE 4. UNDERVOLTAGE PROTECTION RESPONSE

Figure 4 illustrates the protection feature responding to a UV

event on V

. At time T0, V has dropped below 75%

OUT1

of the nominal output voltage. Both outputs are quickly shut

down and the UGATE and LGATE stop switching immediately,

but the fall time of each output is determined by the load

and/or short condition on each plus the output capacitance

that needs to be discharged. The soft-start function begins

producing an internal soft-start ramp. The delay interval, T0 to

T1, seen by the output is equivalent to one soft-start cycle.

Then a normal soft-start ramp of the output starts, at time T1.

At the one-quarter point of the soft-start ramp (not drawn

exactly to scale), the good output will have ramped one-

quarter way up, while the shorted output will presumably be

lower than a quarter (depending on the magnitude of the

short). Once the UV comparators are enabled (at the

VCC12 (2V/DIV)

VCC12 > 9.5V

V

OVER-CHARGED (1V/DIV)

OUT2

V

PRE-CHARGED (1V/DIV)

OUT2

one-quarter point) both outputs will again shut down (if the

fault is still present on one of them). Time T2 starts a new

internal soft-start cycle, and at T3, starts a new ramp, similar

to T1. This time, if we assume the short has gone away, the

outputs will ramp up to T4 as they should. If the short has not

gone away, then the T0, T1, T2 hiccup mode cycle will keep

repeating indefinitely; this cycle time is the equivalent of 1.25

GND>

V

NO CHARGE (1V/DIV)

OUT2

FIGURE 3. PRE-CHARGED OUTPUT

Rev X.00

Page 8 of 18

ISL6549

soft-start cycles (1 internal soft-start ramp cycle, plus

one-quarter on the next).

dependence between the resistor chosen and the resulting

switching frequency.

If either V

INx

voltage is not present at startup, that will cause a

is

Output Voltage Selection

UV shutdown and restart cycle; similarly, if either V

INx

The output voltage of the PWM converter can be programmed

removed after start-up, a shutdown and restart cycle will start

when its output drifts down to the UV trip point. But in both

to any level between V

However, even though the ISL6549 can run at near 100%

duty cycle at zero load, additional voltage margin is required

and the internal reference, 0.8V.

IN1

cases, once the V

is restored, the V will recover on

INx

OUTs

the next soft-start ramp.

above V

to allow for loading. An external resistor divider is

IN1

used to scale the output voltage relative to the reference

voltage and feed it back to the inverting input of the error

amplifier (see Figure 7). A typical value for R1 may be 1.00k

(±1% for accuracy), and then R4 (also ±1%) is chosen

according to Equation 1:

V

(0.5V/DIV)

1.6ms

6.4ms

OUT2

R1  0.8V

R4 = ---------------------------------------

(EQ. 1)

V

– 0.8V

OUT1

R1 is also part of the compensation circuit (see “PWM

Controller Feedback Compensation” on page 10 for more

details), so once chosen for that, it should not be changed to

V

(0.5V/DIV)

OUT2

GND>

adjust V

; only change R4. If the output voltage desired

is 0.8V, simply route V back to the FB pin through R1,

OUT1

V

(0.5V/DIV)

OUT1

but do not populate R4. V

voltages less than the 0.8V

OUT1

FIGURE 5. UNDERVOLTAGE PROTECTION (SIMULATED BY

HAVING NO VIN1 ON POWER-UP)

reference are not available.

V

Q1

Q2

IN1

Figure 5 shows an example of the start-up, with V

powered. V

OUT2

not

ramps up one-quarter of the way, at which

IN1

+

ISL6549

UGATE

C

IN1

time the UV comparators are enabled. Since V

is not

IN1

L

OUT

V

present, V

OUT1

will not be following the soft-start ramp up,

OUT1

PHASE

and it will fail the test for UV, shutting down both outputs. It

starts an internal delay time-out (equal to one soft-start

interval), and then starts a new ramp. For this example, it

shows about a 1.6ms ramp up, and 6.4ms off, before the next

ramp starts. Thus, the total period of 8ms is based on 1.25

soft-start cycles (one-quarter of the first ramp, and then one

full time-out, at a clock period of around 1.6µs) The dotted

+

LGATE

C

OUT1

FB

C2

R1

C3

COMP

R3

magenta line shows the case where V

ramp all of the way up to 2V.

is allowed to

OUT2

C1

V

R2

R4

R1

R4





= 0.8  1 + -------

OUT1





Switching Frequency

1M

FIGURE 7. OUTPUT VOLTAGE SELECTION OF THE

SWITCHER (V

)

OUT1

The linear regulator output voltage is also set by means of

an external resistor divider as shown in Figure 8. Select a

value for R5 (typical 1.00k ±1% for accuracy), and use

Equation 2 to calculate R6 (also ±1%), where V

is the

OUT2

is the

desired linear regulator output voltage and V

REF

internal reference voltage, 0.8V. For an output voltage of

0.8V, simply populate R5 with a value less than 5k and do

100k

10k

100k

1M

R (k)

not populate R6. V

voltages less than the 0.8V

OUT2

FIGURE 6. FREQUENCY vs FS RESISTOR

reference are not available.

R5  0.8V

_OUT2– 0.8V

The switching frequency of the ISL6549 is determined by the

value of the FS resistor. The graph in Figure 6 shows the

(EQ. 2)

R6 = --------------------------------------

V

Rev X.00

Page 9 of 18

ISL6549

For most situations, no external compensation is required for

the linear output. See “Linear Controller Feedback

Compensation” on page 12.

and forces the LGATE to go high for one oscillator cycle,

which allows the bootstrap capacitor time to recharge.

PWM Controller Feedback Compensation

For both outputs, the selection of 1% resistors may not be

able to get the exact ratio desired for any given output voltage.

If the output must be defined better, then one option is to

place a much bigger resistor in parallel with R4 or R6, to lower

its value. For example, a 100k in parallel with a 1.00k

yields 990, 1% below 1.00k, which gives finer resolution

than the next lower size (976 1%). The big resistor may not

have to be 1% tolerance either.

This section highlights the design consideration for a

voltage-mode controller requiring external compensation. To

address a broad range of applications, a type-3 feedback

network is recommended (see Figure 9).

C2

C1

R2

COMP

If the linear output is not required, connect the LDO_DR pin

directly to LDO_FB pin with no other components. This will

terminate the signals and keep the linear from tripping its

undervoltage, which would force both outputs into retry.

FB

C3

ISL6549

R1

V

IN2

R3

+

C

IN2

V

(V )

DIFF OUT

Q3

LDO_DR

FIGURE 9. COMPENSATION CONFIGURATION FOR ISL6549

CIRCUIT

V

OUT2

LDO_FB

R5

Figure 10 highlights the voltage-mode control loop for a

synchronous-rectified buck converter, applicable to the

+

ISL6549

C

R6

OUT2

ISL6549 circuit. The output voltage (V

) is regulated to the

OUT

reference voltage, VREF. The error amplifier output (COMP pin

voltage) is compared with the oscillator (OSC) modified

saw-tooth wave to provide a pulse-width modulated wave with

R5

R6





V

= 0.8  1 + -------

OUT2





an amplitude of V at the PHASE node. The PWM wave is

FIGURE 8. OUTPUT VOLTAGE SELECTION OF THE LINEAR

(V

IN

)

smoothed by the output filter (L and C). The output filter

capacitor bank’s equivalent series resistance is represented by

the series resistor E.

OUT2

Converter Shutdown

Pulling and holding the FS_DIS pin near GND will shut down

both regulators; almost any NFET or other pull-down device

(<1k impedance) should work. Upon release of the FS_DIS

pin, the regulators enter into a soft-start cycle which brings

both outputs back into regulation. The FS_DIS pin requires a

quiet GND to minimize jitter. To accomplish this, the FS

resistor and any pull-down device should be placed as close

as possible to the pin, and the GND should be kept away from

the noisy FET GND.

The modulator transfer function is the small-signal transfer

function of V

/V

. This function is dominated by a DC

V /V , and shaped by the output

OUT COMP

gain, given by d

MAX IN OSC

filter, with a double pole break frequency at F and a zero at

LC

. For the purpose of this analysis, L and D represent the

F

CE

channel inductance and its DCR, while C and E represents

the total output capacitance and its equivalent series

resistance.

1

---------------------------

F

=

-----------------------

F

=

Boot Capacitor, Boot Refresh

LC

(EQ. 3)

CE

2  C  E

2  L  C

A capacitor from the PHASE pin to the BOOT pin is required

for the bootstrap circuit for the Upper Gate. The V

voltage

IN1

The compensation network consists of the error amplifier

(internal to the ISL6549) and the external R1-R3, C1-C3

components. The goal of the compensation network is to

provide a closed loop transfer function with high 0dB crossing

(and thus the PHASE node) is allowed to go as high as a

nominal 12V (±10%) supply. A diode is included on the IC

(anode to PVCC5 pin, cathode to BOOT pin), such that the

PVCC5 (nominally around 5.25V) will be the bootstrap supply.

frequency (F ; typically 0.1 to 0.3 of F ) and adequate phase

0

SW

In the event that the UGATE is on for an extended period of

time, the charge on the boot capacitor can start to sag, raising

margin (better than 45 degrees). Phase margin is the difference

between the closed loop phase at F and 180°. The

0dB

the R

of the upper FET. The ISL6549 has a circuit that

detects a long UGATE on-time (32 oscillator clock periods),

DS(ON)

equations that follow relate the compensation network’s poles,

zeros and gain to the components (R1, R2, R3, C1, C2, and

C3) in Figure 10.

Rev X.00

Page 10 of 18

ISL6549

4. Calculate R3 such that F is placed at F . Calculate C3

Z2

LC

such that F is placed below F

(typically, 0.5 to 1.0

C2

P2

SW

times F ). F

SW

represents the switching frequency.

SW

Change the numerical factor to reflect desired placement

C3

R3

of this pole. Placement of F lower in frequency helps

P2

R2

C1

reduce the gain of the compensation network at high

frequency, in turn reducing the HF ripple component at

the COMP pin and minimizing resultant duty cycle jitter.

COMP

-

R1

FB

+

Ro

E/A

R1

---------------------

1

R3 =

-------------------------------------------------

C3 =

F

VREF

SW

2  R3  0.7  F

------------

SW

– 1

F

LC

(EQ. 7)

It is recommended a mathematical model is used to plot the

loop response. Check the loop gain against the error

amplifier’s open-loop gain. Verify phase margin results and

adjust as necessary. Equation 8 describes the frequency

V

OSCILLATOR

OUT

V

IN

V

OSC

PWM

CIRCUIT

response of the modulator (G

), feedback compensation

MOD

L

(G ) and closed-loop response (G ):

D

UGATE

PHASE

FB

CL

HALF-BRIDGE

DRIVE

d

 V

IN

1 + sf  E  C

MAX

V

C

----------------------------- ----------------------------------------------------------------------------------------

G

f =



MOD

2

OSC

1 + sf  E + D  C + s f  L  C

E

LGATE

1 + sf  R2  C1

------------------------------------------------------

G

f =



FB

sf  R1  C1 + C2

1 + sf  R1 + R3  C3

ISL6549

EXTERNAL CIRCUIT

----------------------------------------------------------------------------------------------------------------------------



C1  C2

C1 + C2





----------------------

1 + sf  R3  C3  1 + sf  R2 

FIGURE 10. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN





G

f = G

f  G f

MOD FB

where sf = 2  f  j

CL

Use the following guidelines for locating the poles and zeros of

the compensation network:

(EQ. 8)

COMPENSATION BREAK FREQUENCY EQUATIONS

1. Select a value for R1 (1k to 5k, typically). Calculate

value for R2 for desired converter bandwidth (F ). If

0

1

----------------------------------------------

F

=

-------------------------------

F

=

setting the output voltage via an offset resistor connected

to the FB pin, Ro in Figure 10, the design procedure can

be followed as presented.

P1

Z1

Z2

C1  C2

2  R2  C1

----------------------

2  R2 

C1 + C2

1

---------------------------------------------------

-------------------------------

F

=

P2

2  R1 + R3  C3

2  R3  C3

V

 R1  F

0

 V  F

IN LC

OSC

(EQ. 4)

(EQ. 9)

---------------------------------------------

R2 =

d

MAX

Figure 11 shows an asymptotic plot of the DC-DC converter’s

gain vs. frequency. The actual Modulator Gain has a high gain

peak dependent on the quality factor (Q) of the output filter,

which is not shown. Using the above guidelines should yield a

compensation gain similar to the curve plotted. The open loop

error amplifier gain bounds the compensation gain. Check the

2. Calculate C1 such that F is placed at a fraction of the F

Z1 LC

,

at 0.1 to 0.75 of F (to adjust, change the 0.5 factor to

LC

desired number). The higher the quality factor of the output

filter and/or the higher the ratio F /F , the lower the F

CE LC

Z1

frequency (to maximize phase boost at F ).

LC

compensation gain at F against the capabilities of the error

amplifier. The closed loop gain, G , is constructed on the

CL

P2

1

-----------------------------------------------

C1 =

(EQ. 5)

2  R2  0.5  F

LC

log-log graph of Figure 11 by adding the modulator gain, G

MOD

(in dB), to the feedback compensation gain, G (in dB). This is

FB

3. Calculate C2 such that F is placed at F

P1

.

equivalent to multiplying the modulator transfer function and the

compensation transfer function and then plotting the resulting

gain.

CE

C1

---------------------------------------------------------

(EQ. 6)

C2 =

2  R2  C1  F

– 1

CE

Rev X.00

Page 11 of 18

ISL6549

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6549 will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval, the

difference between the inductor current and the transient

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

MODULATOR GAIN

COMPENSATION GAIN

CLOSED LOOP GAIN

OPEN LOOP E/A GAIN

F

P1

F

Z1 Z2

P2

R2

-------









20log

d

 V

IN

R1

MAX

20log---------------------------------

V

0

OSC

G

FB

G

CL

The response time to a transient is different for the application

of load and the removal of load. Equation 11 gives the

approximate response time interval for application and

removal of a transient load:

G

MOD

FREQUENCY

LOG

F

0

LC

CE

L

 I

L  I

O TRAN

O

TRAN

FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

-------------------------------

------------------------------

(EQ. 11)

t

=

t

=

FALL

RISE

V

– V

V

IN

OUT

A stable control loop has a gain crossing with close to a

-20dB/decade slope and a phase margin greater than 45°.

Include worst case component variations when determining

phase margin. The mathematical model presented makes a

number of approximations and is generally not accurate at

frequencies approaching or exceeding half the switching

frequency. When designing compensation networks, select

target crossover frequencies in the range of 10% to 30% of

where: I

TRAN

response time to the application of load, and t

is the transient load current step, t

RISE

is the

FALL

response time to the removal of load. With a +5V input

source, the worst case response time can be either at the

application or removal of load and dependent upon the output

voltage setting. Be sure to check both of these equations at

the minimum and maximum output levels for the worst case

response time.

the switching frequency, F

.

SW

Linear Controller Feedback Compensation

Output Capacitors Selection

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current. The

load transient requirements are a function of the slew rate

(di/dt) and the magnitude of the transient load current. These

requirements are generally met with a mix of capacitors and

careful layout.

For most situations, no external compensation is required for

the linear output. As long as the output capacitor (C

) is

OUT2

large (>100µF) and so is its ESR (>20mW), then it should be

stable for loads as low as 10mA up to at least 4A. If smaller

values of capacitance and/or ESR are desired, then special

considerations may be required to add external

compensation (as shown in Figure 8).

Modern microprocessors produce transient load rates above

1A/ns. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

Component Selection Guidelines

Output Inductor Selection

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function of

the ripple current. The ripple voltage and current are

approximated by Equation 10.

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements. And keep in mind that not all

applications have the same requirements; some may need

many ceramic capacitors in parallel; others may need only one.

V

- V

V

OUT

V

IN

F

OUT

------------------------------- ---------------

I =



V

OUT

= I x ESR

x L

SW

(EQ. 10)

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce the

converter’s response time to a load transient (and usually

increases the DCR of the inductor, which decreases the

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors.

The bulk capacitor’s ESR will determine the output ripple

voltage and the initial voltage drop after a high slew-rate

efficiency). Increasing the switching frequency (F ) for a

SW

given inductor also reduces the ripple current and voltage.

Rev X.00

Page 12 of 18

ISL6549

transient. An aluminum electrolytic capacitor's ESR value is

related to the case size with lower ESR available in larger

case sizes. However, the equivalent series inductance

(ESL) of these capacitors increases with case size and can

reduce the usefulness of the capacitor to high slew-rate

transient loading. Unfortunately, ESL is not always a

specified parameter. Work with your capacitor supplier and

measure the capacitor’s impedance with frequency to

select a suitable component. In most cases, multiple

electrolytic capacitors of small case size perform better

than a single large case capacitor.

0.1µF or 0.22µF as a starting value. The bootstrap capacitors

for the ISL6549 can usually be rated for 6.3V.

Switcher FET Considerations

The IC was designed for nominal 12V supply for V

IN1

(drain of

upper FET Q1). However, it will work with most any voltage

(from other supplies or other regulator outputs) down to

around 1V, as long as the input is above the output by a

sufficient margin (based on practical duty cycle limitations and

upper FET R

constraints). For example, although the

DS(ON)

IC can function at near 100% duty cycle, the voltage drop due

to the R of the upper FET at full load current will limit

DS(ON)

the practical duty cycle to something less than 100%. So the

V range is roughly 1.0V up to 12V, with the V range

IN1

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

to supply the current needed each time Q1 turns on. Place the

small ceramic capacitors physically close to the MOSFETs

and between the drain of upper FET Q1 and the source of

lower FET Q2.

OUT1

slightly below it. Therefore, the FETs need to be rated for

drain-source breakdown above the V

30V ratings are common.

voltage; 20V and

IN1

The ISL6549 gate drivers (UGATE and LGATE) were

designed to drive up to 2 upper and 2 lower 8 Ld SOIC FETs;

when the FETs are properly sized, the output currents can

range from under 1A to over 20A. Driving more or bigger FETs

is not recommended; even if there is enough current (from the

internal PVCC5 regulator), the gate driver waveforms may be

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum input

voltage and a voltage rating of 1.5 times is a conservative

guideline. The RMS current rating requirement for the input

capacitor of a buck regulator is approximately half the DC load

current. Several electrolytic capacitors may be needed.

2

degraded. DPAK FET packages can be used, but D PAK

FETs are not recommended, due to the higher inductance of

the package leads. For example, the inductance in the source

of the lower FET can create large negative spikes on the

PHASE node when the UGATE turns off.

Both the UGATE and LGATE voltages are derived from the

internal PVCC5 internal regulator, typically 5.25V. UGATE is

only about 5.0V above PHASE, due to the drop in the internal

BOOT diode charging the BOOT capacitor; LGATE sees the

full 5.25V. So both are considered “5V” drivers; this affects the

FET selection in two ways. First, the FET gate-source voltage

rating can be as low as 12V (this rating is usually consistent

with the 20V or 30V breakdown chosen above). Second, the

FETs must have a low threshold voltage (around 1V), in order

Bootstrap Capacitor Selection

The boot diode is internal to the ISL6549, and uses PVCC5 to

charge the external boot capacitor. The size of the bootstrap

capacitor can be chosen by using the equations in Equation

12.

Q

N  Q  V

G IN

GATE

V

and

-------------------

----------------------------------

C



Q

=

GATE

BOOT

V

GS

to have its R

rating at V = 4.5V in the 10m-20m

DS(ON)

GS

range. While some FETs are also rated with gate voltages as

low as 2.7V, with typical thresholds under 1V, these can cause

application problems. As LGATE shuts off the lower FET, it

does not take much ringing in the LGATE signal to turn the

lower FET back on, while the Upper FET is also turning on,

causing some shoot-through current. So avoid FETs with

thresholds below 1V.

where

N is the number of upper FETs

Q

is the total gate charge per upper FET

is the input voltage

G

V

IN

is the gate-source voltage (~5V for ISL6549)

GS

V is the change in boot voltage before and immediately

after the transfer of charge; typically 0.7V to 1.0V

Another set of important parameters are the turn-on and

turn-off times (internal propagation delays, how long before

the output starts to switch) and the rise and fall times (external

delay to complete the switching). The UGATE and LGATE

drivers use an adaptive technique to determine the dead time

(when both gate drivers signals are low). Comparators sense

when each driver is getting close to GND (such that its FET is

close to being off), before turning on the other. This technique

minimizes the dead time to the 10ns-20ns range. So if either

Q

N  Q  V

G IN

1  33  12

------------------- ---------------------------------- ---------------------------

= 0.113F

GATE

V

C



=

BOOT

V

 V

5  0.7

GS

(EQ. 12)

The last equation plugs in some typical values: N = 1;

is 33nC, V is 12V, V is 11V, V = 1V. In this

Q

G

IN GS max

example, C

 0.113µF. This value is often rounded to

BOOT

Rev X.00

Page 13 of 18

ISL6549

FET is particularly slow in these parameters, there is a greater

chance that shoot-through current will occur.

typically adds power to the IC side, but may reduce some

power on the FET side). For low duty cycle applications (such

as 12V in to 1.5V out), the upper FET is usually chosen for low

gate charge, since switching losses are key, while the lower

As referenced in the “Block Diagram” on page 2, the UGATE

signal is referenced to PHASE signal. The deadtime

comparator also looks at the difference (UGATE - PHASE).

This is significant when viewing the gate driver waveforms on

an oscilloscope. One simple indication of shoot-through (or

insufficient deadtime) is when the UGATE and LGATE signals

overlap. But in this case, one should look at UGATE-PHASE

(either by a math function of the two signals, or by using a

differential probe measurement) compared to LGATE.

Figure 12 shows an example of this. It looks as if the UGATE

and LGATE signals have crossed, but the UGATE-PHASE

signal does not cross the LGATE.

FET is chosen for low R

, since it is on most of the time.

DS(ON)

For high duty cycles (such as 3.3V in to 2.5V out), the

opposite is true.

In summary, the following parameters may need to be

considered in choosing the right FETs for an application:

drain-source breakdown voltage rating, gate-source rating,

maximum current, thermal and package considerations, low

gate threshold voltage, gate charge, R

at 4.5V, and

DS(ON)

switching speed. And, of course, the board layout constraints

and cost also are factored into the decision.

Linear FET Considerations

The linear FET is chosen primarily for thermal performance.

The current for the linear output is generally limited by the

power dissipation (P = (V

- V ) * I), and the FET

IN2

OUT2

UGATE (4V/DIV)

PHASE (4V/DIV)

thermal rating for getting the heat out of the package, and

spreading it out on the board, especially when no heatsinks or

airflow is available. It is generally not recommended to parallel

two FETs in order to get higher current or to spread out the

heat, as the FETs would need to be very well-matched in

order to share the current properly. Should this approach be

desired, and as perfectly matched FETs are seldom available,

a small resistor, or PCB trace of suitable resistance placed in

the source of each of the FETs can be used to improve the

current balance.

LGATE (4V/DIV)

UGATE-PHASE (4V/DIV)

GND>

FIGURE 12. GATE DRIVER WAVEFORMS

The maximum V

several factors:

voltage allowed is determined by

OUT2

One important consideration is negative spikes on the PHASE

node as it goes low. The upper FET is turning off, but before

the lower FET can take over, stray inductance in the layout

(on the board, or even the inductance of some components,

• Power dissipation, as described earlier

• Input voltage available

• LDO_DR voltage

2

such as D PAK FETs) can contribute to the PHASE going

• FET chosen

negative.

The voltage cannot be any higher than the input voltage

There is no maximum spec for PHASE spike below GND,

however, there is an absolute maximum rating for

available, and the max V

is 12V (13.2V for a ±10% supply).

IN2

The LDO_DR voltage is driven from the VCC12 rail; allowing

for headroom, the typical maximum voltage is 11V (lower as

VCC12 goes to its minimum of 10.8V). So the maximum

(BOOT - PHASE) of 7V; exceeding this limit can cause

damage to the IC, and possibly to the system. Since the

BOOT signal is typically 5V above the PHASE node most of

the time, it only takes a few volts of a spike on either signal to

exceed the limit. A good design should be characterized by

using the math function or differential probe, and monitoring

these signals for compliance, especially during full loads,

where the signals are usually the noisiest. Slowing down the

turn-off of the upper FET may help, while at other times,

sometimes the problem may just be the choice of FETs.

output voltage will be at least a V

drop (which includes the

GS

FET threshold voltage) below the 11V, at the maximum load

current; some additional headroom is usually needed to

handle transient conditions. So a practical typical value

around 8V may be possible, but remember to also factor in

the variations for worst case conditions on V

parameters. As long as the V

IN2

and the FET

is low enough such that

IN2

headroom versus VCC12 is not a problem, then the maximum

output voltage is just below V , based on the R

at maximum current.

drop

IN2

DS(ON)

If the power efficiency of the system is important, then other

FET parameters are also considered. Efficiency is a measure

of power losses from input to output, and it contains two major

components: losses in the IC (mostly in the gate drivers) and

losses in the FETs. Optimizing the sum involves many

The input supply for V

IN2

can also be any available supply

less than 12V, subject to the considerations above. The

drain-source breakdown voltage of the FET should be greater

trade-offs (for example, raising the voltage of the gate drivers

Rev X.00

Page 14 of 18

ISL6549

than the V

voltage. The FET’s gate-source rating should be

components. Position the bypass capacitors, C , C , and C

4 5 6

IN2

greater than 12V (even though the output voltage may not

require such a high gate voltage, load transients or other

disturbances might force LDO_DR to momentarily approach

12V). The FET threshold is not critical, except for the cases

where the LDO_DR headroom is diminished. And finally, the

package (and board area allowed) must be able to handle the

maximum power dissipation expected.

close to their pins with a local GND connection, or via directly

to the ground plane. R12 should be placed near VCC5 and

PVCC5 pins. FS_DIS resistor R7 should be near the FS-DIS

pin, and its GND return should be short, and kept away from

the noisy FET GND. Place the PWM converter compensation

components close to the FB and COMP pins. The feedback

resistors for both regulators should also be located as close

as possible to the relevant FB pin with vias tied straight to the

ground plane as required.

Application Guidelines

Layout Considerations

Then the switching components should be placed close to the

ISL6549. Minimize the length of the connections between the

Layout is very important in high frequency switching converter

design. With power devices switching efficiently at 600kHz,

the resulting current transitions from one device to another

cause voltage spikes across the interconnecting impedances

and parasitic circuit elements. These voltage spikes can

degrade efficiency, radiate noise into the circuit, and lead to

device overvoltage stress. Careful component layout and

printed circuit board design minimizes the voltage spikes in

the converters.

input capacitors, C , and the power switches by placing them

IN

nearby. Position both the ceramic and bulk input capacitors as

close to the upper MOSFET drain as possible, and make the

GND returns (from lower FET source to VIN cap GND) short.

Position the output inductor and output capacitors between

the upper MOSFET and lower MOSFET and the load.

V

IN1

VCC12

GND

As an example, consider the turn-off transition of the PWM

upper MOSFET. Prior to turn-off, the MOSFET is carrying the

full load current. During turn-off, current stops flowing in the

upper MOSFET and is picked up by the lower MOSFET and

parasitic diode. Any parasitic inductance in the switched

current path generates a large voltage spike during the

switching interval. Careful component selection, tight layout of

the critical components, and short, wide traces minimizes the

magnitude of voltage spikes.

C

4

C

IN1

ISL6549

PVCC5

PGND

BOOT

C

6

C

7

Q1

L

OUT

UGATE

PHASE

V

OUT1

R12

There are two sets of critical components in a DC/DC converter

using the ISL6549. The switching components are the most

critical because they switch large amounts of energy, and

therefore tend to generate large amounts of noise. Next are the

small signal components which connect to sensitive nodes or

supply critical bypass current and signal coupling.

Q2

C

OUT1

LGATE

COMP

VCC5

GND

C

2

C

1

C

5

R

2

R1

FB

C

R

3

R

4

A multilayer printed circuit board is recommended. Figure 13

shows the connections of the critical components in the

V

FS_DIS

IN2

R

7

converter. Capacitors C and C

could each represent

IN OUT

C

IN2

Q3

numerous physical capacitors. Dedicate one solid layer,

usually a middle layer of the PC board, for a ground plane and

make all critical component ground connections through vias

to this layer. Dedicate another solid layer as a power plane

and break this plane into smaller islands of common voltage

levels. Keep the metal runs from the PHASE terminal to the

output inductor short. The power plane should support the

input and output power nodes. Use copper filled polygons on

the top and bottom circuit layers for the phase node. Use the

remaining printed circuit layers for small signal wiring. The

wiring traces from the LGATE and UGATE pins to the

MOSFET gates should be kept short and wide enough to

easily handle the several Amps of drive current.

LDO_DR

LDO_FB

R5

V

OUT2

R6

C

OUT2

KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 13. PRINTED CIRCUIT BOARD POWER PLANES

AND ISLANDS

References

The critical small signal components include any bypass

capacitors, feedback components, and compensation

Applications Note: AN1201

Visit us on the internet: www.intersil.com

Rev X.00

Page 15 of 18

ISL6549

Quad Flat No-Lead Plastic Package (QFN)

Micro Lead Frame Plastic Package (MLFP)

L16.4x4

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

A

A1

A2

A3

b

0.80

0.90

-

9

0.20 REF

9

0.23

1.95

0.28

0.35

2.25

5, 8

D

4.00 BSC

-

D1

D2

E

3.75 BSC

9

2.10

7, 8

4.00 BSC

-

E1

E2

e

3.75 BSC

9

2.10

7, 8

0.65 BSC

-

k

0.25

0.50

-

L

0.60

0.75

0.15

8

L1

N

-

16

4

-

10

2

Nd

Ne

P

3

-

0.60

12

9



-

9

Rev. 5 5/04

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare providedtoassist with PCB LandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P &  are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

Rev X.00

Page 16 of 18

ISL6549

Small Outline Plastic Packages (SOIC)

M14.15 (JEDEC MS-012-AB ISSUE C)

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC

PACKAGE

N

INDEX

AREA

0.25(0.010)

M

B M

H

E

INCHES

MILLIMETERS

-B-

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

8.55

3.80

MAX

1.75

0.25

0.51

0.25

8.75

4.00

NOTES

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

0.0688

0.0098

0.020

-

1

2

3

L

-

SEATING PLANE

A

9

0.0075

0.3367

0.1497

0.0098

0.3444

0.1574

-

-A-

o

h x 45

D

3

4

-C-



0.050 BSC

1.27 BSC

-

e

A1

C

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

B

0.10(0.004)

5

0.25(0.010) M

C

A M B S

L

6

N



14

7

NOTES:

o

0

8

0

8

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 0 12/93

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension“E”doesnotinclude interlead flash orprotrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

Rev X.00

Page 17 of 18

ISL6549

Shrink Small Outline Plastic Packages (SSOP)

Quarter Size Outline Plastic Packages (QSOP)

M16.15A

N

16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE

(0.150” WIDE BODY)

INDEX

M

B

0.25(0.010)

H

AREA

E

INCHES

MILLIMETERS

GAUGE

PLANE

-B-

SYMBOL

MIN

MAX

MIN

1.55

0.102

1.40

0.20

0.191

4.80

3.81

MAX

1.73

0.249

1.55

0.31

0.249

4.98

3.99

NOTES

A

A1

A2

B

0.061

0.004

0.055

0.008

0.0075

0.189

0.150

0.068

0.0098

0.061

0.012

0.0098

0.196

0.157

-

1

2

3

-

L

-

0.25

0.010

SEATING PLANE

A

9

-A-

D

h x 45°

C

D

E

-

3

-C-

4



A2

e

A1

e

0.025 BSC

0.635 BSC

-

C

B

H

h

0.230

0.010

0.016

0.244

0.016

0.035

5.84

0.25

0.41

6.20

0.41

0.89

-

0.10(0.004)

M

S

B

0.17(0.007)

C

A

5

L

6

NOTES:

N



16

7

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

0°

8°

0°

8°

-

Rev. 2 6/04

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “B” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.10mm (0.004 inch) total in excess

of “B” dimension at maximum material condition.

10. Controlling dimension: INCHES. Converted millimeter dimen-

sions are not necessarily exact.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

Rev X.00

Page 18 of 18


型号：	ISL6549IBZ
厂家：	RENESAS TECHNOLOGY CORP
描述：	SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PDSO14, ROHS COMPLIANT, PLASTIC, MS-012AB, SOIC-14 开关光电二极管
文件：	总18页 (文件大小：849K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6549IBZ [RENESAS]

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