ISL6563CR-T1 [RENESAS]
IC,SMPS CONTROLLER,CURRENT/VOLTAGE,LLCC,24PIN,PLASTIC;
| 型号： | ISL6563CR-T1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,SMPS CONTROLLER,CURRENT/VOLTAGE,LLCC,24PIN,PLASTIC |
| 文件： | 总19页 (文件大小：514K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6563
®
Data Sheet
December 1, 2005
FN9126.7
Two-Phase Multiphase Buck PWM
Features
• Integrated Two-Phase Power Conversion
Controller with Integrated MOSFET Drivers
The ISL6563 two-phase PWM control IC provides a
precision voltage regulation system for advanced
microprocessors. Multiphase power conversion is a marked
departure from single phase converter configurations
employed to satisfy the increasing current demands of
modern microprocessors and other electronic circuits. By
distributing the power and load current, implementation of
multiphase converters utilize smaller and lower cost
transistors with fewer input and output capacitors. These
reductions accrue from the higher effective conversion
frequency with higher frequency ripple current due to the
phase interleaving process of this topology.
• Both 5V and 12V Conversion
• Precision Channel Current Sharing
- Loss Less Current Sampling - Uses r
DS(ON)
• Precision Output Voltage Regulation
- ±1% System Accuracy Over Temperature (Commercial)
• Microprocessor Voltage Identification Inputs
- Up to a 6-Bit DAC
- Selectable between Intel’s VRM9, VRM10, or AMD’s
Hammer DAC codes
- Resistor-Programmable Droop Voltage
• Fast Transient Recovery Time
Outstanding features of this controller IC include
programmable VID codes compatible with Intel VRM9,
VRM10, as well as AMD’s Hammer microprocessors, along
with a system regulation accuracy of ±1%. The droop
characteristic, used to reduce the overshoot or undershoot of
the output voltage, is easily programmed with a single resistor.
• Overcurrent Protection
• Improved, Multi-tiered Overvoltage Protection
• Capable of Start-up into a Pre-Charged Output
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
Important features of this controller IC include a set of
sophisticated overvoltage and overcurrent protection.
Overvoltage results in the converter turning the lower
MOSFETs ON to clamp the rising output voltage and protect
the microprocessor. Like other Intersil multiphase
controllers, the ISL6563 uses cost and space-saving
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
r
sensing for channel current balance, dynamic
DS(ON)
voltage positioning, and overcurrent protection. Channel
current balancing is automatic and accurate with the
integrated current-balance control system. Overcurrent
protection can be tailored to any application with no need for
additional parts. These features provide advanced protection
for the microprocessor and power system.
Pinout
ISL6563 (QFN)
TOP VIEW
24 23 22 21 20 19
Ordering Information
TEMP.
(°C)
PKG.
VID1
VID0
1
2
3
4
5
6
18 PHASE1
PART NUMBER
PACKAGE
DWG. #
17
16
15
LGATE1
PVCC
ISL6563CR
0 to 70 24 Ld 4x4 QFN
L24.4x4B
DACSEL/VID5
VRM10
ISL6563CRZ (Note 1) 0 to 70 24 Ld 4x4 QFN (Pb-free) L24.4x4B
ISL6563IR 0 to 70 24 Ld 4x4 QFN L24.4x4B
ISL6563IRZ (Note 1) 0 to 70 24 Ld 4x4 QFN (Pb-free) L24.4x4B
25
GND
LGATE2
COMP
14 PGND
ISL6563EVAL1
Evaluation Platform
FB
13 PHASE2
NOTES:
7
8
9
10 11
12
1. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-T” suffix for Tape and Reel.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Block Diagram
ENLL
VCC
SSEND
PVCC
BOOT1
OVP WHILE
DISABLED
1.65V/1.95V
+
-
UGATE1
PHASE1
POWER-ON
RESET (POR)
OVP
OSCILLATOR
GATE
CONTROL
+
-
200mV
COMP
LGATE1
PGND
VID0
VID1
VID2
VID3
VID4
PWM1
PWM2
SOFT-START
AND
TTL D/A
CONVERTER
(VID DAC)
FAULT LOGIC
CONTROL
LOGIC
EA
DACSEL/VID5
VRM10
BOOT2
+
OC
Σ
-
UGATE2
PHASE2
Σ
FB
GATE
CONTROL
CURRENT
CORRECTION
Σ
DROOP
LGATE2
SOURCE
OFFSET
SOURCE
GND
Σ
2
OFS
ISEN
ISL6563
Simplified Power System Diagram
+5V
IN
Q1
Q2
CHANNEL1
5-6
VID
DAC
V
OUT
Q3
Q4
CHANNEL2
ISL6563
Typical Application
+12V
IN
L
IN
+5V
IN
C
HFIN1
C
BIN1
C
F2
C
F1
PVCC
VCC
BOOT1
C
BOOT1
DACSEL/VID12
VID4
UGATE1
PHASE1
Q1
VID3
VID2
VID1
L
OUT1
VID0
Q2
VRM10
LGATE1
BOOT2
R
ISEN
ISEN
V
OUT
SSEND
ENLL
OFS
R’
OFS
C
BOOT2
ISL6563
C
C
BOUT
HFOUT
C
HFIN2
C
BIN2
UGATE2
PHASE2
Q3
R
OFS
COMP
C
2
L
OUT2
C
1
LGATE2
Q4
R
2
PGND
GND
FB
R
1
FN9126.7
December 1, 2005
3
ISL6563
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC, PVCC . . . . . . . . . . . . . . . . . . -0.3V to +6.25V
Thermal Resistance
θ
(°C/W)
43
θ
(°C/W)
7
JA
JC
Absolute Boot Voltage, V
. . . . . PGND - 0.3V to PGND + 27V
BOOT
QFN Package (Notes 3, 4). . . . . . . . . .
Phase Voltage, V
. . . . . . . . . . V
- 7V to V
+ 0.3V
+ 0.3V
PHASE
BOOT
BOOT
BOOT
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Upper Gate Voltage, V
Lower Gate Voltage, V
. . . . V
PHASE
- 0.3V to V
UGATE
LGATE
. . . . . . . . PGND - 0.3V to VCC + 0.3V
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . HBM Class 1 JEDEC STD
Recommended Operating Conditions
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
3. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Test Conditions: V = 5V, T = 0°C to 85°C, Unless Otherwise Specified
CC
J
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
BIAS SUPPLY AND INTERNAL OSCILLATOR
Input Bias Supply Current
I
; ENLL = high
VCC
-
4.2
3.7
-
4
6
4.6
4.1
-
mA
V
VCC POR (Power-On Reset) Threshold
VCC Rising
VCC Falling
PVCC Rising
PVCC Falling
4.4
3.9
4.2
3.3
222
205
1.33
66
V
PVCC POR (Power-On Reset) Threshold
V
-
-
V
Switching Frequency (per channel)
(Note 5)
T = 25°C to 85°C
189
166
-
255
241
-
kHz
kHz
V
J
T = -40°C
J
Oscillator Ramp Amplitude (Note 6)
Maximum Duty Cycle (Note 6)
CONTROL THRESHOLDS
ENLL Rising Threshold
V
PP
-
-
%
-
0.61
60
-
-
V
mV
V
ENLL Hysteresis (Note 6)
-
0.23
-
COMP Shutdown Threshold
COMP Shutdown Maximum Pull-Down Impedance
REFERENCE AND DAC
0.36
-
0.49
15
Ω
System Accuracy
-1
-1.5
-
-
-
1
1.5
0.4
-
%
%
V
T = -40°C to 85°C
J
DAC Input Low Voltage
DAC Input High Voltage
DAC Input Pull-Up Current
ERROR AMPLIFIER
-
0.8
-
-
V
VIDx = 0V
45
-
µA
DC Gain (Note 5)
R
C
C
= 10K to ground
-
96
20
-
dB
MHz
V/µs
V
L
L
L
Gain-Bandwidth Product (Note 6)
Slew Rate (Note 6)
= 100pF, R = 10K to ground
L
-
-
= 100pF, Load = ±400µA
-
3.90
-
8
-
-
Maximum Output Voltage
Minimum Output Voltage
Load = 1mA
Load = -1mA
4.20
0.80
0.90
V
FN9126.7
4
December 1, 2005
ISL6563
Electrical Specifications Test Conditions: V = 5V, T = 0°C to 85°C, Unless Otherwise Specified (Continued)
CC
J
PARAMETER
OVERCURRENT PROTECTION
Overcurrent Trip Level
TEST CONDITIONS
MIN
TYP
MAX UNITS
-
95
-
µA
PROTECTION
Overvoltage Threshold while IC Disabled
VRM9.0 configuration
Hammer and VRM10.0 configurations
FB Rising
1.90
1.60
-
1.95
1.65
2.00
1.70
-
V
V
V
Overvoltage Threshold
VID
+200mV
Overvoltage Hysteresis
SWITCHING TIME
-
100
-
mV
UGATE Rise Time (Note 6)
LGATE Rise Time (Note 6)
UGATE Fall Time (Note 6)
LGATE Fall Time (Note 6)
UGATE Turn-On Non-overlap (Note 6)
LGATE Turn-On Non-overlap (Note 6)
OUTPUT
t
t
t
t
t
t
V
= 5V, 3nF Load
= 5V, 3nF Load
= 5V, 3nF Load
= 5V, 3nF Load
-
-
-
-
-
-
8
8
8
4
8
8
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
RUGATE; VCC
V
RLGATE; VCC
V
FUGATE; VCC
V
FLGATE; VCC
; V
= 5V, 3nF Load
= 5V, 3nF Load
PDHUGATE VCC
; V
PDHLGATE VCC
Upper Drive Source Resistance
Upper Drive Sink Resistance
Lower Drive Source Resistance
Lower Drive Sink Resistance
NOTES:
100mA Source Current
100mA Sink Current
100mA Source Current
100mA Sink Current
-
-
-
-
0.5
0.4
0.5
0.3
1.3
1.0
1.3
1.0
Ω
Ω
Ω
Ω
5. Parameter magnitude at T = -40°C determined through characterization.
J
6. Parameter magnitude guaranteed by design.
Timing Diagram
t
PDHUGATE
t
t
FUGATE
RUGATE
UGATE
LGATE
t
t
RLGATE
FLGATE
t
PDHLGATE
GND and PGND (Pins 25 and 14)
Functional Pin Description
VCC (Pin 8)
Bias supply for the IC’s small-signal circuitry. Connect this
pin to a 5V supply and locally decouple using a quality 0.1µF
ceramic capacitor.
Connect these pins to the circuit ground using the shortest
possible paths. All internal small-signal circuitry is
referenced to the GND pin. LGATE drive is referenced to the
PGND pin.
VID0-4 (Pins 2, 1, 24-22)
PVCC (Pin 16)
Power supply pin for the MOSFET drives. Connect this pin to
a 5V supply and locally decouple using a quality 1µF
ceramic capacitor.
Voltage identification inputs from microprocessor. These pins
respond to TTL logic thresholds. The ISL6563 decodes the
VID inputs to establish the output voltage; see VID Tables for
correspondence between DAC codes and output voltage
FN9126.7
5
December 1, 2005
ISL6563
settings. These pins are internally pulled high, to
approximately 1.2V, by 40µA (typically) internal current
sources; the internal pull-up current decrease to 0 as the VID
voltage approaches the internal pull-up voltage. All VID pins
are compatible with external pull-up voltages not exceeding
the IC’s bias voltage.
UGATE1, 2 (Pins 19, 12)
Connect these pins to the upper MOSFETs’ gates. These
pins are used to control the upper MOSFETs and are
monitored for shoot-through prevention purposes. Maximum
individual channel duty cycle is limited to 66%.
BOOT1, 2 (Pins 20, 11)
DACSEL/VID5 (Pin 3)
These pins provide the bias voltage for the upper MOSFETs’
drives. Connect these pins to appropriately-chosen external
bootstrap capacitors. Internal bootstrap diodes connected to
the PVCC pins provide the necessary bootstrap charge.
If VRM10 pin is grounded, DACSEL/VID5 represents the 6th
voltage identification input from the VRM10-compliant
microprocessor, otherwise known as VID5. If VRM10 pin is
open or pulled high, DACSEL/VID5 selects the compliance
standard for the internal DAC: pulled to ground it encodes the
DAC with AMD Hammer VID codes, while left open or pulled
high, it encodes the DAC with Intel VRM9.0 codes.
PHASE1, 2 (Pins 18, 13)
Connect these pins to the sources of the upper MOSFETs.
These pins are the return path for the upper MOSFETs’
drives.
VRM10 (Pin 4)
This pin selects VRM10.0 DAC compliance when grounded.
Left open, it allows selection of either VRM9.0 or Hammer
DAC compliance via DACSEL pin.
LGATE1, 2 (Pins 17, 15)
These pins are used to control the lower MOSFETs and are
monitored for shoot-through prevention purposes. Connect
these pins to the lower MOSFETs’ gates.
ENLL (Pin 21)
This pin is a precision-threshold (approximately 0.6V) enable
pin. Held low, this pin disables controller operation. Pulled
high, the pin enables the controller for operation.
OFS (Pin 9)
This pin is used to create an adjustable output voltage offset.
For no offset, leave this pin open. For negative offset, connect
an R’
resistor from this pin to VCC and size it according to
OFS
FB and COMP (Pins 6, 5)
The internal error amplifier’s inverting input and output
respectively. These pins are connected to the external
network used to compensate the regulator’s feedback loop.
the following equation:
1500
OFFSET
--------------------------
R′
= R
×
OFS
1
V
An internal current source injects the average current
where:
sampled through R
into the FB pin. Pulling COMP to
ISEN
V
= desired output voltage offset magnitude (mV)
OFFSET
ground through an impedance lower than 15Ω disables the
controller (same effect as ENLL pulled low).
For positive output voltage offset, connect an R
from this pin to GND, sizing it according to the following
equation:
resistor
OFS
ISEN (Pin 7)
This pin is used to close the current-feedback loop and set
the overcurrent protection threshold. A resistor connected
between this pin and VCC has a voltage drop forced across
500
OFFSET
--------------------------
R
= R
×
OFS
1
V
it equal to that sampled across the lower MOSFET’s r
DS(ON)
For more information, refer to the ‘Output Voltage Offset
Programming’ paragraph.
during approximately the middle of its conduction interval.
The resulting current through this resistor is used for channel
current balancing, overcurrent protection and is sourced to
the FB pin for load-line regulation. The voltage across the
SSEND (Pin 10)
This pin is an end of Soft-Start (SS) indicator; open drain
output device stays ON during soft-start, and goes open when
soft-start ends.
R
resistor is time multiplexed between the two
ISEN
channels.
Use the following equation to select the proper R
resistor:
ISEN
r
× I
DS(ON)
OUT
R
= ------------------------------------------
50µA
ISEN
where:
r
= lower MOSFET drain-source ON resistance (Ω)
DS(ON)
= channel maximum output current (A)
I
OUT
Read ‘Current Feedback’ paragraph for more information.
FN9126.7
6
December 1, 2005
ISL6563
Current Loop
Operation
The current control loop works in a similar fashion to the
voltage control loop, but with current control information
applied individually to each channel’s Comparator. The
information used for this control is the voltage that is
Figure 1 shows a simplified diagram of the voltage regulation
and current control loops. Both voltage and current feedback
are used to precisely regulate the output voltage and tightly
control the output currents, I and I , of the two power
channels.
L1
L2
developed across the r
of each lower MOSFET, while
DS(ON)
they are conducting. A single resistor converts and scales
the voltage across the MOSFETs to a current that is applied
to the Current Sensing circuit within the ISL6563. Output
from these sensing circuits is applied to the current
averaging circuit. Each PWM channel receives the
difference current signal from the summing circuit that
compares the average sensed current to the individual
channel current. When a power channel’s current is greater
than the average current, the signal applied via the summing
Correction circuit to the Comparator, reduces the output
pulse width of the Comparator to compensate for the
detected “above average” current in that channel.
Voltage Loop
Feedback from the output voltage is applied via resistor R1
to the inverting input of the Error Amplifier. This signal can
drive the Error Amplifier output either high or low, depending
upon the output voltage. Low output voltage makes the
amplifier output move towards a higher output voltage level.
Amplifier output voltage is applied to the positive inputs of
the PWM Circuit comparators via the correction summing
networks. Out-of-phase sawtooth signals are applied to the
two PWM comparators inverting inputs. Increasing Error
Amplifier voltage results in increased Comparator output
duty cycle. This increased duty cycle signal is passed
through the output drivers with no phase reversal to drive the
external upper MOSFETs. Increased duty cycle or ON time
for the upper MOSFET transistors results in increased
output voltage to compensate for the low output voltage
sensed.
Droop Implementation
In addition to controlling each channel’s output current, the
average channel current is used to implement an output
voltage droop characteristic. Internal average channel
current is fed into the FB pin; the voltage thus developed
across R is equal to the droop voltage.
1
DAC
V
OSCILLATOR
IN
&
REFERENCE
UGATE1
ERROR
PWM
CIRCUIT
HALF-BRIDGE
DRIVE
AMP
Σ
LGATE1
COMP
L1
L2
R2
C2
FB
PWM
HALF-BRIDGE
DRIVE
CIRCUIT
Σ
V
C
OUT
PHASE1
V
IN
CURRENT
SENSE
Σ
Σ
OUT
R1
UGATE2
LGATE2
AVERAGE
DROOP
SOURCE, I
FB
CURRENT
SENSE
PHASE2
ISEN
R
VCC
ISEN
FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6563 VOLTAGE AND CURRENT CONTROL LOOPS
FN9126.7
7
December 1, 2005
ISL6563
Assuming identical power switch selection on the two
channels, the following equation determines the current fed
out the FB pin for output voltage droop generation:
To understand the reduction of ripple current amplitude in the
multiphase circuit, examine the equation representing an
individual channel’s peak-to-peak inductor current.
r
⋅ I
(V – V
) ⋅ V
OUT OUT
DS(ON) PHASE
IN
I
I
= ------------------------------------------------
= ---------------------------------------------------------
L ⋅ f ⋅ V
L, PP
FB
R
ISEN
S
IN
where, r
- lower MOSFET/s’ ON resistance (@5V)
DS(ON)
- average phase current
V
and V
are the input and output voltages,
OUT
IN
respectively, L is the single-channel inductor value, and f is
S
I
PHASE
the switching frequency.
Multiphase Power Conversion
The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each
Multiphase power conversion provides a cost-effective
power solution when load currents are no longer easily
supported by single-phase converters. Although its greater
complexity presents additional technical challenges, the
multiphase approach offers cost-saving advantages with
improved response time, superior ripple cancellation, and
thermal distribution.
of the individual channels. Peak-to-peak ripple current, I
,
PP
(V – N ⋅ V
) ⋅ V
OUT
IN
OUT
I
= -------------------------------------------------------------------
L ⋅ f ⋅ V
PP
S
IN
INTERLEAVING
decreases by an amount proportional to the number of
The switching of each channel in an ISL6563-based
converter is timed to be symmetrically out of phase with the
other channel. As a result, the two-phase converter has a
combined ripple frequency twice the frequency of one of its
phases. In addition, the peak-to-peak amplitude of the
combined inductor currents is proportionately reduced.
Increased ripple frequency and lower ripple amplitude
generally translate to lower per-channel inductance and
lower total output capacitance for a given set of performance
specifications.
channels. Output-voltage ripple is a function of capacitance,
capacitor equivalent series resistance (ESR), and inductor
ripple current. Reducing the inductor ripple current allows
the designer to use fewer or less costly output capacitors
(should output ripple be an important design parameter).
C
CURRENT
IN
Q1 D-S CURRENT
I
+ I
L2
L1
Q3 D-S CURRENT
I
L2
PWM2
I
L1
FIGURE 3. INPUT CAPACITOR CURRENT AND INDIVIDUAL
CHANNEL CURRENTS IN A 2-PHASE
CONVERTER
PWM1
Another benefit of interleaving is the reduction of input ripple
current. Input capacitance is determined in a large part by
the maximum input ripple current. Multiphase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 3 illustrates input
currents from a two-phase converter combining to reduce
the total input ripple current.
FIGURE 2. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 2-PHASE CONVERTER
Figure 2 illustrates the additive effect on output ripple
frequency. The two channel currents (I and I ), combine
L1
L2
to form the AC ripple current and the DC load current. The
ripple component has two times the ripple frequency of each
individual channel current.
FN9126.7
8
December 1, 2005
ISL6563
Figure 11, part of the section entitled Input Capacitor
Selection, can be used to determine the input-capacitor
RMS current based on load current and duty cycle. The
figure is provided as an aid in determining the optimal input
capacitor solution.
modifies the pulse width to correct any unbalance and force
the error toward zero.
OVERCURRENT PROTECTION
The individual channel currents, as sensed via the PHASE
pins and scaled via the ISEN resistor, are continuously
monitored and compared with an internal 95µA reference
current. If both channels’ currents exceed, at any time, the
reference current, the overcurrent comparator triggers an
overcurrent event. Similarly, an OC event is also triggered if
either channel’s current exceeds the 95µA reference for 7
consecutive switching cycles.
PWM OPERATION
One switching cycle for the ISL6563 is defined as the time
between consecutive PWM pulse terminations (turn-off of
the upper MOSFET on a channel). Each cycle begins when
a switching clock signal commands the upper MOSFET to
go off. The other channel’s upper MOSFET conduction is
terminated 1/2 of a cycle later.
As a result of an OC event, output drives on both channels
turn off both upper and lower MOSFETs. The system then
waits in this state for a period of 4096 switching clock cycles.
Once a channel’s upper MOSFET is turned off, the lower
MOSFET remains on for a minimum of 1/3 cycle. This forced
off time is required to assure an accurate current sample.
Following the 1/3-cycle forced off time, the controller enables
the upper MOSFET output. Once enabled, the upper
MOSFET output transitions high when the sawtooth signal
crosses the adjusted error-amplifier output signal, as
illustrated in the ISL6563’s block diagram. Just prior to the
upper drive turning the MOSFET on, the lower MOSFET
drive turns the freewheeling element off. The upper
The wait period is followed by a soft-start attempt. If the soft-
start attempt is successful, operation continues as normal.
Should the soft-start attempt fail, the ISL6563 repeats the
2048-cycle wait period and follows with another soft-start
attempt. This hiccup mode of operation continues indefinitely
(as depicted in Figure 4) for as long as the controller is
enabled or until the overcurrent condition is removed.
MOSFET is kept on until the clock signals the beginning of
the next switching cycle and the PWM pulse is terminated.
CURRENT SENSING
ISL6563 senses current by sampling the voltage across the
lower MOSFET during its conduction interval. MOSFET
OUTPUT CURRENT
r
sensing is a no-added-cost method to sense current
DS(ON)
for load line regulation, channel current balance, module
current sharing, and overcurrent protection.
The PHASE pins are used as inputs for each channel.
OUTPUT VOLTAGE
Internal circuitry samples the lower MOSFETs’ r
DS(ON)
voltage, once each cycle, during their conduction periods
and time multiplexes the sampled voltages across the ISEN
resistor. The current that is thus developed through the ISEN
resistor is duplicated and fed back through the FB pin to
create droop, as well as used for channel current balancing.
FIGURE 4. OVERCURRENT BEHAVIOR IN HICCUP MODE
OUTPUT VOLTAGE SETTING
CHANNEL-CURRENT BALANCE
Another benefit of multiphase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this, the
designer avoids the complexity of driving multiple parallel
MOSFETs and the expense of using expensive heat sinks
and exotic magnetic materials.
The ISL6563 uses a digital to analog converter (DAC) to gen-
erate a reference voltage based on the logic signals at the
VID pins. The DAC decodes the 5 or 6-bit logic signals into
one of the discrete voltages shown in Tables 1 - 3. Each VID
pin is pulled up to an internal 1.2V voltage by weak current
sources (about 45µA current, decreasing to 0 as the voltage
at the VID pins varies from 0 to the internal 1.2V pull-up volt-
age). External pull-up resistors or active-high output stages
can augment the pull-up current sources, up to a voltage of
5V.
In order to fully realize the thermal advantage, it is important
that each channel in a multiphase converter be controlled to
deliver about the same current at any load level. Intersil
multiphase controllers ensure current balance by comparing
each channel’s current to the average current delivered by
all channels and making appropriate adjustments to each
channel’s pulse width based on the error. The error signal
.
The ISL6563 accommodates three different DAC ranges:
Intel VRM9.0, AMD Hammer, or Intel VRM10.0 - see
Functional Pin Description for proper connections for DAC
range compatibility.
FN9126.7
9
December 1, 2005
ISL6563
TABLE 1. AMD HAMMER VOLTAGE IDENTIFICATION CODES
TABLE 2. VRM9 VOLTAGE IDENTIFICATION CODES
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VDAC
Off
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VDAC
Off
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
FN9126.7
10
December 1, 2005
ISL6563
TABLE 3. VRM10 VOLTAGE IDENTIFICATION CODES
TABLE 3. VRM10 VOLTAGE IDENTIFICATION CODES
(Continued)
VID4
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID2
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID1
1
1
1
0\
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID5
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VDAC
Off
VID4
1
VID3
0
VID2
0
VID1
1
VID0
1
VID5
1
VDAC
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1.4500
1.4625
1.4750
1.4875
1.5000
1.5125
1.5250
1.5375
1.5500
1.5625
1.5750
1.5875
1.6000
Off
1
0
0
1
1
0
0.8375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
1.0750
1.0875
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.300
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
1
0
1
1
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
0
0
1
0
1
1
1
0
1
0
1
1
0
0
1
0
1
0
1
DYNAMIC VID (VID-ON-THE-FLY)
The ISL6563 is capable of executing on-the-fly output
voltage changes. The way the ISL6563 reacts to a change in
the VID code is dependent on the VID configuration. In
VRM9 or AMD Hammer settings, the ISL6563 checks for a
change in the VID code four times each switching cycle. The
VID code is the bit pattern present at pins VID4-VID0. If a
new code is established and it stays the same for 12
switching cycles, the ISL6563 begins changing the reference
by making one step change every four switching cycles until
it reaches the new VID code. Figure 5 depicts such a
transition, from 1.5V to 1.7V
00110
01110
V
VID
VID CHANGE OCCURS HERE
V
(100mV/DIV)
(100mV/DIV)
REF
1.5V
V
OUT
1.5V
1.3125
1.3250
1.3375
1.3500
1.3625
FIGURE 5. TYPICAL DYNAMIC-VID OPERATION, VRM9 DAC
SETTING
FN9126.7
11
December 1, 2005
ISL6563
In VRM10 setting, the ISL6563 checks for a change in the
VID code six times each switching cycle. If a new code is
established and it stays the same for 3 consecutive
readings, the ISL6563 recognizes the change and
increments the reference. Specific to VRM10, the processor
controls the VID transitions and is responsible for
incrementing or decrementing one VID step at a time. In
VRM10 setting, the ISL6563 will immediately change the
reference to the new requested value as soon as the request
is validated; in cases where the reference step is too large,
the sudden change can trigger overcurrent or overvoltage
events.
In any of the described post-POR functionality, OVP results
in the turn-on of the lower MOSFETs. Once turned on, the
lower MOSFETs are only turned off when the output voltage
drops below the OV comparator’s hysteretic threshold. The
OVP process repeats if the voltage rises back above the
designated threshold. The occurrence of an OVP event does
not latch the controller; should the phenomenon be
transitory, the controller resumes normal operation following
such an event.
LOAD-LINE REGULATION
In applications with high transient current slew rates, the
lowest-cost solution for maintaining regulation often requires
some kind of controlled output impedance. The FB pin of the
ISL6563 carries a current proportional to the average output
In non-VRM10 settings, due to the way the ISL6563
recognizes VID code changes, up to one full switching
period may pass before a VID change registers. Thus, the
current of the converter. The current is equivalent to I in
FB
total time required for a VID change, t
, is dependent on
DVID
Figure 1. Forcing I into the summing node of the error
FB
the switching frequency (f ), the size of the change (∆V ),
S
ID
amplifier produces a voltage drop across the feedback
and the time required to register the VID change. The
resistor, R , proportional to the output current. Assuming
FB
approximate time required for an ISL6563-based converter
the current is shared equally by both phases, the steady-
in VRM9 configuration running at typical f (222kHz) to
S
state value of V
is simply:
DROOP
perform a 1.5V-to-1.7V reference voltage change is about
196µs, as calculated using the following equation (this
example is also illustrated in Figure 5).
V
V
= I ⋅ R
FB
DROOP
DROOP
FB
I
⋅ r
4∆V
0.025
OUT DS(ON)LMOS
1
S
VID
---------------------------------------------------------
=
⋅ R
FB
----
t
≅
+ 13
--------------------
DVID
2 ⋅ R
f
ISEN
ON/OFF CONTROL
OVERVOLTAGE PROTECTION
The internal power-on reset circuit (POR) prevents the
ISL6563 from starting before the bias voltage at VCC and
PVCC reach the rising POR thresholds, as defined in
Electrical Specifications. The POR levels are sufficiently high
to guarantee that all parts of the ISL6563 can perform their
functions properly once bias is applied to the part. While bias
is below the rising POR thresholds, the controlled MOSFETs
are kept in an off state.
The ISL6563 benefits from a multi-tiered approach to
overvoltage protection.
A pre-POR mechanism is at work while the chip does not
have sufficient bias voltage to initiate an active response to
an OV situation. Thus, while VCC is below its POR level, the
lower drives are tristated and internal 5kΩ (typically)
resistors are connected from PHASE to their respective
LGATE pins. As a result, output voltage, duplicated at the
PHASE nodes via the output inductors, is effectively
clamped at the lower MOSFETs’ threshold level. This
approach ensures no catastrophic output voltage can be
developed at the output of an ISL6563-based regulator (for
most typical applications).
ISL6563
EXTERNAL CIRCUIT
+5V
+12V
VCC
15kΩ
The pre-POR mechanism is removed once the bias is above
the POR level, and a fixed-threshold OVP goes into effect.
Based on the specific chip configuration, the OVP goes into
effect once the voltage sensed at the FB pin exceeds about
1.65V (Hammer/VR10) or 1.95V (VR9 configuration). Should
the output voltage exceed these thresholds, the lower
MOSFETs are turned on.
ENABLE
COMPARATOR
+
-
POR
CIRCUIT
ENLL
OFF
ON
1kΩ
0.61V
During soft-start, the OVP threshold changes to the higher of
the fixed threshold (1.65V/1.95V) or the DAC setting plus
200mV. At the end of the soft-start, the OVP threshold
changes to the DAC setting plus 200mV.
FIGURE 6. START-UP COORDINATION USING THRESHOLD-
SENSITIVE ENABLE (ENLL) PIN
A secondary disablement feature is available via the
threshold-sensitive enable input (ENLL). This optional
feature prevents the ISL6563 from operating until a certain
FN9126.7
12
December 1, 2005
ISL6563
other voltage rail is available and above some selectable
threshold. For example, when down-converting off a 12V
OUTPUT PRECHARGED
ABOVE DAC LEVEL
input, it may be desirable the ISL6563-based converter does
not start up until the power input is sufficiently high. The
schematic in Figure 6 demonstrates coordination of the
ISL6563 with such a rail; the resistor components are
chosen to enable the ISL6563 as the 12V input exceeds
approximately 9.75V. Additionally, an open-drain or open-
collector device can be used to wire-AND a second (or
multiple) control signal, as shown in Figure 6. To defeat the
threshold-sensitive enable, connect ENLL to VCC directly or
via a pull-up resistor.
OUTPUT PRECHARGED
BELOW DAC LEVEL
V
(0.5V/DIV)
GND>
GND>
OUT
ENLL (5V/DIV)
The ‘11111’ VID code is reserved as a signal to the controller
that no load is present. The controller is disabled while
receiving this VID code and will subsequently start up upon
receiving any other code.
T1 T2
T3
FIGURE 7. SOFT-START WAVEFORMS FOR ISL6563-BASED
MULTIPHASE CONVERTER
In summary, for the ISL6563 to operate, the following
conditions need be met: VCC and PVCC must be greater
than their respective POR thresholds, the voltage at ENLL
must be greater than 0.61V, and VID has to be different than
‘11111’. Once all these conditions are met, the controller
immediately initiates a soft start sequence.
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts for all common microprocessor
applications.
SOFT-START
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. Following a delay of 16 PHASE clock cycles (about
70µs) between enabling the chip and the start of the ramp,
the output voltage progresses at a fixed rate of 12.5mV per
16 PHASE clock cycles.
MOSFETs
Given the fixed switching frequency of the ISL6563 and the
integrated output drives, the selection of MOSFETs revolves
closely around the current each MOSFET is required to
conduct, the capability of the devices to dissipate heat, as well
as the characteristics of available heat sinking. Since the
ISL6563 drives the MOSFETs with 5V, the selection of
appropriate MOSFETs should be done by comparing and
Thus, the soft-start period (not including the 70µs wait) up to
a given voltage, V
equation
, can be approximated by the following
DAC
V
⋅ 1280
DAC
T
= ---------------------------------
SS
f
S
evaluating their characteristics at this specific V
voltage.
bias
GS
where V
is the DAC-set VID voltage, and f is the
S
DAC
switching frequency (typically 222kHz).
LOWER MOSFET POWER CALCULATION
The ISL6563 also has the ability to start up into a pre-
charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output
to ramp from the pre-charged level to the final level dictated
by the DAC setting. Should the output be pre-charged to a
level exceeding the DAC setting, the output drives are
enabled at the end of the soft-start period, leading to an
abrupt correction in the output voltage down to the DAC-set
level.
Since virtually all of the heat loss in the lower MOSFET is
conduction loss (due to current conducted through the
channel resistance, r
), a quick approximation for heat
DS(ON)
dissipated in the lower MOSFET can be found in the
following equation:
2
2
I
I
(1 – D)
L
,PP
OUT
P
= r
(1 – D) + --------------------------------
-------------
LMOS1
DS(ON)
12
2
where: I is the maximum continuous output current, I
L,PP
is
M
the peak-to-peak inductor current, and D is the duty cycle
(approximately V /V ).
OUT IN
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
FN9126.7
13
December 1, 2005
ISL6563
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I , V ; the switching
Lastly, the conduction loss part of the upper MOSFET’s
power dissipation, P
can be calculated using the
M
D(ON)
UMOS,4,
frequency, f ; and the length of dead times, t and t , at
following equation:
S
d1
d2
the beginning and the end of the lower-MOSFET conduction
interval, respectively.
2
2
I
12
I
PP
OUT
P
= r
d +
---------
-------------
UMOS,4
DS(ON)
2
I
I
OUT
I
I
PP
OUT
PP
P
= V
f
D(ON) S
t
d1
t
d2
+
------------- + --------
------------- – --------
LMOS 2
2
2
2
2
In this case, of course, r
upper MOSFET.
is the ON resistance of the
DS(ON)
The above equation assumes the current through the lower
MOSFET is always positive; if so, the total power dissipated
in each lower MOSFET is approximated by the summation of
The total power dissipated by the upper MOSFET at full load
can be approximated as the summation of these results.
Since the power equations depend on MOSFET parameters,
choosing the correct MOSFETs can be an iterative process
that involves repetitively solving the loss equations for
different MOSFETs and different switching frequencies until
converging upon the best solution.
P
and P
.
LMOS1
UPPER MOSFET POWER CALCULATION
In addition to r losses, a large portion of the upper-
LMOS2
DS(ON)
MOSFET losses are switching losses, due to currents
conducted through the device while the input voltage is
Current Sensing
The resistor connected between the ISEN and VCC pins
determines the gain in the load-line regulation and the
channel-current balance loop. Select the value for this
present as V . Upper MOSFET losses can be divided into
DS
separate components, separating the upper-MOSFET
switching losses, the lower-MOSFET body diode reverse
recovery charge loss, and the upper MOSFET r
conduction loss.
DS(ON)
resistor based on the room temperature r
of the lower
FL
DS(ON)
MOSFETs and the full-load total output current, I
.
r
I
In most typical circuits, when the upper MOSFET turns off, it
continues to conduct the inductor current until the voltage at
the phase node falls below ground. Once the lower
DS(ON) FL
----------------------- -------
R
=
⋅
ISEN
–
6
2
50 ×10
MOSFET begins conducting (via its body diode or
Load Line Regulation Resistor
enhancement channel), the current in the upper MOSFET
falls to zero. In the following equation, the required time for
The load-line regulation resistor is labeled, R1 in Figure 1,
depends on the desired full-load droop voltage. At full load,
this commutation is t and the associated power loss is
1
the current determined by R
is fed into the FB pin and
ISEN
P
.
UMOS,1
creates the output voltage droop across R1. Thus, the load
line regulation resistor can be computed using the following
equation:
t
2
I
I
L
1
OUT
,PP
P
≈ V
f
S
----
------------- + -------------
UMOS,1
IN
2
2
V
⋅ 2 ⋅ R
DROOP
ISEN
R
= ------------------------------------------------------
1
r
⋅ I
DS(ON) FL
Similarly, the upper MOSFET begins conducting as soon as
it begins turning on. Assuming the inductor current is in the
positive domain, the upper MOSFET sees approximately the
input voltage applied across its drain and source terminals,
while it turns on and starts conducting the inductor current.
Frequency Compensation
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output filter LC resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
This transition occurs over a time t , and the approximate
2
the power loss is P
.
UMOS,2
t
2
I
I
L
2
OUT
,PP
P
≈ V
f
S
----
------------- – -------------
UMOS,2
IN
2
2
compensation components, R and C .
2
2
The solution to the system equations can be fairly
complicated. Fortunately, there is a simple approximation
that comes very close to an optimal solution. Treating the
system as though it were a voltage mode regulator by
compensating the LC poles and the ESR zero of the voltage
mode approximation yields a solution that is always stable
with very close to ideal transient performance.
A third component involves the lower MOSFET’s reverse-
recovery charge, Q . Since the lower MOSFET’s body
RR
diode conducts the full inductor current before it has fully
switched to the upper MOSFET, the upper MOSFET has to
provide the charge required to turn off the lower MOSFET’s
body diode. This charge is conducted through the upper
MOSFET across VIN, the power dissipated as a result,
P
can be approximated as:
UMOS,3
P
= V
Q f
UMOS,3
IN rr S
FN9126.7
14
December 1, 2005
ISL6563
V
is the peak-to-peak sawtooth signal amplitude (see
C
PP
1
Electrical Specifications).
Once selected, the compensation values assure a stable
C
2
R
2
COMP
FB
converter with reasonable transient performance. C is
1
needed to cut down the high frequency error amplifier gain
and reduce the noise the PWM comparator sees. Keep a
position available for C , and install a 10pF to 47pF in case
1
jitter is noted.
+
R
V
1
DROOP
Output Filter Design
-
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
square wave voltage at the phase nodes. Additionally, the
output capacitors must also provide the energy required by a
fast transient load during the short interval of time required
by the controller and power train to respond. Because it has
a low bandwidth compared to the switching frequency, the
output filter limits the system transient response leaving the
output capacitor bank to supply the load current or sink the
inductor currents, all while the current in the output inductors
increases or decreases to meet the load demand.
V
OUT
FIGURE 8. COMPENSATION CONFIGURATION FOR ISL6563
CIRCUIT
The feedback resistor, R , has already been chosen as
1
outlined in Load Line Regulation. Select a target bandwidth
for the compensated system, f . The target bandwidth must
0
be large enough to ensure adequate transient performance,
but smaller than 1/3 of the per-channel switching frequency
(75kHz in this case). The values of the compensation
components depend on the relationships of f to the output
0
In high-speed converters, the output capacitor bank is
amongst the costlier (and often the physically largest) parts
of the circuit. Output filter design begins with consideration
of the critical load parameters: maximum size of the load
step, ∆I, the load-current slew rate, di/dt, and the maximum
allowable output voltage deviation under transient loading,
filter, LC, double pole frequency and the ESR zero frequency
of the bulk output capacitor bank. For each of the three
cases defined below, there is a separate set of equations for
the compensation components.
1
Case 1:
-----------------------
> f
0
2π ⋅ LC
∆V
. Capacitors are characterized according to their
MAX
capacitance, ESR, and ESL (equivalent series inductance).
2π ⋅ f ⋅ V
⋅
LC
0
PP
------------------------------------------------
R
= R
⋅
2
1
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates according to
the following equation:
0.66 ⋅ V
IN
0.66 ⋅ V
IN
C
= ------------------------------------------------
2
2π ⋅ V
⋅ R ⋅ f
PP
FB
0
1
1
Case 2:
-----------------------
---------------------------------
≤ f
≤
0
2π ⋅ C ⋅ ESR
2π ⋅ LC
2
2
V
⋅ (2π) ⋅ f ⋅ LC
0
PP
----------------------------------------------------
R
= R
⋅
2
2
1
0.66 ⋅ V
IN
0.66 ⋅ V
IN
C
= --------------------------------------------------------------------
2
2
di
(2π) ⋅ f ⋅ V
⋅ R
⋅
LC
----
∆V ≈ (ESL) + (ESR) ∆I
0
PP
1
dt
1
Case 3:
---------------------------------
f
>
0
2π ⋅ C ⋅ ESR
The filter capacitor must have sufficiently low ESL and ESR
so that ∆V < ∆V
.
MAX
2π ⋅ f ⋅ V
⋅ L
PP
0
-------------------------------------------
R
C
= R
⋅
2
1
0.66 ⋅ V ⋅ ESR
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
IN
0.66 ⋅ V ⋅ ESR ⋅
C
IN
= --------------------------------------------------------
2
2π ⋅ V
⋅ R ⋅ f
0
⋅
L
PP
1
In the previous equations, L is the per-channel filter
inductance divided by the number of active channels, C is
the total bulk output capacitance, ESR is the equivalent
series resistance of the bulk output filter capacitance, and
FN9126.7
15
December 1, 2005
ISL6563
The ESR of the bulk capacitors is also responsible for the
majority of the output-voltage ripple. As the bulk capacitors
sink and source the inductor ac ripple current, a voltage
components are the most critical because they switch large
amounts of energy. Next are small signal components that
connect to sensitive nodes or supply critical bypassing
current and signal coupling.
develops across the bulk-capacitor ESR equal to I . Thus,
PP
once the output capacitors are selected and a maximum
Note that as the ISL6563 does not allow external adjustment
of the channel-to-channel current balancing (current
allowable ripple voltage, V
, is determined from an
PP(MAX)
analysis of the available output voltage budget, the following
equation can be used to determine a lower limit on the
output inductance.
information is multiplexed across a single R
resistor), it
ISEN
is important to have a symmetrical layout, preferably with the
controller equidistantly located from the two power trains it
controls. Equally important are the gate drive lines (UGATE,
LGATE, PHASE): since they drive the power train MOSFETs
using short, high current pulses, it is important to size them
accordingly and reduce their overall impedance. Equidistant
placement of the controller to the two power trains also helps
keeping these traces equally long (equal impedances,
resulting in similar driving of both sets of MOSFETs).
(V – 2 ⋅ V
) ⋅ V
IN
OUT
OUT
----------------------------------------------------------------
L ≥ ESR ⋅
f
⋅ V ⋅ V
S
IN PP(MAX)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
The power components should be placed first. Locate the
input capacitors close to the power switches. Minimize the
∆V
. This places an upper limit on inductance.
MAX
4 ⋅ C ⋅ V
OUT
length of the connections between the input capacitors, C
and the power switches. Locate the output inductors and
output capacitors between the MOSFETs and the load.
,
IN
--------------------------------
L ≤
⋅ (∆V
– ∆I ⋅ ESR)
MAX
2
(∆I)
While the previous equation addresses the leading edge, the
following equation gives the upper limit on L for cases where
the trailing edge of the current transient causes a greater
output voltage deviation than the leading edge.
Locate the high-frequency decoupling capacitors (ceramic)
as close as practicable to the decoupling target, making use
of the shortest connection paths to any internal planes, such
as vias to GND immediately next, or even onto the capacitor
solder pad.
2.5 ⋅ C
----------------
2
L ≤
⋅ (∆V
– ∆I ⋅ ESR) ⋅ (V – V
O
)
MAX
IN
The critical small components include the bypass capacitors
(∆I)
for VCC and PVCC. Locate the bypass capacitors, C
,
BP
Normally, the trailing edge dictates the selection of L, since
duty cycles are usually less than 50%. Nevertheless, both
inequalities should be evaluated, and L should be selected
based on the lower of the two results. In all equations in this
paragraph, L is the per-channel inductance and C is the total
output bulk capacitance.
close to the device. It is especially important to locate the
components associated with the feedback circuit close to
their respective controller pins, since they belong to a high-
impedance circuit loop, sensitive to EMI pick-up. It is
important to place the R
terminal of the ISL6563.
resistor close to the respective
ISEN
A multi-layer printed circuit board is recommended. Figure 9
shows the connections of the critical components for one
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
output channel of the converter. Note that capacitors C
xxIN
and C could each represent numerous physical
capacitors. Dedicate one solid layer, usually the one
xxOUT
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit
and lead to device overvoltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turnoff
transition of the upper PWM MOSFET. Prior to turnoff, the
upper MOSFET was carrying channel current. During the
turnoff, current stops flowing in the upper MOSFET and is
picked up by the lower MOSFET. Any inductance in the
switched current path generates a large voltage spike during
the switching interval. Careful component selection, tight
layout of the critical components, and short, wide circuit
traces minimize the magnitude of voltage spikes.
underneath the component side of the board, for a ground
plane and make all critical component ground connections
with vias to this layer. Dedicate another solid layer as a power
plane and break this plane into smaller islands of common
voltage levels. Keep the metal runs from the PHASE terminal
to inductor L
short. The power plane should support the
OUT
input power and output power nodes. Use copper filled
polygons on the top and bottom circuit layers for the phase
nodes. Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the IC to the MOSFETs’ gates
and sources should be sized to carry at least one ampere of
current (0.02” to 0.05”).
There are two sets of critical components in a DC-DC
converter using an ISL6563 controller. The power
FN9126.7
16
December 1, 2005
ISL6563
High frequency decoupling capacitors should be placed as
Component Selection Guidelines
close to the power pins of the load, or for that reason, to any
decoupling target they are meant for, as physically possible.
Attention should be paid as not to add inductance in the
circuit board wiring that could cancel the usefulness of these
low inductance components. Consult with the manufacturer
of the load on specific decoupling requirements.
Output Capacitor Selection
The output capacitor is selected to meet both the dynamic
load requirements and the voltage ripple requirements. The
load transient a microprocessor impresses is characterized
by high slew rate (di/dt) current demands. In general,
multiple high quality capacitors of different size and dielectric
are paralleled to meet the design constraints.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage
and the initial voltage drop following a high slew-rate
transient’s edge. In most cases, multiple capacitors of small
case size perform better than a single large case capacitor.
Should the load be characterized by high slew rates, attention
should be particularly paid to the selection and placement of
high-frequency decoupling capacitors (MLCCs, typically -
multi-layer ceramic capacitors). High frequency capacitors
supply the initially transient current and slow the load rate-of-
change seen by the bulk capacitors. The bulk filter capacitor
values are generally determined by the ESR (effective series
resistance) and capacitance requirements.
Bulk capacitor choices include aluminum electrolytic, OS-Con,
Tantalum and even ceramic dielectrics. An aluminum
electrolytic capacitor’s ESR value is related to the case size
+12V
IN
L
IN
+5V
IN
(C
)
C
HFIN1
BIN1
(C
)
F2
(C
)
F1
PVCC
VCC
BOOT1
C
BOOT1
DACSEL/VID12
VID4
UGATE1
Q1
Q2
VID3
VID2
VID1
VID0
L
OUT1
PHASE1
VRM10
LGATE1
BOOT2
R
ISEN
ISEN
V
OUT
SSEND
ENLL
OFS
C
R’
BOOT2
OFS
ISL6563
C
BOUT
(C
)
HFOUT
C
BIN2
UGATE2
PHASE2
(C
)
HFIN2
Q3
Q4
R
OFS
COMP
C
2
L
OUT2
C
1
LGATE2
PGND
LOCATE NEAR LOAD;
R
2
(MINIMIZE CONNECTION PATH)
FB
R
LOCATE NEAR SWITCHING TRANSISTORS;
(MINIMIZE CONNECTION PATH)
GND
1
KEY
LOCATE CLOSE TO IC
(MINIMIZE CONNECTION PATH)
HEAVY TRACE ON CIRCUIT PLANE LAYER
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 9. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
FN9126.7
December 1, 2005
17
ISL6563
with lower ESR available in larger case sizes. However, the
equivalent series inductance (ESL) of these capacitors
increases with case size and can reduce the usefulness of the
capacitor to high slew-rate transient loading. Unfortunately,
ESL is not a specified parameter. Consult the capacitor
manufacturer and/or measure the capacitor’s impedance with
frequency to help select a suitable component.
Input Capacitor Selection
The important parameters for the bulk input capacitors are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and
largest RMS current required by the circuit. The capacitor
voltage rating should be at least 1.25 times greater than the
maximum input voltage. The input RMS current required for
a multiphase converter can be approximated with the aid of
Figure 11.
Output Inductor Selection
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. In a multiphase converter, small inductors reduce
the response time with less impact to the total output ripple
current (as compared to single-phase converters).
0.3
0.2
0.1
The output inductor of each power channel controls the
ripple current. The control IC is stable for channel ripple
current (peak-to-peak) up to twice the average current. A
single channel’s ripple current is approximated by:
V
– V
V
V
IN
IN
OUT
×
OUT
------------------------------- ---------------
I
=
L, PP
F
⋅ L
SW
I
= 0
L,PP
The current from multiple channels tend to cancel each other
and reduce the total ripple current. The total output ripple
current can be determined using the curve in Figure 10; it
provides the total ripple current as a function of duty cycle
and number of active channels, normalized to the parameter
I
I
= 0.5 x I
= 0.75 x I
O
L,PP
O
L,PP
0
0
0.1
0.2
0.3
0.4
0.5
DUTY CYCLE (V /V
)
IN
O
K
at zero duty cycle.
NORM
FIGURE 11. NORMALIZED INPUT RMS CURRENT vs DUTY
CYCLE FOR A 2-PHASE CONVERTER
V
OUT
K
= --------------------
NORM
L ⋅ F
SW
As the input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs, their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs. Figure 11 can be used to determine the input-
capacitor RMS current function of duty cycle, maximum
where L is the channel inductor value.
Find the intersection of the active channel curve and duty
cycle for your particular application. The resulting ripple
current multiplier from the y-axis is then multiplied by the
normalization factor, K
, to determine the total output
NORM
ripple current for the given application.
sustained output current (I ), and the ratio of the peak-to-
O
L,PP
peak inductor current (I
) to the maximum sustained load
∆I
= K
⋅ K
TOTAL
NORM
CM
current, I . Figure 11 can also be used as a reference
O
demonstrating the dramatic reduction in input capacitor RMS
current in a 2-phase DC/DC converter, as compared to a
single-phase regulator.
1.0
0.8
0.6
0.4
0.2
0
Use a mix of input bypass capacitors to control the input
voltage ripple. Use ceramic capacitance for the high
frequency decoupling and bulk capacitors to supply the
RMS current. Minimize the connection path inductance of
the high frequency decoupling ceramic capacitors (from
drain of upper MOSFET to source of lower MOSFET).
For bulk capacitance, several electrolytic or high-capacity MLC
capacitors may be needed. For surface mount designs, solid
tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surge-
current at power-up.
0.1
0.2
0.3
0.4
0.5
0
DUTY CYCLE (V /V
)
IN
O
FIGURE 10. RIPPLE CURRENT vs DUTY CYCLE
FN9126.7
18
December 1, 2005
ISL6563
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L24.4x4B
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VGGD-2 ISSUE C)
MILLIMETERS
SYMBOL
MIN
0.80
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.90
-
-
-
-
-
-
9
0.20 REF
9
0.18
2.19
2.19
0.23
0.30
2.49
2.49
5, 8
D
4.00 BSC
-
D1
D2
E
3.75 BSC
9
2.34
7, 8
4.00 BSC
-
E1
E2
e
3.75 BSC
9
2.34
7, 8
0.50 BSC
-
k
0.25
0.30
-
-
-
-
L
0.40
0.50
0.15
8
L1
N
-
24
6
6
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
θ
-
9
Rev. 0 10/03
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9126.7
19
December 1, 2005
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