ISL6594BCBZ-T [RENESAS]
Advanced Synchronous Buck MOSFET Driver with 3V PWM Interface and Advanced Protection Features; DFN10, SOIC8; Temp Range: 0° to 70°;
| 型号： | ISL6594BCBZ-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Advanced Synchronous Buck MOSFET Driver with 3V PWM Interface and Advanced Protection Features; DFN10, SOIC8; Temp Range: 0° to 70° 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总11页 (文件大小：608K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL6594A, ISL6594B
Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features
FN9157
Rev 6.00
Sep 11, 2015
The ISL6594A and ISL6594B are high frequency MOSFET
drivers specifically designed to drive upper and lower power
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
N-Channel MOSFETs in a synchronous rectified buck
converter topology. These drivers combined with the
ISL6592 Digital Multi-Phase Buck PWM controller and
N-Channel MOSFETs form a complete core-voltage
regulator solution for advanced microprocessors.
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 2MHz)
- 3A Sinking Current Capability
The ISL6594A drives the upper gate to 12V, while the lower
gate can be independently driven over a range from 5V to
12V. The ISL6594B drives both upper and lower gates over
a range of 5V to 12V. This drive-voltage provides the
flexibility necessary to optimize applications involving
trade-offs between gate charge and conduction losses.
- Fast Rise/Fall Times and Low Propagation Delays
• Three-State PWM Input for Output Stage Shutdown
• Three-State PWM Input Hysteresis for Applications with
Power Sequencing Requirement
An adaptive zero shoot-through protection is integrated to
prevent both the upper and lower MOSFETs from conducting
simultaneously and to minimize the dead time. These
products add an overvoltage protection feature operational
before VCC exceeds its turn-on threshold, at which the
PHASE node is connected to the gate of the low side
MOSFET (LGATE). The output voltage of the converter is
then limited by the threshold of the low side MOSFET, which
provides some protection to the microprocessor if the upper
MOSFET(s) is shorted during initial start-up.
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free Available (RoHS Compliant)
These drivers also feature a three-state PWM input which,
working together with Intersil’s multi-phase PWM controllers,
prevents a negative transient on the output voltage when the
output is shut down. This feature eliminates the Schottky
diode that is used in some systems for protecting the load
from reversed output voltage events.
Applications
• Core Regulators for Intel® and AMD® Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 for Power Train Design, Layout
Guidelines, and Feedback Compensation Design
FN9157 Rev 6.00
Sep 11, 2015
Page 1 of 11
ISL6594A, ISL6594B
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL6594ACRZ* (Note)
ISL6594BCBZ* (Note)
94AZ
6594 BCBZ
0 to +85
0 to +85
10 Ld 3x3 DFN
8 Ld SOIC
L10.3x3
M8.15
(No longer available, recommended replacement: ISL6594ACRZ-T)
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
Pinouts
ISL6594ACB, ISL6594BCB
(8 LD SOIC)
ISL6594ACR, ISL6594BCR
(10 LD 3x3 DFN)
TOP VIEW
TOP VIEW
UGATE
PHASE
UGATE
BOOT
PWM
1
2
3
4
8
7
6
5
PHASE
PVCC
VCC
1
2
3
4
5
10
9
BOOT
N/C
PVCC
N/C
8
PWM
GND
7
VCC
GND
LGATE
6
LGATE
Block Diagram
ISL6594A AND ISL6594B
BOOT
UVCC
VCC
UGATE
PRE-POR OVP
FEATURES
+5V
PHASE
PVCC
SHOOT-
THROUGH
(LVCC)
13.6k
PROTECTION
UVCC = VCC FOR ISL6594A
UVCC = PVCC FOR ISL6594B
PWM
POR/
CONTROL
LOGIC
LGATE
GND
6.4k
FOR DFN -DEVICES, THE PAD ON THE BOTTOM SIDE OF
PAD
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
FN9157 Rev 6.00
Sep 11, 2015
Page 2 of 11
Typical Application - 4-Channel Converter Using ISL6592 and ISL6594A Gate Drivers
+12V
ISL6594
+5V
1 UGATE PHASE 8
2
3
4
7
6
5
BOOT
PWM
GND
PVCC
VCC
LGATE
VDD
V12_SEN
GND
+3.3V
ISL6594
1 UGATE PHASE 8
ISL6592
OUT1
2 BOOT
PVCC 7
VID4
VID3
VID2
VID1
VID0
VID5
LL0
OUT2
3
4
6
5
PWM
GND
VCC
ISEN1
OUT3
OUT4
ISEN2
LGATE
FROM µP
VOUT
ISL6594
1 UGATE PHASE 8
OUT5
OUT6
2
3
4
7
6
5
BOOT
PWM
GND
PVCC
VCC
ISEN3
LL1
OUTEN
OUT7
LGATE
OUT8
RTN
TO µP
VCC_PWRGD
RESET_N
ISEN4
OUT9
OUT10
ISL6594
UGATE PHASE
1
2
3
4
8
7
6
5
ISEN5
BOOT
PWM
GND
PVCC
VCC
FAULT1
FAULT2
OUT11
FAULT
OUTPUTS
OUT12
LGATE
ISEN6
TEMP_SEN
CAL_CUR_EN
SDA
2
RTHERM
I C I/F
BUS
SCL
SADDR
CAL_CUR_SEN
VSENP
VSENN
ISL6594A, ISL6594B
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
Thermal Resistance
(°C/W)
(°C/W)
JC
JA
SOIC Package (Note 1) . . . . . . . . . . . .
DFN Package (Notes 2, 3). . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
100
48
N/A
7
BOOT Voltage (V
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
BOOT
Input Voltage (V
) . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V
PWM
UGATE. . . . . . . . . . . . . . . . . . . V
- 0.3V
to V
+ 0.3V
+ 0.3V
+ 0.3V
+ 0.3V
= 12V)
PHASE
DC
BOOT
BOOT
PVCC
PVCC
V
- 3.5V (<100ns Pulse Width, 2µJ) to V
PHASE
LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V
to V
DC
GND - 5V (<100ns Pulse Width, 2µJ) to V
PHASE. . . . . . . . . . . . . . . GND - 0.3V to 15V (V
DC DC PVCC
Recommended Operating Conditions
GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT - GND < 36V)
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to +85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V ±10%
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V ±10%
CC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. is measured with the component mounted on a high effective thermal conductivity test board in free air.
JA
2. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
3. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
VCC SUPPLY CURRENT
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Bias Supply Current
I
I
ISL6594A, f
ISL6594B, f
ISL6594A, f
ISL6594B, f
ISL6594A, f
ISL6594B, f
ISL6594A, f
ISL6594B, f
= 300kHz, V
= 300kHz, V
= 12V
= 12V
-
-
-
-
-
-
-
-
8
4.5
10.5
5
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
VCC
VCC
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
VCC
VCC
= 1MHz, V
= 1MHz, V
= 12V
VCC
VCC
= 12V
Gate Drive Bias Current
I
I
= 300kHz, V
= 300kHz, V
= 12V
4
PVCC
PVCC
= 12V
7.5
5
PVCC
= 1MHz, V
= 1MHz, V
= 12V
= 12V
PVCC
(Note 4)
PVCC
PVCC
8.5
POWER-ON RESET AND ENABLE
VCC Rising Threshold
9.35
7.35
9.8
7.6
10.0
8.0
V
V
VCC Falling Threshold
PWM INPUT (See Timing Diagram on page 6)
Input Current
I
V
V
V
V
V
V
V
V
V
= 3.3V
-
505
-460
1.70
1.30
-
-
µA
µA
V
PWM
PWM
PWM
= 0V
-
-
PWM Rising Threshold (Note 4)
PWM Falling Threshold (Note 4)
Typical Three-State Shutdown Window
Three-State Lower Gate Falling Threshold
Three-State Lower Gate Rising Threshold
Three-State Upper Gate Rising Threshold
Three-State Upper Gate Falling Threshold
Shutdown Hold-off Time
= 12V
= 12V
= 12V
= 12V
= 12V
= 12V
= 12V
-
-
CC
CC
CC
CC
CC
CC
CC
-
-
V
1.23
1.82
V
-
-
-
-
-
-
1.18
0.76
2.36
1.96
245
26
-
-
-
-
-
-
V
V
V
V
t
ns
ns
TSSHD
UGATE Rise Time
t
V
= 12V, 3nF Load, 10% to 90%
PVCC
RU
FN9157 Rev 6.00
Sep 11, 2015
Page 4 of 11
ISL6594A, ISL6594B
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
LGATE Rise Time
SYMBOL
TEST CONDITIONS
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load
MIN
TYP
18
18
12
10
10
10
10
10
MAX
UNITS
ns
t
V
V
V
V
V
V
V
V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RL
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
UGATE Fall Time (Note 4)
t
ns
FU
LGATE Fall Time (Note 4)
t
ns
FL
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Three-State Propagation Delay (Note 4)
OUTPUT
t
t
ns
PDHU
t
ns
PDHL
PDLU
ns
t
= 12V, 3nF Load
ns
PDLL
t
= 12V, 3nF Load
ns
PDTS
Upper Drive Source Current (Note 4)
Upper Drive Source Impedance
Upper Drive Sink Current (Note 4)
Upper Drive Sink Impedance
I
V
= 12V, 3nF Load
-
1.4
-
1.25
2.0
2
-
3.0
-
A
A
A
A
U_SOURCE
PVCC
R
150mA Source Current
U_SOURCE
I
V
= 12V, 3nF Load
U_SINK
PVCC
150mA Sink Current
V = 12V, 3nF Load
R
0.9
-
1.65
2
3.0
-
U_SINK
Lower Drive Source Current (Note 4)
Lower Drive Source Impedance
Lower Drive Sink Current (Note 4)
Lower Drive Sink Impedance
I
L_SOURCE
PVCC
150mA Source Current
R
0.85
-
1.3
3
2.2
-
L_SOURCE
I
V
= 12V, 3nF Load
L_SINK
PVCC
R
150mA Sink Current
0.60
0.94
1.35
L_SINK
NOTE:
4. Limits should be considered typical and are not production tested.
Functional Pin Description
PACKAGE PIN #
PIN
SOIC
DFN
SYMBOL
FUNCTION
1
2
1
2
UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
BOOT
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 7 for guidance in choosing the capacitor value.
-
3, 8
4
N/C
No Connection.
3
PWM
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
“Three-State PWM Input” on page 6 for further details. Connect this pin to the PWM output of the controller.
4
5
6
7
5
6
7
9
GND
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
VCC
Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
PVCC
This pin supplies power to both upper and lower gate drives in ISL6594B; only the lower gate drive in ISL6594A.
Its operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.
8
9
10
11
PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
PAD
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
FN9157 Rev 6.00
Sep 11, 2015
Page 5 of 11
ISL6594A, ISL6594B
Description
1.18V < PWM < 2.36V
0.76V < PWM < 1.96V
PWM
t
t
PDLU
PDHU
t
TSSHD
t
PDTS
t
PDTS
t
FU
UGATE
LGATE
t
RU
t
t
FL
RL
t
t
TSSHD
PDLL
t
PDHL
FIGURE 1. TIMING DIAGRAM
Operation
Adaptive Zero Shoot-Through Deadtime Control
Designed for versatility and speed, the ISL6594A and
ISL6594B MOSFET drivers control both high-side and low-side
N-Channel FETs of a half-bridge power train from one
externally provided PWM signal.
These drivers incorporate an adaptive deadtime control
technique to minimize deadtime, resulting in high efficiency
from the reduced freewheeling time of the lower MOSFETs’
body-diode conduction, and to prevent the upper and lower
MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other
has turned off.
Prior to VCC exceeding its POR level, the Pre-POR
overvoltage protection function is activated during initial
start-up; the upper gate (UGATE) is held low and the lower
gate (LGATE), controlled by the Pre-POR overvoltage
protection circuits, is connected to the PHASE. Once the
VCC voltage surpasses the VCC Rising Threshold (See
“Electrical Specifications” on page 4), the PWM signal takes
control of gate transitions. A rising edge on PWM initiates
the turn-off of the lower MOSFET (see “Timing Diagram” on
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it drops below 1.75V, at which time the
UGATE is released to rise after 20ns of propagation delay.
Once the PHASE is high, the adaptive shoot-through
circuitry monitors the PHASE and UGATE voltages during a
PWM falling edge and the subsequent UGATE turn-off. If
either the UGATE falls to less than 1.75V above the PHASE
or the PHASE falls to less than +0.8V, the LGATE is
released to turn on.
page 6). After a short propagation delay [t
], the lower
PDLL
gate begins to fall. Typical fall times [t ] are provided in
FL
“Electrical Specifications” on page 4. Adaptive shoot-through
circuitry monitors the LGATE voltage and determines the
upper gate delay time [t
and upper MOSFETs from conducting simultaneously. Once
this delay period is complete, the upper gate drive begins to
]. This prevents both the lower
PDHU
Three-State PWM Input
A unique feature of these drivers and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set hold off time, the driver outputs are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the “Electrical Specifications” on
page 4 determine when the lower and upper gates are
enabled.
rise [t ] and the upper MOSFET turns on.
RU
A falling transition on PWM results in the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
] is encountered before the upper
PDLU
gate begins to fall [t ]. Again, the adaptive shoot-through
FU
circuitry determines the lower gate delay time, t
. The
PDHL
PHASE voltage and the UGATE voltage are monitored, and
the lower gate is allowed to rise after PHASE drops below a
level or the voltage of UGATE to PHASE reaches a level
depending upon the current direction (See next section for
details). The lower gate then rises [t ], turning on the lower
MOSFET.
This feature helps prevent a negative transient on the output
voltage when the output is shut down, eliminating the
Schottky diode that is used in some systems for protecting
the load from reversed output voltage events.
RL
FN9157 Rev 6.00
Sep 11, 2015
Page 6 of 11
ISL6594A, ISL6594B
In addition, more than 400mV hysteresis also incorporates
into the three-state shutdown window to eliminate PWM
input oscillations due to the capacitive load seen by the
PWM input through the body diode of the controller’s PWM
output when the power-up and/or power-down sequence of
bias supplies of the driver and PWM controller are required.
As an example, suppose two IRLR7821 FETs are chosen as
the upper MOSFETs. The gate charge, Q , from the data
G
sheet is 10nC at 4.5V (V ) gate-source voltage. Then the
GS
Q
is calculated to be 53nC for UVCC (i.e. PVCC in
GATE
ISL6594B, VCC in ISL6594A) = 12V. We will assume a
200mV droop in drive voltage over the PWM cycle. We find
that a bootstrap capacitance of at least 0.267F is required.
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds 9.8V (typically),
operation of the driver is enabled and the PWM input signal
takes control of the gate drives. If VCC drops below the
falling threshold of 7.6V (typically), operation of the driver is
disabled.
1.6
1.4
1.2
1.0
0.8
0.6
Pre-POR Overvoltage Protection
For the ISL6594A, prior to VCC exceeding its POR level, the
upper gate is held low. For the ISL6594B, the upper gate
driver is powered from PVCC and will be held low when a
voltage of 2.75V or higher is present on PVCC as VCC
surpasses its POR threshold. For both devices, the lower
gate is controlled by the overvoltage protection circuits
during initial start-up. The PHASE is connected to the gate of
the low side MOSFET (LGATE), which provides some
protection to the microprocessor if the upper MOSFET(s) is
shorted during initial start-up. For complete protection, the
low side MOSFET should have a gate threshold well below
the maximum voltage rating of the load/microprocessor.
Q
= 100nC
GATE
0.4
50nC
0.2
0.0
20nC
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
V (V)
BOOT_CAP
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
When VCC drops below its POR level, both gates pull low
and the Pre-POR overvoltage protection circuits are not
activated until VCC resets.
The ISL6594A and ISL6594B provide the user flexibility in
choosing the gate drive voltage for efficiency optimization.
The ISL6594A upper gate drive is fixed to VCC [+12V], but
the lower drive rail can range from 12V down to 5V
depending on what voltage is applied to PVCC. The
ISL6594B ties the upper and lower drive rails together.
Simply applying a voltage from 5V up to 12V on PVCC sets
both gate drive rail voltages simultaneously.
Internal Bootstrap Device
Both drivers feature an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces voltage
stress on the boot to phase pins.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (f ), the output drive impedance, the
SW
The bootstrap capacitor must have a maximum voltage
rating above UVCC + 5V and its capacitance value can be
chosen from Equation 1:
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
+125°C. The maximum allowable IC power dissipation for
the SO8 package is approximately 800mW at room
temperature, while the power dissipation capacity in the DFN
package with an exposed heat escape pad is more than
1.5W. The DFN package is more suitable for high frequency
applications. See “Layout Considerations” on page 8 for
thermal transfer improvement suggestions. When designing
the driver into an application, it is recommended that the
following calculation is used to ensure safe operation at the
Q
GATE
-------------------------------------
C
BOOT_CAP
V
BOOT_CAP
(EQ. 1)
Q
UVCC
G1
-----------------------------------
Q
=
N
Q1
GATE
V
GS1
where Q is the amount of gate charge per upper MOSFET
G1
at V
gate-source voltage and N is the number of
GS1
control MOSFETs. The V
Q1
term is defined as the
BOOT_CAP
allowable droop in the rail of the upper gate drive.
FN9157 Rev 6.00
Sep 11, 2015
Page 7 of 11
ISL6594A, ISL6594B
desired frequency for the selected MOSFETs. The total gate
drive power losses due to the gate charge of MOSFETs and
the driver’s internal circuitry and their corresponding average
driver current can be estimated with Equations 2 and 3,
respectively:
UVCC
BOOT
D
C
GD
R
HI1
G
C
DS
R
R
LO1
R
GI1
C
G1
(EQ. 2)
P
= P
+ P
+ I VCC
Q
Qg_TOT
Qg_Q1
Qg_Q2
2
GS
Q1
Q
UVCC
S
G1
---------------------------------------
P
=
f
N
Qg_Q1
SW
Q1
V
GS1
PHASE
2
Q
LVCC
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
G2
--------------------------------------
P
=
f
N
Qg_Q2
SW
Q2
V
GS2
LVCC
Q
UVCC N
Q
LVCC N
G2 Q2
G1
Q1
I
=
----------------------------------------------------- + ---------------------------------------------------- f
+ I
DR
SW
Q
D
V
V
GS2
GS1
C
(EQ. 3)
GD
R
HI2
G
C
DS
where the gate charge (Q and Q ) is defined at a
G1
G2
R
R
LO2
R
GI2
C
particular gate to source voltage (V
and V
) in the
G2
GS1
GS2
corresponding MOSFET datasheet; I is the driver’s total
GS
Q
Q2
quiescent current with no load at both drive outputs; N
Q1
S
and N are number of upper and lower MOSFETs,
Q2
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I VCC
product is the quiescent power of the driver without
capacitive load and is typically 116mW at 300kHz.
Q*
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Layout Considerations
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
resistors (R and R ) and the internal gate resistors
G1 G2
(R
GI1
and R ) of MOSFETs. Figures 3 and 4 show the
GI2
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as shown in Equation 4:
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
in between the power components is required for good
airflow. The traces from the drivers to the FETs should be
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.
P
P
= P
+ P
+ I VCC
(EQ. 4)
DR
DR_UP
DR_LOW
Q
P
R
R
Qg_Q1
HI1
LO1
---------------------
=
-------------------------------------- + ---------------------------------------
DR_UP
2
R
+ R
R
+ R
EXT1
HI1
EXT1
LO1
P
R
R
Qg_Q2
HI2
LO2
---------------------
P
R
=
-------------------------------------- + ---------------------------------------
DR_LOW
2
R
+ R
R
+ R
LO2 EXT2
HI2
EXT2
R
R
GI1
GI2
= R
+ -------------
R
= R
+ -------------
EXT1
G1
EXT2
G2
N
N
Q1
Q2
FN9157 Rev 6.00
Sep 11, 2015
Page 8 of 11
ISL6594A, ISL6594B
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
CHANGE
September 11, 2015
FN9157.6 Updated Ordering Information table on page 2.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing L10.3x3 to the latest revision.
-Revision 3 to Revision 4 changes - Add Typical Recommended Land Pattern
-Revision 4 to Revision 5 changes - Converted to newer standard
-Revision 5 to Revision 6 changes - Changed Note 4 from "Dimension b applies..." to "Lead width
applies...", Changed Note callout in Detail X from 4 to 5, Changed height in side view from 0.90 MAX to 1.00
MAX, Added Note 4 callout next to lead width in Bottom View, In Land Pattern, corrected lead shape for 4
corner pins to "L" shape (was rectangular and did not match bottom view)
-Revision 6 to Revision 7 changes - Removed package outline and included center to center distance
between lands on recommended land pattern. Removed Note 4 "Dimension b applies to the metallized
terminal and is measured between 0.18mm and 0.30mm from the terminal tip." since it is not applicable to
this package. Renumbered notes accordingly.
-Revision 7 to Revision 8 changes - Corrected L-shaped leads in Bottom view and land pattern so that
they align with the rest of the leads (L shaped leads were shorter)
-Revision 8 to Revision 9 changes - Added missing dimension 0.415 in Typical Recommended land
pattern.
-Revision 9 to Revision 10 changes - Shortened the e-pad rectangle on both the recommended land
pattern and the package bottom view to line up with the centers of the corner pins.
-Revision 10 to Revision 11 changes - Tiebar Note 4 updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2004-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9157 Rev 6.00
Sep 11, 2015
Page 9 of 11
ISL6594A, ISL6594B
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 11, 3/15
5
3.00
A
B
PIN #1 INDEX AREA
1
2
5
PIN 1
INDEX AREA
10 x 0.23
(4X)
0.10
1.60
10x 0.35
TOP VIEW
BOTTOM VIEW
A B
C
M
0.10
(4X)
0.415
0.23
0.35
SEE DETAIL "X"
0.10
(10 x 0.55)
(10x 0.23)
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
0.415
4
0.20 REF
0.05
C
1.60
2.85 TYP
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
5. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN9157 Rev 6.00
Sep 11, 2015
Page 10 of 11
ISL6594A, ISL6594B
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN9157 Rev 6.00
Sep 11, 2015
Page 11 of 11
相关型号：
ISL6594BCRZ
3A HALF BRDG BASED MOSFET DRIVER, PDSO10, 3 X 3 MM, ROHS COMPLIANT, PLASTIC, DFN-10
RENESAS
ISL6594BCRZ-T
3A HALF BRDG BASED MOSFET DRIVER, PDSO10, 3 X 3 MM, ROHS COMPLIANT, PLASTIC, DFN-10
RENESAS
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