ISL6612BEIB-T [RENESAS]
3A HALF BRDG BASED MOSFET DRIVER, PDSO8, PLASTIC, SOIC-8;
| 型号： | ISL6612BEIB-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 3A HALF BRDG BASED MOSFET DRIVER, PDSO8, PLASTIC, SOIC-8 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总12页 (文件大小：615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
NOT RECOMMENDED FOR NEW DESIGNS
RECOMMENDED REPLACEMENT PARTS
ISL6622A, ISL6622B
ISL6612B, ISL6613B
Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP
FN9205
Rev.4.00
May 1, 2012
The ISL6612B and ISL6613B are high frequency MOSFET
drivers specifically designed to drive upper and lower power
Features
• Pin-to-pin Compatible with HIP6601 SOIC family
N-Channel MOSFETs in a synchronous rectified buck
converter topology. These drivers combined with HIP63xx or
ISL65xx Multi-Phase Buck PWM controllers and N-Channel
MOSFETs form complete core-voltage regulator solutions for
advanced microprocessors.
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Low VCC Rising Threshold (7V) for IBA Applications.
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
The ISL6612B drives the upper gate to above rising VCC
POR (7V), while the lower gate can be independently driven
over a range from 5V to 12V. The ISL6613B drives both
upper and lower gates over a range of 5V to 12V. This drive-
voltage provides the flexibility necessary to optimize
applications involving trade-offs between gate charge and
conduction losses. These drivers are optimized for POL
DC/DC Converters for IBA Systems.
- Auto-zero of r
DS(ON)
Conduction Offset Effect
• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 2MHz)
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. These products add an overvoltage protection feature
operational before VCC exceeds its turn-on threshold, at
which the PHASE node is connected to the gate of the low
side MOSFET (LGATE). The output voltage of the converter
is then limited by the threshold of the low side MOSFET,
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during initial start-up.
• Three-State PWM Input for Output Stage Shutdown
• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• Dual Flat No-Lead (DFN) Package
These drivers also feature a three-state PWM input which,
working together with Intersil’s multi-phase PWM controllers,
prevents a negative transient on the output voltage when the
output is shut down. This feature eliminates the Schottky
diode that is used in some systems for protecting the load
from reversed output voltage events.
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free (RoHS Compliant)
Applications
• Optimized for POL DC/DC Converters for IBA Systems
®
®
• Core Regulators for Intel and AMD Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 for Power Train Design, Layout
Guidelines, and Feedback Compensation Design
FN9205 Rev.4.00
May 1, 2012
Page 1 of 12
ISL6612B, ISL6613B
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6612BCBZ
ISL6612BCRZ
ISL6612BECBZ
ISL6612BEIBZ
ISL6612BIBZ
ISL6612BIRZ
ISL6613BCBZ
ISL6613BCRZ
ISL6613BECBZ
ISL6613BEIBZ
ISL6613BIBZ
ISL6613BIRZ
NOTES:
6612 BCBZ
12BZ
0 to +85
0 to +85
8 Ld SOIC
M8.15
10 Ld 3x3 DFN
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld SOIC
L10.3x3
M8.15B
M8.15B
M8.15
6612 BECBZ
6612 BEIBZ
6612 BIBZ
2BIZ
0 to +85
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0 to +85
10 Ld 3x3 DFN
8 Ld SOIC
L10.3x3
M8.15
6613 BCBZ
13BZ
0 to +85
10 Ld 3x3 DFN
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld SOIC
L10.3x3
M8.15B
M8.15B
M8.15
6613 BECBZ
6613 BEIBZ
6613 BIBZ
3BIZ
0 to +85
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
10 Ld 3x3 DFN
L10.3x3
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6612B, ISL6613B. For more information on MSL, please see
Technical Brief TB363.
Pinouts
ISL6612BCB, ISL6613BCB, ISL6612BECB, ISL6613BECB
(8 LD SOIC, EPSOIC)
ISL6612BCR, ISL6613BCR
(10 LD 3x3 DFN)
TOP VIEW
TOP VIEW
UGATE
BOOT
PWM
1
2
3
4
8
7
6
5
PHASE
PVCC
VCC
1
2
3
4
5
10
9
UGATE
BOOT
PHASE
GND
PVCC
N/C
GND
8
N/C
PWM
GND
LGATE
7
VCC
6
GND
LGATE
FN9205 Rev.4.00
May 1, 2012
Page 2 of 12
ISL6612B, ISL6613B
Block Diagram
ISL6612B AND ISL6613B
UVCC
BOOT
VCC
UGATE
PRE-POR OVP
FEATURES
+5V
PHASE
PVCC
SHOOT-
THROUGH
(LVCC)
10K
PROTECTION
UVCC = VCC FOR ISL6612B
UVCC = PVCC FOR ISL6613B
POR/
CONTROL
LOGIC
PWM
LGATE
GND
8K
FOR DFN AND EPSOIC-DEVICES, THE PAD ON THE BOTTOM SIDE OF
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
PAD
FN9205 Rev.4.00
May 1, 2012
Page 3 of 12
ISL6612B, ISL6613B
Typical Application - 3 Channel Converter Using ISL65xx and ISL6612B Gate Drivers
+7V to +12V
+5V TO 12V
BOOT
UGATE
VCC
PVCC
PWM
PHASE
LGATE
ISL6612B
GND
+7V to +12V
+5V TO 12V
+5V
+V
CORE
VCC
BOOT
VCC
VFB
COMP
PWM1
UGATE
PHASE
PVCC
PWM
VSEN
ISL6612B
PWM2
PWM3
PGOOD
LGATE
MAIN
GND
CONTROL
ISL65xx
VID
ISEN1
ISEN2
ISEN3
FS
+7V to +12V
+5V TO 12V
GND
BOOT
VCC
UGATE
PHASE
PVCC
PWM
ISL6612B
LGATE
GND
FN9205 Rev.4.00
May 1, 2012
Page 4 of 12
ISL6612B, ISL6613B
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
Thermal Resistance
(°C/W)
(°C/W)
JC
JA
SOIC Package (Note 4) . . . . . . . . . . . .
EPSOIC Package (Notes 5, 6). . . . . . .
DFN Package (Notes 5, 6). . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
100
50
48
N/A
7
7
BOOT Voltage (V
). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
BOOT-GND
) . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V
Input Voltage (V
PWM
UGATE. . . . . . . . . . . . . . . . . . . V
- 0.3V
to V
+ 0.3V
+ 0.3V
+ 0.3V
+ 0.3V
PHASE
DC
BOOT
BOOT
V
- 3.5V (<100ns Pulse Width, 2µJ) to V
PHASE
LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V
to V
DC
GND - 5V (<100ns Pulse Width, 2µJ) to V
PVCC
PVCC
PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V
to 15V
DC
DC
GND - 8V (<400ns, 20µJ) to 30V (<200ns, V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
<36V)
BOOT-GND
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V to 13.2V
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V 10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. is measured with the component mounted on a high effective thermal conductivity test board in free air.
JA
5. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
6. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating
temperature range.
MIN
MAX
PARAMETER
VCC SUPPLY CURRENT
SYMBOL
TEST CONDITIONS
(Note 8)
TYP
(Note 8) UNITS
Bias Supply Current
I
I
ISL6612B, f
ISL6613B, f
ISL6612B, f
ISL6613B, f
ISL6612B, f
ISL6613B, f
ISL6612B, f
ISL6613B, f
= 300kHz, V
= 300kHz, V
=12V
=12V
-
-
-
-
-
-
-
-
8
4.5
10.5
5
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
VCC
VCC
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
VCC
VCC
= 1MHz, V
= 1MHz, V
= 12V
= 12V
VCC
VCC
Gate Drive Bias Current
I
I
= 300kHz, V
= 300kHz, V
=12V
4
PVCC
PVCC
PVCC
PVCC
=12V
7.5
5
= 1MHz, V
= 1MHz, V
= 12V
= 12V
PVCC
PVCC
8.5
POWER-ON RESET AND ENABLE
VCC Rising Threshold
0°C to +85°C
-40°C to +85°C
0°C to +85°C
-40°C to +85°C
6.75
5.75
5.20
4.20
6.92
5.44
7.10
7.10
5.60
5.60
V
V
V
V
VCC Falling Threshold
PWM INPUT (See Timing Diagram on page 7)
Input Current
I
V
V
= 5V
= 0V
-
500
-450
3.00
2.00
-
µA
µA
V
PWM
PWM
PWM
-
-
PWM Rising Threshold
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
-
-
-
-
PWM Falling Threshold
V
Typical Three-State Shutdown Window
Three-State Lower Gate Falling Threshold
Three-State Lower Gate Rising Threshold
Three-State Upper Gate Rising Threshold
1.80
2.40
V
1.50
1.00
3.20
V
V
V
FN9205 Rev.4.00
May 1, 2012
Page 5 of 12
ISL6612B, ISL6613B
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating
temperature range. (Continued)
MIN
MAX
PARAMETER
Three-State Upper Gate Falling Threshold
Shutdown Holdoff Time
SYMBOL
TEST CONDITIONS
VCC = 12V
(Note 8)
TYP
2.60
245
26
(Note 8) UNITS
V
t
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSSHD
UGATE Rise Time
t
V
V
V
V
V
V
V
V
V
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load
RU
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
LGATE Rise Time
t
18
RL
FU
UGATE Fall Time
t
18
LGATE Fall Time
t
12
FL
UGATE Turn-On Propagation Delay (Note 7)
LGATE Turn-On Propagation Delay (Note 7)
UGATE Turn-Off Propagation Delay (Note 7)
LGATE Turn-Off Propagation Delay (Note 7)
LG/UG Three-State Propagation Delay (Note 7)
OUTPUT (Note 7)
t
10
PDHU
t
10
PDHL
PDLU
t
t
10
t
= 12V, 3nF Load
10
PDLL
= 12V, 3nF Load
10
PDTS
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
I
V
= 12V, 3nF Load
-
1.25
-
1.25
2.0
2
-
3.0
-
A
U_SOURCE
PVCC
R
150mA Source Current
U_SOURCE
I
V
= 12V, 3nF Load
U_SINK
PVCC
150mA Source Current
V = 12V, 3nF Load
Upper Drive DC Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
R
0.9
-
1.6
2
3.0
-
U_SINK
I
L_SOURCE
PVCC
150mA Source Current
R
0.85
-
1.35
3
2.2
-
A
L_SOURCE
I
V
= 12V, 3nF Load
L_SINK
PVCC
Lower Drive Sink Impedance
NOTE:
R
150mA Sink Current
0.60
0.80
1.35
L_SINK
7. Limits established by characterization and are not production tested.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Functional Pin Description
PACKAGE PIN #
PIN
SOIC
DFN
SYMBOL
FUNCTION
1
2
1
2
UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
BOOT
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 8 for guidance in choosing the capacitor value.
-
3, 8
4
N/C
No Connection.
3
PWM
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
the “Three-State PWM Input” on page 7 for further details. Connect this pin to the PWM output of the controller.
4
5
6
7
5
6
7
9
GND
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
VCC
Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
PVCC
This pin supplies power to both upper and lower gate drives in ISL6613B; only the lower gate drive in ISL6612B.
Its operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.
8
9
10
11
PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
PAD
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
FN9205 Rev.4.00
May 1, 2012
Page 6 of 12
ISL6612B, ISL6613B
Description
1.5V<PWM<3.2V
1.0V<PWM<2.6V
PWM
t
t
PDLU
PDHU
t
TSSHD
t
PDTS
t
PDTS
t
FU
UGATE
LGATE
t
RU
t
t
FL
RL
t
t
TSSHD
PDLL
t
PDHL
FIGURE 1. TIMING DIAGRAM
Operation
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
Designed for versatility and speed, the ISL6612B and
ISL6613B MOSFET drivers control both high-side and low-side
N-Channel FETs of a half-bridge power train from one
externally provided PWM signal.
These drivers incorporate a unique adaptive deadtime control
technique to minimize deadtime, resulting in high efficiency
from the reduced freewheeling time of the lower MOSFETs’
body-diode conduction, and to prevent the upper and lower
MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
Prior to VCC exceeding its POR level, the Pre-POR over-
voltage protection function is activated during initial start-up; the
upper gate (UGATE) is held low and the lower gate (LGATE),
controlled by the Pre-POR overvoltage protection circuits, is
connected to the PHASE. Once the VCC voltage surpasses the
VCC Rising Threshold (See “Electrical Specifications” on
page 5), the PWM signal takes control of gate transitions. A
rising edge on PWM initiates the turn-off of the lower MOSFET
(see Timing Diagram on page 7). After a short propagation
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.2V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is released
to rise. An auto-zero comparator is used to correct the r
DS(ON)
delay [t
], the lower gate begins to fall. Typical fall times
drop in the phase voltage preventing from false detection of the
-0.2V phase level during r conduction period. In the case
PDLL
[t ] are provided in the “Electrical Specifications” section.
FL
DS(ON
Adaptive shoot-through circuitry monitors the PHASE voltage
of zero current, the UGATE is released after 35ns delay of the
LGATE dropping below 0.5V. During the phase detection, the
disturbance of LGATE’s falling transition on the PHASE node is
blanked out to prevent falsely tripping. Once the PHASE is
high, the advanced adaptive shoot-through circuitry monitors
the PHASE and UGATE voltages during a PWM falling edge
and the subsequent UGATE turn-off. If either the UGATE falls
to less than 1.75V above the PHASE or the PHASE falls to less
than +0.8V, the LGATE is released to turn on.
and determines the upper gate delay time [t
]. This
PDHU
prevents both the lower and upper MOSFETs from conducting
simultaneously. Once this delay period is complete, the upper
gate drive begins to rise [t ] and the upper MOSFET turns on.
RU
A falling transition on PWM results in the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
] is encountered before the upper
PDLU
gate begins to fall [t ]. Again, the adaptive shoot-through
FU
circuitry determines the lower gate delay time, t
. The
Three-State PWM Input
PDHL
PHASE voltage and the UGATE voltage are monitored, and
the lower gate is allowed to rise after PHASE drops below a
level or the voltage of UGATE to PHASE reaches a level
depending upon the current direction (See next section for
A unique feature of these drivers and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the driver outputs are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the “Electrical Specifications”
details). The lower gate then rises [t ], turning on the lower
RL
MOSFET.
determine when the lower and upper gates are enabled.
FN9205 Rev.4.00
May 1, 2012
Page 7 of 12
ISL6612B, ISL6613B
This feature helps prevent a negative transient on the output
voltage when the output is shut down, eliminating the
Schottky diode that is used in some systems for protecting
the load from reversed output voltage events.
As an example, suppose two IRLR7821 FETs are chosen as
the upper MOSFETs. The gate charge, Q , from the data
G
sheet is 10nC at 4.5V (V ) gate-source voltage. Then the
GS
Q
is calculated to be 53nC for UVCC (i.e. PVCC in
GATE
ISL6613B, VCC in ISL6612B) =12V. We will assume a
200mV droop in drive voltage over the PWM cycle. We find
that a bootstrap capacitance of at least 0.267F is required.
1.6
In addition, more than 400mV hysteresis also incorporates
into the three-state shutdown window to eliminate PWM
input oscillations due to the capacitive load seen by the
PWM input through the body diode of the controller’s PWM
output when the power-up and/or power-down sequence of
bias supplies of the driver and PWM controller are required.
1.4
1.2
1.
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds 6.9V (typically),
operation of the driver is enabled and the PWM input signal
takes control of the gate drives. If VCC drops below the
falling threshold of 5.6V (typically), operation of the driver is
disabled.
0.8
0.6
Q
= 100nC
GATE
0.4
50nC
Pre-POR Overvoltage Protection
0.2
0.0
20nC
Prior to VCC exceeding its POR level, the upper gate is held
low and the lower gate is controlled by the overvoltage
protection circuits during initial startup. The PHASE is
connected to the gate of the low side MOSFET (LGATE),
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during initial start-up. For
complete protection, the low side MOSFET should have a
gate threshold well below the maximum voltage rating of the
load/microprocessor.
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
V (V)
BOOT_CAP
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The ISL6612B and ISL6613B provide the user flexibility in
choosing the gate drive voltage for efficiency optimization.
The ISL6612B upper gate drive can be driven above VCC
rising POR (7V) to 12V, but the lower drive rail can range
from 12V down to 5V depending on what voltage is applied
to PVCC. The ISL6613B ties the upper and lower drive rails
together. Simply applying a voltage from 5V up to 12V on
PVCC sets both gate drive rail voltages simultaneously.
When VCC drops below its POR level, both gates pull low
and the Pre-POR overvoltage protection circuits are not
activated until VCC resets.
Internal Bootstrap Device
Both drivers feature an internal bootstrap schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces voltage
stress on the boot to phase pins.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F ), the output drive impedance, the
SW
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
+125°C. The maximum allowable IC power dissipation for
the SO8 package is approximately 800mW at room
The bootstrap capacitor must have a maximum voltage
rating above UVCC + 5V and its capacitance value can be
chosen from the following equation:
Q
GATE
-------------------------------------
C
BOOT_CAP
V
BOOT_CAP
(EQ. 1)
temperature, while the power dissipation capacity in the
EPSOIC and DFN packages, with an exposed heat escape
pad, is more than 2W and 1.5W, respectively. Both EPSOIC
and DFN packages are more suitable for high frequency
applications. See Layout Considerations paragraph for
thermal transfer improvement suggestions. When designing
the driver into an application, it is recommended that the
following calculation is used to ensure safe operation at the
Q
UVCC
G1
-----------------------------------
Q
=
N
Q1
GATE
V
GS1
where Q is the amount of gate charge per upper MOSFET
G1
at V
gate-source voltage and N is the number of
GS1
control MOSFETs. The V
Q1
term is defined as the
BOOT_CAP
allowable droop in the rail of the upper gate drive.
FN9205 Rev.4.00
May 1, 2012
Page 8 of 12
ISL6612B, ISL6613B
desired frequency for the selected MOSFETs. The total gate
drive power losses due to the gate charge of MOSFETs and
the driver’s internal circuitry and their corresponding average
driver current can be estimated with Equations 2 and 3,
respectively,
UVCC
BOOT
D
C
GD
R
HI1
G
C
DS
R
R
LO1
R
GI1
C
(EQ. 2)
P
= P
+ P
+ I VCC
Q
G1
Qg_TOT
Qg_Q1
Qg_Q2
2
GS
Q1
Q
UVCC
G1
S
---------------------------------------
P
=
F
N
Qg_Q1
SW
Q1
V
GS1
PHASE
2
Q
LVCC
G2
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
--------------------------------------
P
=
F
N
Qg_Q2
SW
Q2
V
GS2
Q
UVCC N
Q
LVCC N
G2 Q2
LVCC
G1
Q1
----------------------------------------------------- ----------------------------------------------------
I
=
+
F
+ I
DR
SW
Q
V
V
GS2
GS1
D
(EQ. 3)
C
GD
R
HI2
G
where the gate charge (Q and Q ) is defined at a particular
G1
G2
and V
C
DS
gate to source voltage (V
) in the corresponding
GS1
GS2
R
R
LO2
R
GI2
C
G2
MOSFET datasheet; I is the driver’s total quiescent current
Q
GS
Q2
with no load at both drive outputs; N and N are the
Q1 Q2
S
number of upper and lower MOSFETs, respectively; UVCC
and LVCC are the drive voltages for both upper and lower
FETs, respectively. The I VCC product is the quiescent power
Q*
of the driver without capacitive load and is typically 116mW at
300kHz.
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Layout Considerations
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate resistors
For heat spreading, place copper underneath the IC whether it
has an exposed pad or not. The copper area can be extended
beyond the bottom area of the IC and/or connected to buried
copper plane(s) with thermal vias. This combination of vias for
vertical heat escape, extended copper plane, and buried
planes for heat spreading allows the IC to achieve its full
thermal potential.
(R and R ) and the internal gate resistors (R
G1 G2
and R )
GI2
GI1
of MOSFETs. Figures 3 and 4 show the typical upper and
lower gate drives turn-on transition path. The power dissipation
on the driver can be roughly estimated as:
Place each channel power component as close to each other
as possible to reduce PCB copper losses and PCB parasitics:
shortest distance between DRAINs of upper FETs and
SOURCEs of lower FETs; shortest distance between DRAINs
of lower FETs and the power ground. Thus, smaller amplitudes
of positive and negative ringing are on the switching edges of
the PHASE node. However, some space in between the power
components is required for good airflow. The traces from the
drivers to the FETs should be kept short and wide to reduce the
inductance of the traces and to promote clean drive signals.
P
P
= P
+ P
+ I VCC
(EQ. 4)
DR
DR_UP
DR_LOW
Q
R
R
P
Qg_Q1
HI1
LO1
-------------------------------------- --------------------------------------- ---------------------
=
+
DR_UP
R
+ R
R
+ R
EXT1
2
HI1
EXT1
LO1
R
R
P
Qg_Q2
HI2
LO2
-------------------------------------- --------------------------------------- ---------------------
P
R
=
+
DR_LOW
R
+ R
R
+ R
EXT2
2
HI2
EXT2
LO2
R
R
GI1
GI2
-------------
-------------
= R
+
R
= R +
G2
EXT1
G1
EXT2
N
N
Q1
Q2
FN9205 Rev.4.00
May 1, 2012
Page 9 of 12
ISL6612B, ISL6613B
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 6, 09/09
6
3.00
A
B
PIN #1 INDEX AREA
1
2
6
PIN 1
INDEX AREA
10 x 0.23
4
(4X)
0.10
1.60
10x 0.35
4
TOP VIEW
BOTTOM VIEW
C A B
M
0.10
(4X)
0.415
0.23
PACKAGE
OUTLINE
0.35
SEE DETAIL "X"
0.10
(10 x 0.55)
(10x 0.23)
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
5
0.20 REF
0.05
C
1.60
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN9205 Rev.4.00
May 1, 2012
Page 10 of 12
ISL6612B, ISL6613B
Small Outline Exposed Pad Plastic Packages (EPSOIC)
M8.15B
N
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.43
0.03
0.35
0.19
4.80
3.81
MAX
1.68
0.13
0.49
0.25
4.98
3.99
NOTES
A
A1
B
C
D
E
e
0.056
0.001
0.0138
0.0075
0.189
0.150
0.066
0.005
0.0192
0.0098
0.196
0.157
-
1
2
3
-
TOP VIEW
9
-
L
3
SEATING PLANE
A
4
-A-
D
o
0.050 BSC
1.27 BSC
-
h x 45
H
h
0.230
0.010
0.016
0.244
0.016
0.035
5.84
0.25
0.41
6.20
0.41
0.89
-
-C-
5
L
6
e
B
A1
C
N
8
8
7
0.10(0.004)
0°
-
8°
0°
-
8°
-
11
P
0.25(0.010) M
SIDE VIEW
C A M B S
0.094
0.094
2.387
2.387
P1
-
-
11
Rev. 5 8/10
NOTES:
1
2
3
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P1
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
N
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
P
BOTTOM VIEW
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: INCH. Converted millimeter dimensions
are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
FN9205 Rev.4.00
May 1, 2012
Page 11 of 12
ISL6612B, ISL6613B
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN9205 Rev.4.00
May 1, 2012
Page 12 of 12
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